1 /* 2 * Copyright 2002/03, Thomas Kurschel. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 */ 5 6 /* 7 PCI bus manager 8 */ 9 10 #ifndef _PCI2_H 11 #define _PCI2_H 12 13 #include <device_manager.h> 14 #include <PCI.h> 15 16 // currently, this structure is disabled to avoid collision with R5 header 17 #if 0 18 19 typedef struct pci_info { 20 ushort vendor_id; /* vendor id */ 21 ushort device_id; /* device id */ 22 uchar bus; /* bus number */ 23 uchar device; /* device number on bus */ 24 uchar function; /* function number in device */ 25 uchar revision; /* revision id */ 26 uchar class_api; /* specific register interface type */ 27 uchar class_sub; /* specific device function */ 28 uchar class_base; /* device type (display vs network, etc) */ 29 uchar line_size; /* cache line size in 32 bit words */ 30 uchar latency; /* latency timer */ 31 uchar header_type; /* header type */ 32 uchar bist; /* built-in self-test */ 33 uchar reserved; /* filler, for alignment */ 34 union { 35 struct { 36 ulong cardbus_cis; /* CardBus CIS pointer */ 37 ushort subsystem_id; /* subsystem (add-in card) id */ 38 ushort subsystem_vendor_id; /* subsystem (add-in card) vendor id */ 39 ulong rom_base; /* rom base address, viewed from host */ 40 ulong rom_base_pci; /* rom base addr, viewed from pci */ 41 ulong rom_size; /* rom size */ 42 ulong base_registers[6]; /* base registers, viewed from host */ 43 ulong base_registers_pci[6]; /* base registers, viewed from pci */ 44 ulong base_register_sizes[6]; /* size of what base regs point to */ 45 uchar base_register_flags[6]; /* flags from base address fields */ 46 uchar interrupt_line; /* interrupt line */ 47 uchar interrupt_pin; /* interrupt pin */ 48 uchar min_grant; /* burst period @ 33 Mhz */ 49 uchar max_latency; /* how often PCI access needed */ 50 } h0; 51 struct { 52 ulong base_registers[2]; /* base registers, viewed from host */ 53 ulong base_registers_pci[2]; /* base registers, viewed from pci */ 54 ulong base_register_sizes[2]; /* size of what base regs point to */ 55 uchar base_register_flags[2]; /* flags from base address fields */ 56 uchar primary_bus; 57 uchar secondary_bus; 58 uchar subordinate_bus; 59 uchar secondary_latency; 60 uchar io_base; 61 uchar io_limit; 62 ushort secondary_status; 63 ushort memory_base; 64 ushort memory_limit; 65 ushort prefetchable_memory_base; 66 ushort prefetchable_memory_limit; 67 ulong prefetchable_memory_base_upper32; 68 ulong prefetchable_memory_limit_upper32; 69 ushort io_base_upper16; 70 ushort io_limit_upper16; 71 ulong rom_base; /* rom base address, viewed from host */ 72 ulong rom_base_pci; /* rom base addr, viewed from pci */ 73 uchar interrupt_line; /* interrupt line */ 74 uchar interrupt_pin; /* interrupt pin */ 75 ushort bridge_control; 76 } h1; 77 } u; 78 } pci_info; 79 80 #endif 81 82 83 typedef struct pci_device_info *pci_device; 84 85 // Interface to one PCI device. 86 // Actually, this is a _function_ of a device only, but 87 // pci_function_module_info would be a bit non-intuitive 88 typedef struct pci_device_module_info { 89 driver_module_info info; 90 91 uint8 (*read_io_8)(pci_device device, int mapped_io_addr); 92 void (*write_io_8)(pci_device device, int mapped_io_addr, uint8 value); 93 uint16 (*read_io_16)(pci_device device, int mapped_io_addr); 94 void (*write_io_16)(pci_device device, int mapped_io_addr, uint16 value); 95 uint32 (*read_io_32)(pci_device device, int mapped_io_addr); 96 void (*write_io_32)(pci_device device, int mapped_io_addr, uint32 value); 97 98 uint32 (*read_pci_config)(pci_device device, 99 uchar offset, /* offset in configuration space */ 100 uchar size); /* # bytes to read (1, 2 or 4) */ 101 void (*write_pci_config)(pci_device device, 102 uchar offset, /* offset in configuration space */ 103 uchar size, /* # bytes to write (1, 2 or 4) */ 104 uint32 value); /* value to write */ 105 106 void *(*ram_address)(pci_device device, const void *physical_address_in_system_memory); 107 108 /* status_t (*allocate_iomem)( void *base, size_t len, const char *name ); 109 status_t (*release_iomem)( void *base, size_t len ); 110 111 status_t (*allocate_ioports)( uint16 ioport_base, size_t len, const char *name ); 112 status_t (*release_ioports)( uint16 ioport_base, size_t len );*/ 113 114 status_t (*get_pci_info)(pci_device device, struct pci_info *info); 115 116 status_t (*find_pci_capability)(pci_device device, 117 uchar cap_id, 118 uchar *offset); 119 } pci_device_module_info; 120 121 122 // directory of PCI drivers 123 #define PCI_DRIVERS_DIR "pci" 124 125 // attributes of PCI device nodes 126 // bus idx (uint8) 127 #define PCI_DEVICE_BUS_ITEM "pci/bus" 128 // device idx (uint8) 129 #define PCI_DEVICE_DEVICE_ITEM "pci/device" 130 // function idx (uint8) 131 #define PCI_DEVICE_FUNCTION_ITEM "pci/function" 132 133 // vendor id (uint16) 134 #define PCI_DEVICE_VENDOR_ID_ITEM "pci/vendor_id" 135 // device id (uint16) 136 #define PCI_DEVICE_DEVICE_ID_ITEM "pci/device_id" 137 // subsystem id (uint16) 138 #define PCI_DEVICE_SUBSYSTEM_ID_ITEM "pci/subsystem_id" 139 // subvendor id (uint16) 140 #define PCI_DEVICE_SUBVENDOR_ID_ITEM "pci/subvendor_id" 141 142 // device base class (uint8) 143 #define PCI_DEVICE_BASE_CLASS_ID_ITEM "pci/class/base_id" 144 // device subclass (uint8) 145 #define PCI_DEVICE_SUB_CLASS_ID_ITEM "pci/class/sub_id" 146 // device api (uint8) 147 #define PCI_DEVICE_API_ID_ITEM "pci/class/api_id" 148 149 150 // dynamic consumer patterns for PCI devices 151 #define PCI_DEVICE_DYNAMIC_CONSUMER_0 \ 152 PCI_DRIVERS_DIR "/" \ 153 "vendor %" PCI_DEVICE_VENDOR_ID_ITEM "%|" \ 154 ", device %" PCI_DEVICE_DEVICE_ID_ITEM "%|" \ 155 ", subsystem %" PCI_DEVICE_SUBSYSTEM_ID_ITEM "%|" \ 156 ", subvendor %" PCI_DEVICE_SUBVENDOR_ID_ITEM "%" 157 158 #define PCI_DEVICE_DYNAMIC_CONSUMER_1 \ 159 PCI_DRIVERS_DIR "/" \ 160 "base_class %" PCI_DEVICE_BASE_CLASS_ID_ITEM "%|" \ 161 ", sub_class %" PCI_DEVICE_SUB_CLASS_ID_ITEM "%|" \ 162 ", api %" PCI_DEVICE_API_ID_ITEM "%" 163 164 #endif 165