1 /* 2 ** Copyright 2002/03, Thomas Kurschel. All rights reserved. 3 ** Distributed under the terms of the OpenBeOS License. 4 */ 5 6 /* 7 PCI bus manager 8 */ 9 10 #ifndef _PCI2_H 11 #define _PCI2_H 12 13 #include <device_manager.h> 14 //#include "r5_wrapper.h" 15 #include <PCI.h> 16 17 // currently, this structure is disables to avoid collision with R5 header 18 #if 0 19 20 typedef struct pci_info { 21 ushort vendor_id; /* vendor id */ 22 ushort device_id; /* device id */ 23 uchar bus; /* bus number */ 24 uchar device; /* device number on bus */ 25 uchar function; /* function number in device */ 26 uchar revision; /* revision id */ 27 uchar class_api; /* specific register interface type */ 28 uchar class_sub; /* specific device function */ 29 uchar class_base; /* device type (display vs network, etc) */ 30 uchar line_size; /* cache line size in 32 bit words */ 31 uchar latency; /* latency timer */ 32 uchar header_type; /* header type */ 33 uchar bist; /* built-in self-test */ 34 uchar reserved; /* filler, for alignment */ 35 union { 36 struct { 37 ulong cardbus_cis; /* CardBus CIS pointer */ 38 ushort subsystem_id; /* subsystem (add-in card) id */ 39 ushort subsystem_vendor_id; /* subsystem (add-in card) vendor id */ 40 ulong rom_base; /* rom base address, viewed from host */ 41 ulong rom_base_pci; /* rom base addr, viewed from pci */ 42 ulong rom_size; /* rom size */ 43 ulong base_registers[6]; /* base registers, viewed from host */ 44 ulong base_registers_pci[6]; /* base registers, viewed from pci */ 45 ulong base_register_sizes[6]; /* size of what base regs point to */ 46 uchar base_register_flags[6]; /* flags from base address fields */ 47 uchar interrupt_line; /* interrupt line */ 48 uchar interrupt_pin; /* interrupt pin */ 49 uchar min_grant; /* burst period @ 33 Mhz */ 50 uchar max_latency; /* how often PCI access needed */ 51 } h0; 52 struct { 53 ulong base_registers[2]; /* base registers, viewed from host */ 54 ulong base_registers_pci[2]; /* base registers, viewed from pci */ 55 ulong base_register_sizes[2]; /* size of what base regs point to */ 56 uchar base_register_flags[2]; /* flags from base address fields */ 57 uchar primary_bus; 58 uchar secondary_bus; 59 uchar subordinate_bus; 60 uchar secondary_latency; 61 uchar io_base; 62 uchar io_limit; 63 ushort secondary_status; 64 ushort memory_base; 65 ushort memory_limit; 66 ushort prefetchable_memory_base; 67 ushort prefetchable_memory_limit; 68 ulong prefetchable_memory_base_upper32; 69 ulong prefetchable_memory_limit_upper32; 70 ushort io_base_upper16; 71 ushort io_limit_upper16; 72 ulong rom_base; /* rom base address, viewed from host */ 73 ulong rom_base_pci; /* rom base addr, viewed from pci */ 74 uchar interrupt_line; /* interrupt line */ 75 uchar interrupt_pin; /* interrupt pin */ 76 ushort bridge_control; 77 } h1; 78 } u; 79 } pci_info; 80 81 #endif 82 83 84 typedef struct pci_device_info *pci_device; 85 86 // Interface to one PCI device. 87 // Actually, this is a _function_ of a device only, but 88 // pci_function_module_info would be a bit non-intuitive 89 typedef struct pci_device_module_info { 90 pnp_driver_info dinfo; 91 92 uint8 (*read_io_8) (pci_device device, int mapped_io_addr); 93 void (*write_io_8) (pci_device device, int mapped_io_addr, uint8 value); 94 uint16 (*read_io_16) (pci_device device, int mapped_io_addr); 95 void (*write_io_16) (pci_device device, int mapped_io_addr, uint16 value); 96 uint32 (*read_io_32) (pci_device device, int mapped_io_addr); 97 void (*write_io_32) (pci_device device, int mapped_io_addr, uint32 value); 98 99 uint32 (*read_pci_config) ( 100 pci_device device, 101 uchar offset, /* offset in configuration space */ 102 uchar size /* # bytes to read (1, 2 or 4) */ 103 ); 104 void (*write_pci_config) ( 105 pci_device device, 106 uchar offset, /* offset in configuration space */ 107 uchar size, /* # bytes to write (1, 2 or 4) */ 108 uint32 value /* value to write */ 109 ); 110 111 void * (*ram_address) (pci_device device, const void *physical_address_in_system_memory); 112 113 /* status_t (*allocate_iomem)( void *base, size_t len, const char *name ); 114 status_t (*release_iomem)( void *base, size_t len ); 115 116 status_t (*allocate_ioports)( uint16 ioport_base, size_t len, const char *name ); 117 status_t (*release_ioports)( uint16 ioport_base, size_t len );*/ 118 } pci_device_module_info; 119 120 121 // type of PCI device 122 #define PCI_DEVICE_TYPE_NAME "pci/device/v1" 123 // directory of PCI drivers 124 #define PCI_DRIVERS_DIR "pci" 125 126 // attributes of PCI device nodes 127 // bus idx (uint8) 128 #define PCI_DEVICE_BUS_ITEM "pci/bus" 129 // device idx (uint8) 130 #define PCI_DEVICE_DEVICE_ITEM "pci/device" 131 // function idx (uint8) 132 #define PCI_DEVICE_FUNCTION_ITEM "pci/function" 133 134 // vendor id (uint16) 135 #define PCI_DEVICE_VENDOR_ID_ITEM "pci/vendor_id" 136 // device id (uint16) 137 #define PCI_DEVICE_DEVICE_ID_ITEM "pci/device_id" 138 // subsystem id (uint16) 139 #define PCI_DEVICE_SUBSYSTEM_ID_ITEM "pci/subsystem_id" 140 // subvendor id (uint16) 141 #define PCI_DEVICE_SUBVENDOR_ID_ITEM "pci/subvendor_id" 142 143 // device base class (uint16) 144 #define PCI_DEVICE_BASE_CLASS_ID_ITEM "pci/class/base_id" 145 // device subclass (uint16) 146 #define PCI_DEVICE_SUB_CLASS_ID_ITEM "pci/class/sub_id" 147 // device api (uint16) 148 #define PCI_DEVICE_API_ID_ITEM "pci/class/api_id" 149 150 151 // dynamic consumer patterns for PCI devices 152 #define PCI_DEVICE_DYNAMIC_CONSUMER_0 \ 153 PCI_DRIVERS_DIR "/" \ 154 "vendor %" PCI_DEVICE_VENDOR_ID_ITEM "%|" \ 155 ", device %" PCI_DEVICE_DEVICE_ID_ITEM "%|" \ 156 ", subsystem %" PCI_DEVICE_SUBSYSTEM_ID_ITEM "%|" \ 157 ", subvendor %" PCI_DEVICE_SUBVENDOR_ID_ITEM "%" 158 159 #define PCI_DEVICE_DYNAMIC_CONSUMER_1 \ 160 PCI_DRIVERS_DIR "/" \ 161 "base_class %" PCI_DEVICE_BASE_CLASS_ID_ITEM "%|" \ 162 ", sub_class %" PCI_DEVICE_SUB_CLASS_ID_ITEM "%|" \ 163 ", api %" PCI_DEVICE_API_ID_ITEM "%" 164 165 #endif 166