1 /******************************************************************************* 2 / 3 / File: PCI.h 4 / 5 / Description: Interface to the PCI bus. 6 / For more information, see "PCI Local Bus Specification, Revision 2.1", 7 / PCI Special Interest Group, 1995. 8 / 9 / Copyright 1993-98, Be Incorporated, All Rights Reserved. 10 / 11 *******************************************************************************/ 12 13 14 #ifndef _PCI_H 15 #define _PCI_H 16 17 //#include <BeBuild.h> 18 //#include <SupportDefs.h> 19 #include <bus_manager.h> 20 21 #ifdef __cplusplus 22 extern "C" { 23 #endif 24 25 26 /* ----- 27 pci device info 28 ----- */ 29 30 typedef struct pci_info { 31 ushort vendor_id; /* vendor id */ 32 ushort device_id; /* device id */ 33 uchar bus; /* bus number */ 34 uchar device; /* device number on bus */ 35 uchar function; /* function number in device */ 36 uchar revision; /* revision id */ 37 uchar class_api; /* specific register interface type */ 38 uchar class_sub; /* specific device function */ 39 uchar class_base; /* device type (display vs network, etc) */ 40 uchar line_size; /* cache line size in 32 bit words */ 41 uchar latency; /* latency timer */ 42 uchar header_type; /* header type */ 43 uchar bist; /* built-in self-test */ 44 uchar reserved; /* filler, for alignment */ 45 union { 46 struct { 47 ulong cardbus_cis; /* CardBus CIS pointer */ 48 ushort subsystem_id; /* subsystem (add-in card) id */ 49 ushort subsystem_vendor_id; /* subsystem (add-in card) vendor id */ 50 ulong rom_base; /* rom base address, viewed from host */ 51 ulong rom_base_pci; /* rom base addr, viewed from pci */ 52 ulong rom_size; /* rom size */ 53 ulong base_registers[6]; /* base registers, viewed from host */ 54 ulong base_registers_pci[6]; /* base registers, viewed from pci */ 55 ulong base_register_sizes[6]; /* size of what base regs point to */ 56 uchar base_register_flags[6]; /* flags from base address fields */ 57 uchar interrupt_line; /* interrupt line */ 58 uchar interrupt_pin; /* interrupt pin */ 59 uchar min_grant; /* burst period @ 33 Mhz */ 60 uchar max_latency; /* how often PCI access needed */ 61 } h0; 62 struct { 63 ulong base_registers[2]; /* base registers, viewed from host */ 64 ulong base_registers_pci[2]; /* base registers, viewed from pci */ 65 ulong base_register_sizes[2]; /* size of what base regs point to */ 66 uchar base_register_flags[2]; /* flags from base address fields */ 67 uchar primary_bus; 68 uchar secondary_bus; 69 uchar subordinate_bus; 70 uchar secondary_latency; 71 uchar io_base; 72 uchar io_limit; 73 ushort secondary_status; 74 ushort memory_base; 75 ushort memory_limit; 76 ushort prefetchable_memory_base; 77 ushort prefetchable_memory_limit; 78 ulong prefetchable_memory_base_upper32; 79 ulong prefetchable_memory_limit_upper32; 80 ushort io_base_upper16; 81 ushort io_limit_upper16; 82 ulong rom_base; /* rom base address, viewed from host */ 83 ulong rom_base_pci; /* rom base addr, viewed from pci */ 84 uchar interrupt_line; /* interrupt line */ 85 uchar interrupt_pin; /* interrupt pin */ 86 ushort bridge_control; 87 ushort subsystem_id; /* subsystem (add-in card) id */ 88 ushort subsystem_vendor_id; /* subsystem (add-in card) vendor id */ 89 } h1; 90 struct { 91 ushort subsystem_id; /* subsystem (add-in card) id */ 92 ushort subsystem_vendor_id; /* subsystem (add-in card) vendor id */ 93 } h2; 94 } u; 95 } pci_info; 96 97 98 typedef struct pci_module_info pci_module_info; 99 100 struct pci_module_info { 101 bus_manager_info binfo; 102 103 uint8 (*read_io_8) (int mapped_io_addr); 104 void (*write_io_8) (int mapped_io_addr, uint8 value); 105 uint16 (*read_io_16) (int mapped_io_addr); 106 void (*write_io_16) (int mapped_io_addr, uint16 value); 107 uint32 (*read_io_32) (int mapped_io_addr); 108 void (*write_io_32) (int mapped_io_addr, uint32 value); 109 110 long (*get_nth_pci_info) ( 111 long index, /* index into pci device table */ 112 pci_info *info /* caller-supplied buffer for info */ 113 ); 114 uint32 (*read_pci_config) ( 115 uchar bus, /* bus number */ 116 uchar device, /* device # on bus */ 117 uchar function, /* function # in device */ 118 uchar offset, /* offset in configuration space */ 119 uchar size /* # bytes to read (1, 2 or 4) */ 120 ); 121 void (*write_pci_config) ( 122 uchar bus, /* bus number */ 123 uchar device, /* device # on bus */ 124 uchar function, /* function # in device */ 125 uchar offset, /* offset in configuration space */ 126 uchar size, /* # bytes to write (1, 2 or 4) */ 127 uint32 value /* value to write */ 128 ); 129 130 void * (*ram_address) (const void *physical_address_in_system_memory); 131 }; 132 133 #define B_PCI_MODULE_NAME "bus_managers/pci/v1" 134 135 /* --- 136 offsets in PCI configuration space to the elements of the predefined 137 header common to all header types 138 --- */ 139 140 #define PCI_vendor_id 0x00 /* (2 byte) vendor id */ 141 #define PCI_device_id 0x02 /* (2 byte) device id */ 142 #define PCI_command 0x04 /* (2 byte) command */ 143 #define PCI_status 0x06 /* (2 byte) status */ 144 #define PCI_revision 0x08 /* (1 byte) revision id */ 145 #define PCI_class_api 0x09 /* (1 byte) specific register interface type */ 146 #define PCI_class_sub 0x0a /* (1 byte) specific device function */ 147 #define PCI_class_base 0x0b /* (1 byte) device type (display vs network, etc) */ 148 #define PCI_line_size 0x0c /* (1 byte) cache line size in 32 bit words */ 149 #define PCI_latency 0x0d /* (1 byte) latency timer */ 150 #define PCI_header_type 0x0e /* (1 byte) header type */ 151 #define PCI_bist 0x0f /* (1 byte) built-in self-test */ 152 153 154 155 /* --- 156 offsets in PCI configuration space to the elements of the predefined 157 header common to header types 0x00 and 0x01 158 --- */ 159 #define PCI_base_registers 0x10 /* base registers (size varies) */ 160 #define PCI_interrupt_line 0x3c /* (1 byte) interrupt line */ 161 #define PCI_interrupt_pin 0x3d /* (1 byte) interrupt pin */ 162 163 164 165 /* --- 166 offsets in PCI configuration space to the elements of header type 0x00 167 --- */ 168 169 #define PCI_cardbus_cis 0x28 /* (4 bytes) CardBus CIS (Card Information Structure) pointer (see PCMCIA v2.10 Spec) */ 170 #define PCI_subsystem_vendor_id 0x2c /* (2 bytes) subsystem (add-in card) vendor id */ 171 #define PCI_subsystem_id 0x2e /* (2 bytes) subsystem (add-in card) id */ 172 #define PCI_rom_base 0x30 /* (4 bytes) expansion rom base address */ 173 #define PCI_capabilities_ptr 0x34 /* (1 byte) pointer to the start of the capabilities list */ 174 #define PCI_min_grant 0x3e /* (1 byte) burst period @ 33 Mhz */ 175 #define PCI_max_latency 0x3f /* (1 byte) how often PCI access needed */ 176 177 178 /* --- 179 offsets in PCI configuration space to the elements of header type 0x01 (PCI-to-PCI bridge) 180 --- */ 181 182 #define PCI_primary_bus 0x18 /* (1 byte) */ 183 #define PCI_secondary_bus 0x19 /* (1 byte) */ 184 #define PCI_subordinate_bus 0x1A /* (1 byte) */ 185 #define PCI_secondary_latency 0x1B /* (1 byte) latency of secondary bus */ 186 #define PCI_io_base 0x1C /* (1 byte) io base address register for 2ndry bus*/ 187 #define PCI_io_limit 0x1D /* (1 byte) */ 188 #define PCI_secondary_status 0x1E /* (2 bytes) */ 189 #define PCI_memory_base 0x20 /* (2 bytes) */ 190 #define PCI_memory_limit 0x22 /* (2 bytes) */ 191 #define PCI_prefetchable_memory_base 0x24 /* (2 bytes) */ 192 #define PCI_prefetchable_memory_limit 0x26 /* (2 bytes) */ 193 #define PCI_prefetchable_memory_base_upper32 0x28 194 #define PCI_prefetchable_memory_limit_upper32 0x2C 195 #define PCI_io_base_upper16 0x30 /* (2 bytes) */ 196 #define PCI_io_limit_upper16 0x32 /* (2 bytes) */ 197 #define PCI_sub_vendor_id_1 0x34 /* (2 bytes) */ 198 #define PCI_sub_device_id_1 0x36 /* (2 bytes) */ 199 #define PCI_bridge_rom_base 0x38 200 #define PCI_bridge_control 0x3E /* (1 byte) */ 201 202 203 /* PCI type 2 header offsets */ 204 #define PCI_capabilities_ptr_2 0x14 /* (1 byte) */ 205 #define PCI_secondary_status_2 0x16 /* (2 bytes) */ 206 #define PCI_primary_bus_2 0x18 /* (1 byte) */ 207 #define PCI_secondary_bus_2 0x19 /* (1 byte) */ 208 #define PCI_subordinate_bus_2 0x1A /* (1 byte) */ 209 #define PCI_secondary_latency_2 0x1B /* (1 byte) latency of secondary bus */ 210 #define PCI_memory_base0_2 0x1C /* (4 bytes) */ 211 #define PCI_memory_limit0_2 0x20 /* (4 bytes) */ 212 #define PCI_memory_base1_2 0x24 /* (4 bytes) */ 213 #define PCI_memory_limit1_2 0x28 /* (4 bytes) */ 214 #define PCI_io_base0_2 0x2c /* (4 bytes) */ 215 #define PCI_io_limit0_2 0x30 /* (4 bytes) */ 216 #define PCI_io_base1_2 0x34 /* (4 bytes) */ 217 #define PCI_io_limit1_2 0x38 /* (4 bytes) */ 218 #define PCI_bridge_control_2 0x3E /* (1 byte) */ 219 220 #define PCI_sub_vendor_id_2 0x40 /* (2 bytes) */ 221 #define PCI_sub_device_id_2 0x42 /* (2 bytes) */ 222 223 #define PCI_card_interface_2 0x44 /* ?? */ 224 225 /* --- 226 values for the class_base field in the common header 227 --- */ 228 229 #define PCI_early 0x00 /* built before class codes defined */ 230 #define PCI_mass_storage 0x01 /* mass storage_controller */ 231 #define PCI_network 0x02 /* network controller */ 232 #define PCI_display 0x03 /* display controller */ 233 #define PCI_multimedia 0x04 /* multimedia device */ 234 #define PCI_memory 0x05 /* memory controller */ 235 #define PCI_bridge 0x06 /* bridge controller */ 236 #define PCI_simple_communications 0x07 /* simple communications controller */ 237 #define PCI_base_peripheral 0x08 /* base system peripherals */ 238 #define PCI_input 0x09 /* input devices */ 239 #define PCI_docking_station 0x0a /* docking stations */ 240 #define PCI_processor 0x0b /* processors */ 241 #define PCI_serial_bus 0x0c /* serial_bus_controller */ 242 #define PCI_wireless 0x0d 243 #define PCI_intelligent_io 0x0e 244 #define PCI_satellite_communications 0x0f 245 #define PCI_encryption_decryption 0x10 246 #define PCI_data_acquisition 0x11 247 248 #define PCI_undefined 0xFF /* not in any defined class */ 249 250 251 /* --- 252 values for the class_sub field for class_base = 0x00 (built before 253 class codes were defined) 254 --- */ 255 256 #define PCI_early_not_vga 0x00 /* all except vga */ 257 #define PCI_early_vga 0x01 /* vga devices */ 258 259 260 /* --- 261 values for the class_sub field for class_base = 0x01 (mass storage) 262 --- */ 263 264 #define PCI_scsi 0x00 /* SCSI controller */ 265 #define PCI_ide 0x01 /* IDE controller */ 266 #define PCI_floppy 0x02 /* floppy disk controller */ 267 #define PCI_ipi 0x03 /* IPI bus controller */ 268 #define PCI_raid 0x04 /* RAID controller */ 269 #define PCI_mass_storage_other 0x80 /* other mass storage controller */ 270 271 272 /* --- 273 values for the class_sub field for class_base = 0x02 (network) 274 --- */ 275 276 #define PCI_ethernet 0x00 /* Ethernet controller */ 277 #define PCI_token_ring 0x01 /* Token Ring controller */ 278 #define PCI_fddi 0x02 /* FDDI controller */ 279 #define PCI_atm 0x03 /* ATM controller */ 280 #define PCI_isdn 0x04 /* ISDN controller */ 281 #define PCI_network_other 0x80 /* other network controller */ 282 283 284 /* --- 285 values for the class_sub field for class_base = 0x03 (display) 286 --- */ 287 288 #define PCI_vga 0x00 /* VGA controller */ 289 #define PCI_xga 0x01 /* XGA controller */ 290 #define PCI_3d 0x02 /* £d controller */ 291 #define PCI_display_other 0x80 /* other display controller */ 292 293 294 /* --- 295 values for the class_sub field for class_base = 0x04 (multimedia device) 296 --- */ 297 298 #define PCI_video 0x00 /* video */ 299 #define PCI_audio 0x01 /* audio */ 300 #define PCI_telephony 0x02 /* computer telephony device */ 301 #define PCI_multimedia_other 0x80 /* other multimedia device */ 302 303 304 /* --- 305 values for the class_sub field for class_base = 0x05 (memory) 306 --- */ 307 308 #define PCI_ram 0x00 /* RAM */ 309 #define PCI_flash 0x01 /* flash */ 310 #define PCI_memory_other 0x80 /* other memory controller */ 311 312 313 /* --- 314 values for the class_sub field for class_base = 0x06 (bridge) 315 --- */ 316 317 #define PCI_host 0x00 /* host bridge */ 318 #define PCI_isa 0x01 /* ISA bridge */ 319 #define PCI_eisa 0x02 /* EISA bridge */ 320 #define PCI_microchannel 0x03 /* MicroChannel bridge */ 321 #define PCI_pci 0x04 /* PCI-to-PCI bridge */ 322 #define PCI_pcmcia 0x05 /* PCMCIA bridge */ 323 #define PCI_nubus 0x06 /* NuBus bridge */ 324 #define PCI_cardbus 0x07 /* CardBus bridge */ 325 #define PCI_raceway 0x08 /* RACEway bridge */ 326 #define PCI_bridge_other 0x80 /* other bridge device */ 327 328 329 /* --- 330 values for the class_sub field for class_base = 0x07 (simple 331 communications controllers) 332 --- */ 333 334 #define PCI_serial 0x00 /* serial port controller */ 335 #define PCI_parallel 0x01 /* parallel port */ 336 #define PCI_multiport_serial 0x02 /* multiport serial controller */ 337 #define PCI_modem 0x03 /* modem */ 338 #define PCI_simple_communications_other 0x80 /* other communications device */ 339 340 /* --- 341 values of the class_api field for 342 class_base = 0x07 (simple communications), and 343 class_sub = 0x00 (serial port controller) 344 --- */ 345 346 #define PCI_serial_xt 0x00 /* XT-compatible serial controller */ 347 #define PCI_serial_16450 0x01 /* 16450-compatible serial controller */ 348 #define PCI_serial_16550 0x02 /* 16550-compatible serial controller */ 349 350 351 /* --- 352 values of the class_api field for 353 class_base = 0x07 (simple communications), and 354 class_sub = 0x01 (parallel port) 355 --- */ 356 357 #define PCI_parallel_simple 0x00 /* simple (output-only) parallel port */ 358 #define PCI_parallel_bidirectional 0x01 /* bidirectional parallel port */ 359 #define PCI_parallel_ecp 0x02 /* ECP 1.x compliant parallel port */ 360 361 362 /* --- 363 values for the class_sub field for class_base = 0x08 (generic 364 system peripherals) 365 --- */ 366 367 #define PCI_pic 0x00 /* periperal interrupt controller */ 368 #define PCI_dma 0x01 /* dma controller */ 369 #define PCI_timer 0x02 /* timers */ 370 #define PCI_rtc 0x03 /* real time clock */ 371 #define PCI_generic_hot_plug 0x04 /* generic PCI hot-plug controller */ 372 #define PCI_system_peripheral_other 0x80 /* other generic system peripheral */ 373 374 /* --- 375 values of the class_api field for 376 class_base = 0x08 (generic system peripherals) 377 class_sub = 0x00 (peripheral interrupt controller) 378 --- */ 379 380 #define PCI_pic_8259 0x00 /* generic 8259 */ 381 #define PCI_pic_isa 0x01 /* ISA pic */ 382 #define PCI_pic_eisa 0x02 /* EISA pic */ 383 384 /* --- 385 values of the class_api field for 386 class_base = 0x08 (generic system peripherals) 387 class_sub = 0x01 (dma controller) 388 --- */ 389 390 #define PCI_dma_8237 0x00 /* generic 8237 */ 391 #define PCI_dma_isa 0x01 /* ISA dma */ 392 #define PCI_dma_eisa 0x02 /* EISA dma */ 393 394 /* --- 395 values of the class_api field for 396 class_base = 0x08 (generic system peripherals) 397 class_sub = 0x02 (timer) 398 --- */ 399 400 #define PCI_timer_8254 0x00 /* generic 8254 */ 401 #define PCI_timer_isa 0x01 /* ISA timer */ 402 #define PCI_timer_eisa 0x02 /* EISA timers (2 timers) */ 403 404 405 /* --- 406 values of the class_api field for 407 class_base = 0x08 (generic system peripherals) 408 class_sub = 0x03 (real time clock 409 --- */ 410 411 #define PCI_rtc_generic 0x00 /* generic real time clock */ 412 #define PCI_rtc_isa 0x01 /* ISA real time clock */ 413 414 415 /* --- 416 values for the class_sub field for class_base = 0x09 (input devices) 417 --- */ 418 419 #define PCI_keyboard 0x00 /* keyboard controller */ 420 #define PCI_pen 0x01 /* pen */ 421 #define PCI_mouse 0x02 /* mouse controller */ 422 #define PCI_scanner 0x03 /* scanner controller */ 423 #define PCI_gameport 0x04 /* gameport controller */ 424 #define PCI_input_other 0x80 /* other input controller */ 425 426 427 /* --- 428 values for the class_sub field for class_base = 0x0a (docking stations) 429 --- */ 430 431 #define PCI_docking_generic 0x00 /* generic docking station */ 432 433 /* --- 434 values for the class_sub field for class_base = 0x0b (processor) 435 --- */ 436 437 #define PCI_386 0x00 /* 386 */ 438 #define PCI_486 0x01 /* 486 */ 439 #define PCI_pentium 0x02 /* Pentium */ 440 #define PCI_alpha 0x10 /* Alpha */ 441 #define PCI_PowerPC 0x20 /* PowerPC */ 442 #define PCI_mips 0x30 /* MIPS */ 443 #define PCI_coprocessor 0x40 /* co-processor */ 444 445 /* --- 446 values for the class_sub field for class_base = 0x0c (serial bus 447 controller) 448 --- */ 449 450 #define PCI_firewire 0x00 /* FireWire (IEEE 1394) */ 451 #define PCI_access 0x01 /* ACCESS bus */ 452 #define PCI_ssa 0x02 /* SSA */ 453 #define PCI_usb 0x03 /* Universal Serial Bus */ 454 #define PCI_fibre_channel 0x04 /* Fibre channel */ 455 456 /* --- 457 values of the class_api field for 458 class_base = 0x0c ( serial bus controller ) 459 class_sub = 0x03 ( Universal Serial Bus ) 460 --- */ 461 462 #define PCI_usb_uhci 0x00 /* Universal Host Controller Interface */ 463 #define PCI_usb_ohci 0x10 /* Open Host Controller Interface */ 464 465 466 /* --- 467 masks for command register bits 468 --- */ 469 470 #define PCI_command_io 0x001 /* 1/0 i/o space en/disabled */ 471 #define PCI_command_memory 0x002 /* 1/0 memory space en/disabled */ 472 #define PCI_command_master 0x004 /* 1/0 pci master en/disabled */ 473 #define PCI_command_special 0x008 /* 1/0 pci special cycles en/disabled */ 474 #define PCI_command_mwi 0x010 /* 1/0 memory write & invalidate en/disabled */ 475 #define PCI_command_vga_snoop 0x020 /* 1/0 vga pallette snoop en/disabled */ 476 #define PCI_command_parity 0x040 /* 1/0 parity check en/disabled */ 477 #define PCI_command_address_step 0x080 /* 1/0 address stepping en/disabled */ 478 #define PCI_command_serr 0x100 /* 1/0 SERR# en/disabled */ 479 #define PCI_command_fastback 0x200 /* 1/0 fast back-to-back en/disabled */ 480 481 482 /* --- 483 masks for status register bits 484 --- */ 485 486 #define PCI_status_capabilities 0x0010 /* capabilities list */ 487 #define PCI_status_66_MHz_capable 0x0020 /* 66 Mhz capable */ 488 #define PCI_status_udf_supported 0x0040 /* user-definable-features (udf) supported */ 489 #define PCI_status_fastback 0x0080 /* fast back-to-back capable */ 490 #define PCI_status_parity_signalled 0x0100 /* parity error signalled */ 491 #define PCI_status_devsel 0x0600 /* devsel timing (see below) */ 492 #define PCI_status_target_abort_signalled 0x0800 /* signaled a target abort */ 493 #define PCI_status_target_abort_received 0x1000 /* received a target abort */ 494 #define PCI_status_master_abort_received 0x2000 /* received a master abort */ 495 #define PCI_status_serr_signalled 0x4000 /* signalled SERR# */ 496 #define PCI_status_parity_error_detected 0x8000 /* parity error detected */ 497 498 499 /* --- 500 masks for devsel field in status register 501 --- */ 502 503 #define PCI_status_devsel_fast 0x0000 /* fast */ 504 #define PCI_status_devsel_medium 0x0200 /* medium */ 505 #define PCI_status_devsel_slow 0x0400 /* slow */ 506 507 508 /* --- 509 masks for header type register 510 --- */ 511 512 #define PCI_header_type_mask 0x7F /* header type field */ 513 #define PCI_multifunction 0x80 /* multifunction device flag */ 514 515 516 /** types of PCI header */ 517 518 #define PCI_header_type_generic 0x00 519 #define PCI_header_type_PCI_to_PCI_bridge 0x01 520 #define PCI_header_type_cardbus 0x02 521 522 523 /* --- 524 masks for built in self test (bist) register bits 525 --- */ 526 527 #define PCI_bist_code 0x0F /* self-test completion code, 0 = success */ 528 #define PCI_bist_start 0x40 /* 1 = start self-test */ 529 #define PCI_bist_capable 0x80 /* 1 = self-test capable */ 530 531 532 /** masks for flags in the various base address registers */ 533 534 #define PCI_address_space 0x01 /* 0 = memory space, 1 = i/o space */ 535 #define PCI_register_start 0x10 536 #define PCI_register_end 0x24 537 #define PCI_register_ppb_end 0x18 538 #define PCI_register_pcb_end 0x14 539 540 /** masks for flags in memory space base address registers */ 541 542 #define PCI_address_type_32 0x00 /* locate anywhere in 32 bit space */ 543 #define PCI_address_type_32_low 0x02 /* locate below 1 Meg */ 544 #define PCI_address_type_64 0x04 /* locate anywhere in 64 bit space */ 545 #define PCI_address_type 0x06 /* type (see below) */ 546 #define PCI_address_prefetchable 0x08 /* 1 if prefetchable (see PCI spec) */ 547 548 #define PCI_address_memory_32_mask 0xFFFFFFF0 /* mask to get 32bit memory space base address */ 549 550 551 /* --- 552 masks for flags in i/o space base address registers 553 --- */ 554 555 #define PCI_address_io_mask 0xFFFFFFFC /* mask to get i/o space base address */ 556 557 558 /* --- 559 masks for flags in expansion rom base address registers 560 --- */ 561 562 #define PCI_rom_enable 0x00000001 /* 1 = expansion rom decode enabled */ 563 #define PCI_rom_address_mask 0xFFFFF800 /* mask to get expansion rom addr */ 564 565 /** PCI interrupt pin values */ 566 #define PCI_pin_mask 0x07 567 #define PCI_pin_none 0x00 568 #define PCI_pin_a 0x01 569 #define PCI_pin_b 0x02 570 #define PCI_pin_c 0x03 571 #define PCI_pin_d 0x04 572 #define PCI_pin_max 0x04 573 574 /** PCI Capability Codes */ 575 #define PCI_cap_id_reserved 0x00 576 #define PCI_cap_id_pm 0x01 /* Power management */ 577 #define PCI_cap_id_agp 0x02 /* AGP */ 578 #define PCI_cap_id_vpd 0x03 /* Vital product data */ 579 #define PCI_cap_id_slotid 0x04 /* Slot ID */ 580 #define PCI_cap_id_msi 0x05 /* Message signalled interrupt ??? */ 581 #define PCI_cap_id_chswp 0x06 /* Compact PCI HotSwap */ 582 #define PCI_cap_id_pcix 0x07 583 #define PCI_cap_id_ldt 0x08 584 #define PCI_cap_id_vendspec 0x09 585 #define PCI_cap_id_debugport 0x0a 586 #define PCI_cap_id_cpci_rsrcctl 0x0b 587 #define PCI_cap_id_hotplug 0x0c 588 589 /** Power Management Control Status Register settings */ 590 #define PCI_pm_mask 0x03 591 #define PCI_pm_ctrl 0x02 592 #define PCI_pm_d1supp 0x0200 593 #define PCI_pm_d2supp 0x0400 594 #define PCI_pm_status 0x04 595 #define PCI_pm_state_d0 0x00 596 #define PCI_pm_state_d1 0x01 597 #define PCI_pm_state_d2 0x02 598 #define PCI_pm_state_d3 0x03 599 600 #ifdef __cplusplus 601 } 602 #endif 603 604 #endif /* _PCI_H */ 605