1 /******************************************************************************* 2 / 3 / File: PCI.h 4 / 5 / Description: Interface to the PCI bus. 6 / For more information, see "PCI Local Bus Specification, Revision 2.1", 7 / PCI Special Interest Group, 1995. 8 / 9 / Copyright 1993-98, Be Incorporated, All Rights Reserved. 10 / 11 *******************************************************************************/ 12 13 14 #ifndef _PCI_H 15 #define _PCI_H 16 17 //#include <BeBuild.h> 18 //#include <SupportDefs.h> 19 #include <bus_manager.h> 20 21 #ifdef __cplusplus 22 extern "C" { 23 #endif 24 25 26 /* ----- 27 pci device info 28 ----- */ 29 30 typedef struct pci_info { 31 ushort vendor_id; /* vendor id */ 32 ushort device_id; /* device id */ 33 uchar bus; /* bus number */ 34 uchar device; /* device number on bus */ 35 uchar function; /* function number in device */ 36 uchar revision; /* revision id */ 37 uchar class_api; /* specific register interface type */ 38 uchar class_sub; /* specific device function */ 39 uchar class_base; /* device type (display vs network, etc) */ 40 uchar line_size; /* cache line size in 32 bit words */ 41 uchar latency; /* latency timer */ 42 uchar header_type; /* header type */ 43 uchar bist; /* built-in self-test */ 44 uchar reserved; /* filler, for alignment */ 45 union { 46 struct { 47 ulong cardbus_cis; /* CardBus CIS pointer */ 48 ushort subsystem_id; /* subsystem (add-in card) id */ 49 ushort subsystem_vendor_id; /* subsystem (add-in card) vendor id */ 50 ulong rom_base; /* rom base address, viewed from host */ 51 ulong rom_base_pci; /* rom base addr, viewed from pci */ 52 ulong rom_size; /* rom size */ 53 ulong base_registers[6]; /* base registers, viewed from host */ 54 ulong base_registers_pci[6]; /* base registers, viewed from pci */ 55 ulong base_register_sizes[6]; /* size of what base regs point to */ 56 uchar base_register_flags[6]; /* flags from base address fields */ 57 uchar interrupt_line; /* interrupt line */ 58 uchar interrupt_pin; /* interrupt pin */ 59 uchar min_grant; /* burst period @ 33 Mhz */ 60 uchar max_latency; /* how often PCI access needed */ 61 } h0; 62 struct { 63 ulong base_registers[2]; /* base registers, viewed from host */ 64 ulong base_registers_pci[2]; /* base registers, viewed from pci */ 65 ulong base_register_sizes[2]; /* size of what base regs point to */ 66 uchar base_register_flags[2]; /* flags from base address fields */ 67 uchar primary_bus; 68 uchar secondary_bus; 69 uchar subordinate_bus; 70 uchar secondary_latency; 71 uchar io_base; 72 uchar io_limit; 73 ushort secondary_status; 74 ushort memory_base; 75 ushort memory_limit; 76 ushort prefetchable_memory_base; 77 ushort prefetchable_memory_limit; 78 ulong prefetchable_memory_base_upper32; 79 ulong prefetchable_memory_limit_upper32; 80 ushort io_base_upper16; 81 ushort io_limit_upper16; 82 ulong rom_base; /* rom base address, viewed from host */ 83 ulong rom_base_pci; /* rom base addr, viewed from pci */ 84 uchar interrupt_line; /* interrupt line */ 85 uchar interrupt_pin; /* interrupt pin */ 86 ushort bridge_control; 87 ushort subsystem_id; /* subsystem (add-in card) id */ 88 ushort subsystem_vendor_id; /* subsystem (add-in card) vendor id */ 89 } h1; 90 struct { 91 ushort subsystem_id; /* subsystem (add-in card) id */ 92 ushort subsystem_vendor_id; /* subsystem (add-in card) vendor id */ 93 94 #ifdef __HAIKU_PCI_BUS_MANAGER_TESTING 95 // for testing only, not final (do not use!): 96 uchar primary_bus; 97 uchar secondary_bus; 98 uchar subordinate_bus; 99 uchar secondary_latency; 100 ushort reserved; 101 ulong memory_base; 102 ulong memory_limit; 103 ulong memory_base_upper32; 104 ulong memory_limit_upper32; 105 ulong io_base; 106 ulong io_limit; 107 ulong io_base_upper32; 108 ulong io_limit_upper32; 109 ushort secondary_status; 110 uchar bridge_control; 111 #endif /* __HAIKU_PCI_BUS_MANAGER_TESTING */ 112 } h2; 113 } u; 114 } pci_info; 115 116 117 typedef struct pci_module_info pci_module_info; 118 119 struct pci_module_info { 120 bus_manager_info binfo; 121 122 uint8 (*read_io_8) (int mapped_io_addr); 123 void (*write_io_8) (int mapped_io_addr, uint8 value); 124 uint16 (*read_io_16) (int mapped_io_addr); 125 void (*write_io_16) (int mapped_io_addr, uint16 value); 126 uint32 (*read_io_32) (int mapped_io_addr); 127 void (*write_io_32) (int mapped_io_addr, uint32 value); 128 129 long (*get_nth_pci_info) ( 130 long index, /* index into pci device table */ 131 pci_info *info /* caller-supplied buffer for info */ 132 ); 133 uint32 (*read_pci_config) ( 134 uchar bus, /* bus number */ 135 uchar device, /* device # on bus */ 136 uchar function, /* function # in device */ 137 uchar offset, /* offset in configuration space */ 138 uchar size /* # bytes to read (1, 2 or 4) */ 139 ); 140 void (*write_pci_config) ( 141 uchar bus, /* bus number */ 142 uchar device, /* device # on bus */ 143 uchar function, /* function # in device */ 144 uchar offset, /* offset in configuration space */ 145 uchar size, /* # bytes to write (1, 2 or 4) */ 146 uint32 value /* value to write */ 147 ); 148 149 void * (*ram_address) (const void *physical_address_in_system_memory); 150 151 status_t (*find_pci_capability) ( 152 uchar bus, 153 uchar device, 154 uchar function, 155 uchar cap_id, 156 uchar *offset 157 ); 158 }; 159 160 #define B_PCI_MODULE_NAME "bus_managers/pci/v1" 161 162 /* --- 163 offsets in PCI configuration space to the elements of the predefined 164 header common to all header types 165 --- */ 166 167 #define PCI_vendor_id 0x00 /* (2 byte) vendor id */ 168 #define PCI_device_id 0x02 /* (2 byte) device id */ 169 #define PCI_command 0x04 /* (2 byte) command */ 170 #define PCI_status 0x06 /* (2 byte) status */ 171 #define PCI_revision 0x08 /* (1 byte) revision id */ 172 #define PCI_class_api 0x09 /* (1 byte) specific register interface type */ 173 #define PCI_class_sub 0x0a /* (1 byte) specific device function */ 174 #define PCI_class_base 0x0b /* (1 byte) device type (display vs network, etc) */ 175 #define PCI_line_size 0x0c /* (1 byte) cache line size in 32 bit words */ 176 #define PCI_latency 0x0d /* (1 byte) latency timer */ 177 #define PCI_header_type 0x0e /* (1 byte) header type */ 178 #define PCI_bist 0x0f /* (1 byte) built-in self-test */ 179 180 181 182 /* --- 183 offsets in PCI configuration space to the elements of the predefined 184 header common to header types 0x00 and 0x01 185 --- */ 186 #define PCI_base_registers 0x10 /* base registers (size varies) */ 187 #define PCI_interrupt_line 0x3c /* (1 byte) interrupt line */ 188 #define PCI_interrupt_pin 0x3d /* (1 byte) interrupt pin */ 189 190 191 192 /* --- 193 offsets in PCI configuration space to the elements of header type 0x00 194 --- */ 195 196 #define PCI_cardbus_cis 0x28 /* (4 bytes) CardBus CIS (Card Information Structure) pointer (see PCMCIA v2.10 Spec) */ 197 #define PCI_subsystem_vendor_id 0x2c /* (2 bytes) subsystem (add-in card) vendor id */ 198 #define PCI_subsystem_id 0x2e /* (2 bytes) subsystem (add-in card) id */ 199 #define PCI_rom_base 0x30 /* (4 bytes) expansion rom base address */ 200 #define PCI_capabilities_ptr 0x34 /* (1 byte) pointer to the start of the capabilities list */ 201 #define PCI_min_grant 0x3e /* (1 byte) burst period @ 33 Mhz */ 202 #define PCI_max_latency 0x3f /* (1 byte) how often PCI access needed */ 203 204 205 /* --- 206 offsets in PCI configuration space to the elements of header type 0x01 (PCI-to-PCI bridge) 207 --- */ 208 209 #define PCI_primary_bus 0x18 /* (1 byte) */ 210 #define PCI_secondary_bus 0x19 /* (1 byte) */ 211 #define PCI_subordinate_bus 0x1A /* (1 byte) */ 212 #define PCI_secondary_latency 0x1B /* (1 byte) latency of secondary bus */ 213 #define PCI_io_base 0x1C /* (1 byte) io base address register for 2ndry bus*/ 214 #define PCI_io_limit 0x1D /* (1 byte) */ 215 #define PCI_secondary_status 0x1E /* (2 bytes) */ 216 #define PCI_memory_base 0x20 /* (2 bytes) */ 217 #define PCI_memory_limit 0x22 /* (2 bytes) */ 218 #define PCI_prefetchable_memory_base 0x24 /* (2 bytes) */ 219 #define PCI_prefetchable_memory_limit 0x26 /* (2 bytes) */ 220 #define PCI_prefetchable_memory_base_upper32 0x28 221 #define PCI_prefetchable_memory_limit_upper32 0x2C 222 #define PCI_io_base_upper16 0x30 /* (2 bytes) */ 223 #define PCI_io_limit_upper16 0x32 /* (2 bytes) */ 224 #define PCI_sub_vendor_id_1 0x34 /* (2 bytes) */ 225 #define PCI_sub_device_id_1 0x36 /* (2 bytes) */ 226 #define PCI_bridge_rom_base 0x38 227 #define PCI_bridge_control 0x3E /* (1 byte) */ 228 229 230 /* PCI type 2 header offsets */ 231 #define PCI_capabilities_ptr_2 0x14 /* (1 byte) */ 232 #define PCI_secondary_status_2 0x16 /* (2 bytes) */ 233 #define PCI_primary_bus_2 0x18 /* (1 byte) */ 234 #define PCI_secondary_bus_2 0x19 /* (1 byte) */ 235 #define PCI_subordinate_bus_2 0x1A /* (1 byte) */ 236 #define PCI_secondary_latency_2 0x1B /* (1 byte) latency of secondary bus */ 237 #define PCI_memory_base0_2 0x1C /* (4 bytes) */ 238 #define PCI_memory_limit0_2 0x20 /* (4 bytes) */ 239 #define PCI_memory_base1_2 0x24 /* (4 bytes) */ 240 #define PCI_memory_limit1_2 0x28 /* (4 bytes) */ 241 #define PCI_io_base0_2 0x2c /* (4 bytes) */ 242 #define PCI_io_limit0_2 0x30 /* (4 bytes) */ 243 #define PCI_io_base1_2 0x34 /* (4 bytes) */ 244 #define PCI_io_limit1_2 0x38 /* (4 bytes) */ 245 #define PCI_bridge_control_2 0x3E /* (1 byte) */ 246 247 #define PCI_sub_vendor_id_2 0x40 /* (2 bytes) */ 248 #define PCI_sub_device_id_2 0x42 /* (2 bytes) */ 249 250 #define PCI_card_interface_2 0x44 /* ?? */ 251 252 /* --- 253 values for the class_base field in the common header 254 --- */ 255 256 #define PCI_early 0x00 /* built before class codes defined */ 257 #define PCI_mass_storage 0x01 /* mass storage_controller */ 258 #define PCI_network 0x02 /* network controller */ 259 #define PCI_display 0x03 /* display controller */ 260 #define PCI_multimedia 0x04 /* multimedia device */ 261 #define PCI_memory 0x05 /* memory controller */ 262 #define PCI_bridge 0x06 /* bridge controller */ 263 #define PCI_simple_communications 0x07 /* simple communications controller */ 264 #define PCI_base_peripheral 0x08 /* base system peripherals */ 265 #define PCI_input 0x09 /* input devices */ 266 #define PCI_docking_station 0x0a /* docking stations */ 267 #define PCI_processor 0x0b /* processors */ 268 #define PCI_serial_bus 0x0c /* serial_bus_controller */ 269 #define PCI_wireless 0x0d 270 #define PCI_intelligent_io 0x0e 271 #define PCI_satellite_communications 0x0f 272 #define PCI_encryption_decryption 0x10 273 #define PCI_data_acquisition 0x11 274 275 #define PCI_undefined 0xFF /* not in any defined class */ 276 277 278 /* --- 279 values for the class_sub field for class_base = 0x00 (built before 280 class codes were defined) 281 --- */ 282 283 #define PCI_early_not_vga 0x00 /* all except vga */ 284 #define PCI_early_vga 0x01 /* vga devices */ 285 286 287 /* --- 288 values for the class_sub field for class_base = 0x01 (mass storage) 289 --- */ 290 291 #define PCI_scsi 0x00 /* SCSI controller */ 292 #define PCI_ide 0x01 /* IDE controller */ 293 #define PCI_floppy 0x02 /* floppy disk controller */ 294 #define PCI_ipi 0x03 /* IPI bus controller */ 295 #define PCI_raid 0x04 /* RAID controller */ 296 #define PCI_ata 0x05 /* ATA controller with ADMA interface */ 297 #define PCI_sata 0x06 /* Serial ATA controller */ 298 #define PCI_sas 0x07 /* Serial Attached SCSI controller */ 299 #define PCI_mass_storage_other 0x80 /* other mass storage controller */ 300 301 /* --- 302 values of the class_api field for 303 class_base = 0x01 (mass storage) 304 class_sub = 0x06 (Serial ATA controller) 305 --- */ 306 307 #define PCI_sata_other 0x00 /* vendor specific interface */ 308 #define PCI_sata_ahci 0x01 /* AHCI interface */ 309 310 311 /* --- 312 values for the class_sub field for class_base = 0x02 (network) 313 --- */ 314 315 #define PCI_ethernet 0x00 /* Ethernet controller */ 316 #define PCI_token_ring 0x01 /* Token Ring controller */ 317 #define PCI_fddi 0x02 /* FDDI controller */ 318 #define PCI_atm 0x03 /* ATM controller */ 319 #define PCI_isdn 0x04 /* ISDN controller */ 320 #define PCI_network_other 0x80 /* other network controller */ 321 322 323 /* --- 324 values for the class_sub field for class_base = 0x03 (display) 325 --- */ 326 327 #define PCI_vga 0x00 /* VGA controller */ 328 #define PCI_xga 0x01 /* XGA controller */ 329 #define PCI_3d 0x02 /* £d controller */ 330 #define PCI_display_other 0x80 /* other display controller */ 331 332 333 /* --- 334 values for the class_sub field for class_base = 0x04 (multimedia device) 335 --- */ 336 337 #define PCI_video 0x00 /* video */ 338 #define PCI_audio 0x01 /* audio */ 339 #define PCI_telephony 0x02 /* computer telephony device */ 340 #define PCI_multimedia_other 0x80 /* other multimedia device */ 341 342 343 /* --- 344 values for the class_sub field for class_base = 0x05 (memory) 345 --- */ 346 347 #define PCI_ram 0x00 /* RAM */ 348 #define PCI_flash 0x01 /* flash */ 349 #define PCI_memory_other 0x80 /* other memory controller */ 350 351 352 /* --- 353 values for the class_sub field for class_base = 0x06 (bridge) 354 --- */ 355 356 #define PCI_host 0x00 /* host bridge */ 357 #define PCI_isa 0x01 /* ISA bridge */ 358 #define PCI_eisa 0x02 /* EISA bridge */ 359 #define PCI_microchannel 0x03 /* MicroChannel bridge */ 360 #define PCI_pci 0x04 /* PCI-to-PCI bridge */ 361 #define PCI_pcmcia 0x05 /* PCMCIA bridge */ 362 #define PCI_nubus 0x06 /* NuBus bridge */ 363 #define PCI_cardbus 0x07 /* CardBus bridge */ 364 #define PCI_raceway 0x08 /* RACEway bridge */ 365 #define PCI_bridge_other 0x80 /* other bridge device */ 366 367 368 /* --- 369 values for the class_sub field for class_base = 0x07 (simple 370 communications controllers) 371 --- */ 372 373 #define PCI_serial 0x00 /* serial port controller */ 374 #define PCI_parallel 0x01 /* parallel port */ 375 #define PCI_multiport_serial 0x02 /* multiport serial controller */ 376 #define PCI_modem 0x03 /* modem */ 377 #define PCI_simple_communications_other 0x80 /* other communications device */ 378 379 /* --- 380 values of the class_api field for 381 class_base = 0x07 (simple communications), and 382 class_sub = 0x00 (serial port controller) 383 --- */ 384 385 #define PCI_serial_xt 0x00 /* XT-compatible serial controller */ 386 #define PCI_serial_16450 0x01 /* 16450-compatible serial controller */ 387 #define PCI_serial_16550 0x02 /* 16550-compatible serial controller */ 388 389 390 /* --- 391 values of the class_api field for 392 class_base = 0x07 (simple communications), and 393 class_sub = 0x01 (parallel port) 394 --- */ 395 396 #define PCI_parallel_simple 0x00 /* simple (output-only) parallel port */ 397 #define PCI_parallel_bidirectional 0x01 /* bidirectional parallel port */ 398 #define PCI_parallel_ecp 0x02 /* ECP 1.x compliant parallel port */ 399 400 401 /* --- 402 values for the class_sub field for class_base = 0x08 (generic 403 system peripherals) 404 --- */ 405 406 #define PCI_pic 0x00 /* periperal interrupt controller */ 407 #define PCI_dma 0x01 /* dma controller */ 408 #define PCI_timer 0x02 /* timers */ 409 #define PCI_rtc 0x03 /* real time clock */ 410 #define PCI_generic_hot_plug 0x04 /* generic PCI hot-plug controller */ 411 #define PCI_system_peripheral_other 0x80 /* other generic system peripheral */ 412 413 /* --- 414 values of the class_api field for 415 class_base = 0x08 (generic system peripherals) 416 class_sub = 0x00 (peripheral interrupt controller) 417 --- */ 418 419 #define PCI_pic_8259 0x00 /* generic 8259 */ 420 #define PCI_pic_isa 0x01 /* ISA pic */ 421 #define PCI_pic_eisa 0x02 /* EISA pic */ 422 423 /* --- 424 values of the class_api field for 425 class_base = 0x08 (generic system peripherals) 426 class_sub = 0x01 (dma controller) 427 --- */ 428 429 #define PCI_dma_8237 0x00 /* generic 8237 */ 430 #define PCI_dma_isa 0x01 /* ISA dma */ 431 #define PCI_dma_eisa 0x02 /* EISA dma */ 432 433 /* --- 434 values of the class_api field for 435 class_base = 0x08 (generic system peripherals) 436 class_sub = 0x02 (timer) 437 --- */ 438 439 #define PCI_timer_8254 0x00 /* generic 8254 */ 440 #define PCI_timer_isa 0x01 /* ISA timer */ 441 #define PCI_timer_eisa 0x02 /* EISA timers (2 timers) */ 442 443 444 /* --- 445 values of the class_api field for 446 class_base = 0x08 (generic system peripherals) 447 class_sub = 0x03 (real time clock 448 --- */ 449 450 #define PCI_rtc_generic 0x00 /* generic real time clock */ 451 #define PCI_rtc_isa 0x01 /* ISA real time clock */ 452 453 454 /* --- 455 values for the class_sub field for class_base = 0x09 (input devices) 456 --- */ 457 458 #define PCI_keyboard 0x00 /* keyboard controller */ 459 #define PCI_pen 0x01 /* pen */ 460 #define PCI_mouse 0x02 /* mouse controller */ 461 #define PCI_scanner 0x03 /* scanner controller */ 462 #define PCI_gameport 0x04 /* gameport controller */ 463 #define PCI_input_other 0x80 /* other input controller */ 464 465 466 /* --- 467 values for the class_sub field for class_base = 0x0a (docking stations) 468 --- */ 469 470 #define PCI_docking_generic 0x00 /* generic docking station */ 471 472 /* --- 473 values for the class_sub field for class_base = 0x0b (processor) 474 --- */ 475 476 #define PCI_386 0x00 /* 386 */ 477 #define PCI_486 0x01 /* 486 */ 478 #define PCI_pentium 0x02 /* Pentium */ 479 #define PCI_alpha 0x10 /* Alpha */ 480 #define PCI_PowerPC 0x20 /* PowerPC */ 481 #define PCI_mips 0x30 /* MIPS */ 482 #define PCI_coprocessor 0x40 /* co-processor */ 483 484 /* --- 485 values for the class_sub field for class_base = 0x0c (serial bus 486 controller) 487 --- */ 488 489 #define PCI_firewire 0x00 /* FireWire (IEEE 1394) */ 490 #define PCI_access 0x01 /* ACCESS bus */ 491 #define PCI_ssa 0x02 /* SSA */ 492 #define PCI_usb 0x03 /* Universal Serial Bus */ 493 #define PCI_fibre_channel 0x04 /* Fibre channel */ 494 495 /* --- 496 values of the class_api field for 497 class_base = 0x0c ( serial bus controller ) 498 class_sub = 0x03 ( Universal Serial Bus ) 499 --- */ 500 501 #define PCI_usb_uhci 0x00 /* Universal Host Controller Interface */ 502 #define PCI_usb_ohci 0x10 /* Open Host Controller Interface */ 503 #define PCI_usb_ehci 0x20 /* Enhanced Host Controller Interface */ 504 505 506 /* --- 507 masks for command register bits 508 --- */ 509 510 #define PCI_command_io 0x001 /* 1/0 i/o space en/disabled */ 511 #define PCI_command_memory 0x002 /* 1/0 memory space en/disabled */ 512 #define PCI_command_master 0x004 /* 1/0 pci master en/disabled */ 513 #define PCI_command_special 0x008 /* 1/0 pci special cycles en/disabled */ 514 #define PCI_command_mwi 0x010 /* 1/0 memory write & invalidate en/disabled */ 515 #define PCI_command_vga_snoop 0x020 /* 1/0 vga pallette snoop en/disabled */ 516 #define PCI_command_parity 0x040 /* 1/0 parity check en/disabled */ 517 #define PCI_command_address_step 0x080 /* 1/0 address stepping en/disabled */ 518 #define PCI_command_serr 0x100 /* 1/0 SERR# en/disabled */ 519 #define PCI_command_fastback 0x200 /* 1/0 fast back-to-back en/disabled */ 520 521 522 /* --- 523 masks for status register bits 524 --- */ 525 526 #define PCI_status_capabilities 0x0010 /* capabilities list */ 527 #define PCI_status_66_MHz_capable 0x0020 /* 66 Mhz capable */ 528 #define PCI_status_udf_supported 0x0040 /* user-definable-features (udf) supported */ 529 #define PCI_status_fastback 0x0080 /* fast back-to-back capable */ 530 #define PCI_status_parity_signalled 0x0100 /* parity error signalled */ 531 #define PCI_status_devsel 0x0600 /* devsel timing (see below) */ 532 #define PCI_status_target_abort_signalled 0x0800 /* signaled a target abort */ 533 #define PCI_status_target_abort_received 0x1000 /* received a target abort */ 534 #define PCI_status_master_abort_received 0x2000 /* received a master abort */ 535 #define PCI_status_serr_signalled 0x4000 /* signalled SERR# */ 536 #define PCI_status_parity_error_detected 0x8000 /* parity error detected */ 537 538 539 /* --- 540 masks for devsel field in status register 541 --- */ 542 543 #define PCI_status_devsel_fast 0x0000 /* fast */ 544 #define PCI_status_devsel_medium 0x0200 /* medium */ 545 #define PCI_status_devsel_slow 0x0400 /* slow */ 546 547 548 /* --- 549 masks for header type register 550 --- */ 551 552 #define PCI_header_type_mask 0x7F /* header type field */ 553 #define PCI_multifunction 0x80 /* multifunction device flag */ 554 555 556 /** types of PCI header */ 557 558 #define PCI_header_type_generic 0x00 559 #define PCI_header_type_PCI_to_PCI_bridge 0x01 560 #define PCI_header_type_cardbus 0x02 561 562 563 /* --- 564 masks for built in self test (bist) register bits 565 --- */ 566 567 #define PCI_bist_code 0x0F /* self-test completion code, 0 = success */ 568 #define PCI_bist_start 0x40 /* 1 = start self-test */ 569 #define PCI_bist_capable 0x80 /* 1 = self-test capable */ 570 571 572 /** masks for flags in the various base address registers */ 573 574 #define PCI_address_space 0x01 /* 0 = memory space, 1 = i/o space */ 575 #define PCI_register_start 0x10 576 #define PCI_register_end 0x24 577 #define PCI_register_ppb_end 0x18 578 #define PCI_register_pcb_end 0x14 579 580 /** masks for flags in memory space base address registers */ 581 582 #define PCI_address_type_32 0x00 /* locate anywhere in 32 bit space */ 583 #define PCI_address_type_32_low 0x02 /* locate below 1 Meg */ 584 #define PCI_address_type_64 0x04 /* locate anywhere in 64 bit space */ 585 #define PCI_address_type 0x06 /* type (see below) */ 586 #define PCI_address_prefetchable 0x08 /* 1 if prefetchable (see PCI spec) */ 587 588 #define PCI_address_memory_32_mask 0xFFFFFFF0 /* mask to get 32bit memory space base address */ 589 590 591 /* --- 592 masks for flags in i/o space base address registers 593 --- */ 594 595 #define PCI_address_io_mask 0xFFFFFFFC /* mask to get i/o space base address */ 596 597 598 /* --- 599 masks for flags in expansion rom base address registers 600 --- */ 601 602 #define PCI_rom_enable 0x00000001 /* 1 = expansion rom decode enabled */ 603 #define PCI_rom_address_mask 0xFFFFF800 /* mask to get expansion rom addr */ 604 605 /** PCI interrupt pin values */ 606 #define PCI_pin_mask 0x07 607 #define PCI_pin_none 0x00 608 #define PCI_pin_a 0x01 609 #define PCI_pin_b 0x02 610 #define PCI_pin_c 0x03 611 #define PCI_pin_d 0x04 612 #define PCI_pin_max 0x04 613 614 /** PCI Capability Codes */ 615 #define PCI_cap_id_reserved 0x00 616 #define PCI_cap_id_pm 0x01 /* Power management */ 617 #define PCI_cap_id_agp 0x02 /* AGP */ 618 #define PCI_cap_id_vpd 0x03 /* Vital product data */ 619 #define PCI_cap_id_slotid 0x04 /* Slot ID */ 620 #define PCI_cap_id_msi 0x05 /* Message signalled interrupt */ 621 #define PCI_cap_id_chswp 0x06 /* Compact PCI HotSwap */ 622 #define PCI_cap_id_pcix 0x07 /* PCI-X */ 623 #define PCI_cap_id_ldt 0x08 624 #define PCI_cap_id_vendspec 0x09 625 #define PCI_cap_id_debugport 0x0a 626 #define PCI_cap_id_cpci_rsrcctl 0x0b 627 #define PCI_cap_id_hotplug 0x0c 628 #define PCI_cap_id_pcie 0x10 /* PCIe (PCI express) */ 629 #define PCI_cap_id_msix 0x11 /* MSI-X */ 630 #define PCI_cap_id_sata 0x12 /* Serial ATA Capability */ 631 632 /** Power Management Control Status Register settings */ 633 #define PCI_pm_mask 0x03 634 #define PCI_pm_ctrl 0x02 635 #define PCI_pm_d1supp 0x0200 636 #define PCI_pm_d2supp 0x0400 637 #define PCI_pm_status 0x04 638 #define PCI_pm_state_d0 0x00 639 #define PCI_pm_state_d1 0x01 640 #define PCI_pm_state_d2 0x02 641 #define PCI_pm_state_d3 0x03 642 643 #ifdef __cplusplus 644 } 645 #endif 646 647 #endif /* _PCI_H */ 648