1 /******************************************************************************* 2 / 3 / File: PCI.h 4 / 5 / Description: Interface to the PCI bus. 6 / For more information, see "PCI Local Bus Specification, Revision 2.1", 7 / PCI Special Interest Group, 1995. 8 / 9 / Copyright 1993-98, Be Incorporated, All Rights Reserved. 10 / 11 *******************************************************************************/ 12 13 14 #ifndef _PCI_H 15 #define _PCI_H 16 17 //#include <BeBuild.h> 18 //#include <SupportDefs.h> 19 #include <bus_manager.h> 20 21 #ifdef __cplusplus 22 extern "C" { 23 #endif 24 25 26 /* ----- 27 pci device info 28 ----- */ 29 30 typedef struct pci_info { 31 ushort vendor_id; /* vendor id */ 32 ushort device_id; /* device id */ 33 uchar bus; /* bus number */ 34 uchar device; /* device number on bus */ 35 uchar function; /* function number in device */ 36 uchar revision; /* revision id */ 37 uchar class_api; /* specific register interface type */ 38 uchar class_sub; /* specific device function */ 39 uchar class_base; /* device type (display vs network, etc) */ 40 uchar line_size; /* cache line size in 32 bit words */ 41 uchar latency; /* latency timer */ 42 uchar header_type; /* header type */ 43 uchar bist; /* built-in self-test */ 44 uchar reserved; /* filler, for alignment */ 45 union { 46 struct { 47 uint32 cardbus_cis; /* CardBus CIS pointer */ 48 ushort subsystem_id; /* subsystem (add-in card) id */ 49 ushort subsystem_vendor_id; /* subsystem (add-in card) vendor id */ 50 uint32 rom_base; /* rom base address, viewed from host */ 51 uint32 rom_base_pci; /* rom base addr, viewed from pci */ 52 uint32 rom_size; /* rom size */ 53 uint32 base_registers[6]; /* base registers, viewed from host */ 54 uint32 base_registers_pci[6]; /* base registers, viewed from pci */ 55 uint32 base_register_sizes[6]; /* size of what base regs point to */ 56 uchar base_register_flags[6]; /* flags from base address fields */ 57 uchar interrupt_line; /* interrupt line */ 58 uchar interrupt_pin; /* interrupt pin */ 59 uchar min_grant; /* burst period @ 33 Mhz */ 60 uchar max_latency; /* how often PCI access needed */ 61 } h0; 62 struct { 63 uint32 base_registers[2]; /* base registers, viewed from host */ 64 uint32 base_registers_pci[2]; /* base registers, viewed from pci */ 65 uint32 base_register_sizes[2]; /* size of what base regs point to */ 66 uchar base_register_flags[2]; /* flags from base address fields */ 67 uchar primary_bus; 68 uchar secondary_bus; 69 uchar subordinate_bus; 70 uchar secondary_latency; 71 uchar io_base; 72 uchar io_limit; 73 ushort secondary_status; 74 ushort memory_base; 75 ushort memory_limit; 76 ushort prefetchable_memory_base; 77 ushort prefetchable_memory_limit; 78 uint32 prefetchable_memory_base_upper32; 79 uint32 prefetchable_memory_limit_upper32; 80 ushort io_base_upper16; 81 ushort io_limit_upper16; 82 uint32 rom_base; /* rom base address, viewed from host */ 83 uint32 rom_base_pci; /* rom base addr, viewed from pci */ 84 uchar interrupt_line; /* interrupt line */ 85 uchar interrupt_pin; /* interrupt pin */ 86 ushort bridge_control; 87 ushort subsystem_id; /* subsystem (add-in card) id */ 88 ushort subsystem_vendor_id; /* subsystem (add-in card) vendor id */ 89 } h1; 90 struct { 91 ushort subsystem_id; /* subsystem (add-in card) id */ 92 ushort subsystem_vendor_id; /* subsystem (add-in card) vendor id */ 93 94 #ifdef __HAIKU_PCI_BUS_MANAGER_TESTING 95 // for testing only, not final (do not use!): 96 uchar primary_bus; 97 uchar secondary_bus; 98 uchar subordinate_bus; 99 uchar secondary_latency; 100 ushort reserved; 101 uint32 memory_base; 102 uint32 memory_limit; 103 uint32 memory_base_upper32; 104 uint32 memory_limit_upper32; 105 uint32 io_base; 106 uint32 io_limit; 107 uint32 io_base_upper32; 108 uint32 io_limit_upper32; 109 ushort secondary_status; 110 ushort bridge_control; 111 #endif /* __HAIKU_PCI_BUS_MANAGER_TESTING */ 112 } h2; 113 } u; 114 } pci_info; 115 116 117 typedef struct pci_module_info pci_module_info; 118 119 struct pci_module_info { 120 bus_manager_info binfo; 121 122 uint8 (*read_io_8) (int mapped_io_addr); 123 void (*write_io_8) (int mapped_io_addr, uint8 value); 124 uint16 (*read_io_16) (int mapped_io_addr); 125 void (*write_io_16) (int mapped_io_addr, uint16 value); 126 uint32 (*read_io_32) (int mapped_io_addr); 127 void (*write_io_32) (int mapped_io_addr, uint32 value); 128 129 long (*get_nth_pci_info) ( 130 long index, /* index into pci device table */ 131 pci_info *info /* caller-supplied buffer for info */ 132 ); 133 uint32 (*read_pci_config) ( 134 uint8 bus, /* bus number */ 135 uint8 device, /* device # on bus */ 136 uint8 function, /* function # in device */ 137 uint16 offset, /* offset in configuration space */ 138 uint8 size /* # bytes to read (1, 2 or 4) */ 139 ); 140 void (*write_pci_config) ( 141 uint8 bus, /* bus number */ 142 uint8 device, /* device # on bus */ 143 uint8 function, /* function # in device */ 144 uint16 offset, /* offset in configuration space */ 145 uint8 size, /* # bytes to write (1, 2 or 4) */ 146 uint32 value /* value to write */ 147 ); 148 149 phys_addr_t (*ram_address) (phys_addr_t physical_address_in_system_memory); 150 151 status_t (*find_pci_capability) ( 152 uchar bus, 153 uchar device, 154 uchar function, 155 uchar cap_id, 156 uchar *offset 157 ); 158 159 status_t (*reserve_device) ( 160 uchar bus, 161 uchar device, 162 uchar function, 163 const char *driver_name, 164 void *cookie); 165 status_t (*unreserve_device) ( 166 uchar bus, 167 uchar device, 168 uchar function, 169 const char *driver_name, 170 void *cookie); 171 172 status_t (*update_interrupt_line) ( 173 uchar bus, 174 uchar device, 175 uchar function, 176 uchar newInterruptLineValue); 177 178 status_t (*find_pci_extended_capability) ( 179 uint8 bus, 180 uint8 device, 181 uint8 function, 182 uint16 cap_id, 183 uint16 *offset 184 ); 185 }; 186 187 #define B_PCI_MODULE_NAME "bus_managers/pci/v1" 188 189 /* --- 190 offsets in PCI configuration space to the elements of the predefined 191 header common to all header types 192 --- */ 193 194 #define PCI_vendor_id 0x00 /* (2 byte) vendor id */ 195 #define PCI_device_id 0x02 /* (2 byte) device id */ 196 #define PCI_command 0x04 /* (2 byte) command */ 197 #define PCI_status 0x06 /* (2 byte) status */ 198 #define PCI_revision 0x08 /* (1 byte) revision id */ 199 #define PCI_class_api 0x09 /* (1 byte) specific register interface type */ 200 #define PCI_class_sub 0x0a /* (1 byte) specific device function */ 201 #define PCI_class_base 0x0b /* (1 byte) device type (display vs network, etc) */ 202 #define PCI_line_size 0x0c /* (1 byte) cache line size in 32 bit words */ 203 #define PCI_latency 0x0d /* (1 byte) latency timer */ 204 #define PCI_header_type 0x0e /* (1 byte) header type */ 205 #define PCI_bist 0x0f /* (1 byte) built-in self-test */ 206 207 #define PCI_extended_capability 0x100 /* (4 bytes) extended capability */ 208 209 210 /* --- 211 offsets in PCI configuration space to the elements of the predefined 212 header common to header types 0x00 and 0x01 213 --- */ 214 #define PCI_base_registers 0x10 /* base registers (size varies) */ 215 #define PCI_interrupt_line 0x3c /* (1 byte) interrupt line */ 216 #define PCI_interrupt_pin 0x3d /* (1 byte) interrupt pin */ 217 218 219 220 /* --- 221 offsets in PCI configuration space to the elements of header type 0x00 222 --- */ 223 224 #define PCI_cardbus_cis 0x28 /* (4 bytes) CardBus CIS (Card Information Structure) pointer (see PCMCIA v2.10 Spec) */ 225 #define PCI_subsystem_vendor_id 0x2c /* (2 bytes) subsystem (add-in card) vendor id */ 226 #define PCI_subsystem_id 0x2e /* (2 bytes) subsystem (add-in card) id */ 227 #define PCI_rom_base 0x30 /* (4 bytes) expansion rom base address */ 228 #define PCI_capabilities_ptr 0x34 /* (1 byte) pointer to the start of the capabilities list */ 229 #define PCI_min_grant 0x3e /* (1 byte) burst period @ 33 Mhz */ 230 #define PCI_max_latency 0x3f /* (1 byte) how often PCI access needed */ 231 232 233 /* --- 234 offsets in PCI configuration space to the elements of header type 0x01 (PCI-to-PCI bridge) 235 --- */ 236 237 #define PCI_primary_bus 0x18 /* (1 byte) */ 238 #define PCI_secondary_bus 0x19 /* (1 byte) */ 239 #define PCI_subordinate_bus 0x1A /* (1 byte) */ 240 #define PCI_secondary_latency 0x1B /* (1 byte) latency of secondary bus */ 241 #define PCI_io_base 0x1C /* (1 byte) io base address register for 2ndry bus*/ 242 #define PCI_io_limit 0x1D /* (1 byte) */ 243 #define PCI_secondary_status 0x1E /* (2 bytes) */ 244 #define PCI_memory_base 0x20 /* (2 bytes) */ 245 #define PCI_memory_limit 0x22 /* (2 bytes) */ 246 #define PCI_prefetchable_memory_base 0x24 /* (2 bytes) */ 247 #define PCI_prefetchable_memory_limit 0x26 /* (2 bytes) */ 248 #define PCI_prefetchable_memory_base_upper32 0x28 249 #define PCI_prefetchable_memory_limit_upper32 0x2C 250 #define PCI_io_base_upper16 0x30 /* (2 bytes) */ 251 #define PCI_io_limit_upper16 0x32 /* (2 bytes) */ 252 #define PCI_sub_vendor_id_1 0x34 /* (2 bytes) */ 253 #define PCI_sub_device_id_1 0x36 /* (2 bytes) */ 254 #define PCI_bridge_rom_base 0x38 255 #define PCI_bridge_control 0x3E /* (2 bytes) */ 256 257 258 /* PCI type 2 header offsets */ 259 #define PCI_capabilities_ptr_2 0x14 /* (1 byte) */ 260 #define PCI_secondary_status_2 0x16 /* (2 bytes) */ 261 #define PCI_primary_bus_2 0x18 /* (1 byte) */ 262 #define PCI_secondary_bus_2 0x19 /* (1 byte) */ 263 #define PCI_subordinate_bus_2 0x1A /* (1 byte) */ 264 #define PCI_secondary_latency_2 0x1B /* (1 byte) latency of secondary bus */ 265 #define PCI_memory_base0_2 0x1C /* (4 bytes) */ 266 #define PCI_memory_limit0_2 0x20 /* (4 bytes) */ 267 #define PCI_memory_base1_2 0x24 /* (4 bytes) */ 268 #define PCI_memory_limit1_2 0x28 /* (4 bytes) */ 269 #define PCI_io_base0_2 0x2c /* (4 bytes) */ 270 #define PCI_io_limit0_2 0x30 /* (4 bytes) */ 271 #define PCI_io_base1_2 0x34 /* (4 bytes) */ 272 #define PCI_io_limit1_2 0x38 /* (4 bytes) */ 273 #define PCI_bridge_control_2 0x3E /* (2 bytes) */ 274 275 #define PCI_sub_vendor_id_2 0x40 /* (2 bytes) */ 276 #define PCI_sub_device_id_2 0x42 /* (2 bytes) */ 277 278 #define PCI_card_interface_2 0x44 /* ?? */ 279 280 /* --- 281 values for the class_base field in the common header 282 --- */ 283 284 #define PCI_early 0x00 /* built before class codes defined */ 285 #define PCI_mass_storage 0x01 /* mass storage_controller */ 286 #define PCI_network 0x02 /* network controller */ 287 #define PCI_display 0x03 /* display controller */ 288 #define PCI_multimedia 0x04 /* multimedia device */ 289 #define PCI_memory 0x05 /* memory controller */ 290 #define PCI_bridge 0x06 /* bridge controller */ 291 #define PCI_simple_communications 0x07 /* simple communications controller */ 292 #define PCI_base_peripheral 0x08 /* base system peripherals */ 293 #define PCI_input 0x09 /* input devices */ 294 #define PCI_docking_station 0x0a /* docking stations */ 295 #define PCI_processor 0x0b /* processors */ 296 #define PCI_serial_bus 0x0c /* serial bus controllers */ 297 #define PCI_wireless 0x0d /* wireless controllers */ 298 #define PCI_intelligent_io 0x0e 299 #define PCI_satellite_communications 0x0f 300 #define PCI_encryption_decryption 0x10 301 #define PCI_data_acquisition 0x11 302 303 #define PCI_undefined 0xFF /* not in any defined class */ 304 305 306 /* --- 307 values for the class_sub field for class_base = 0x00 (built before 308 class codes were defined) 309 --- */ 310 311 #define PCI_early_not_vga 0x00 /* all except vga */ 312 #define PCI_early_vga 0x01 /* vga devices */ 313 314 315 /* --- 316 values for the class_sub field for class_base = 0x01 (mass storage) 317 --- */ 318 319 #define PCI_scsi 0x00 /* SCSI controller */ 320 #define PCI_ide 0x01 /* IDE controller */ 321 #define PCI_floppy 0x02 /* floppy disk controller */ 322 #define PCI_ipi 0x03 /* IPI bus controller */ 323 #define PCI_raid 0x04 /* RAID controller */ 324 #define PCI_ata 0x05 /* ATA controller with ADMA interface */ 325 #define PCI_sata 0x06 /* Serial ATA controller */ 326 #define PCI_sas 0x07 /* Serial Attached SCSI controller */ 327 #define PCI_nvm 0x08 /* NVM Express controller */ 328 #define PCI_ufs 0x09 /* Universal Flash Storage controller */ 329 #define PCI_mass_storage_other 0x80 /* other mass storage controller */ 330 331 /* --- 332 bit mask of the class_api field for 333 class_base = 0x01 (mass storage) 334 class_sub = 0x01 (IDE controller) 335 --- */ 336 337 #define PCI_ide_primary_native 0x01 /* primary channel is in native mode */ 338 #define PCI_ide_primary_fixed 0x02 /* primary channel can be switched to native mode */ 339 #define PCI_ide_secondary_native 0x04 /* secondary channel is in native mode */ 340 #define PCI_ide_secondary_fixed 0x08 /* secondary channel can be switched to native mode */ 341 #define PCI_ide_master 0x80 /* master device */ 342 343 /* --- 344 values of the class_api field for 345 class_base = 0x01 (mass storage) 346 class_sub = 0x06 (Serial ATA controller) 347 --- */ 348 349 #define PCI_sata_other 0x00 /* vendor specific interface */ 350 #define PCI_sata_ahci 0x01 /* AHCI interface */ 351 352 /* --- 353 values of the class_api field for 354 class_base = 0x01 (mass storage) 355 class_sub = 0x08 (NVM Express controller) 356 --- */ 357 358 #define PCI_nvm_other 0x00 /* vendor specific interface */ 359 #define PCI_nvm_hci 0x01 /* NVMHCI interface 1.0 */ 360 #define PCI_nvm_hci_enterprise 0x02 /* NVMHCI enterprise */ 361 362 /* --- 363 values of the class_api field for 364 class_base = 0x01 (mass storage) 365 class_sub = 0x09 (Universal Flash Storage controller) 366 --- */ 367 368 #define PCI_ufs_other 0x00 /* vendor specific interface */ 369 #define PCI_ufs_hci 0x01 /* UFSHCI interface */ 370 371 /* --- 372 values for the class_sub field for class_base = 0x02 (network) 373 --- */ 374 375 #define PCI_ethernet 0x00 /* Ethernet controller */ 376 #define PCI_token_ring 0x01 /* Token Ring controller */ 377 #define PCI_fddi 0x02 /* FDDI controller */ 378 #define PCI_atm 0x03 /* ATM controller */ 379 #define PCI_isdn 0x04 /* ISDN controller */ 380 #define PCI_worldfip 0x05 /* WorldFip controller */ 381 #define PCI_picmg 0x06 /* PICMG controller */ 382 #define PCI_network_infiniband 0x07 /* InfiniBand controller */ 383 #define PCI_hfc 0x08 /* Host fabric controller */ 384 #define PCI_network_other 0x80 /* other network controller */ 385 386 387 /* --- 388 values for the class_sub field for class_base = 0x03 (display) 389 --- */ 390 391 #define PCI_vga 0x00 /* VGA controller */ 392 #define PCI_xga 0x01 /* XGA controller */ 393 #define PCI_3d 0x02 /* 3d controller */ 394 #define PCI_display_other 0x80 /* other display controller */ 395 396 397 /* --- 398 values for the class_sub field for class_base = 0x04 (multimedia device) 399 --- */ 400 401 #define PCI_video 0x00 /* video */ 402 #define PCI_audio 0x01 /* audio */ 403 #define PCI_telephony 0x02 /* computer telephony device */ 404 #define PCI_hd_audio 0x03 /* HD audio */ 405 #define PCI_multimedia_other 0x80 /* other multimedia device */ 406 407 408 /* --- 409 values of the class_api field for 410 class_base = 0x04 (multimedia device) 411 class_sub = 0x03 (HD audio) 412 --- */ 413 414 #define PCI_hd_audio_vendor 0x80 /* with additional vendor specific extensions */ 415 416 /* --- 417 values for the class_sub field for class_base = 0x05 (memory) 418 --- */ 419 420 #define PCI_ram 0x00 /* RAM */ 421 #define PCI_flash 0x01 /* flash */ 422 #define PCI_memory_other 0x80 /* other memory controller */ 423 424 425 /* --- 426 values for the class_sub field for class_base = 0x06 (bridge) 427 --- */ 428 429 #define PCI_host 0x00 /* host bridge */ 430 #define PCI_isa 0x01 /* ISA bridge */ 431 #define PCI_eisa 0x02 /* EISA bridge */ 432 #define PCI_microchannel 0x03 /* MicroChannel bridge */ 433 #define PCI_pci 0x04 /* PCI-to-PCI bridge */ 434 #define PCI_pcmcia 0x05 /* PCMCIA bridge */ 435 #define PCI_nubus 0x06 /* NuBus bridge */ 436 #define PCI_cardbus 0x07 /* CardBus bridge */ 437 #define PCI_raceway 0x08 /* RACEway bridge */ 438 #define PCI_bridge_transparent 0x09 /* PCI transparent */ 439 #define PCI_bridge_infiniband 0x0a /* Infiniband */ 440 #define PCI_bridge_as_pci 0x0b /* Advanced Switching to PCI host bridge */ 441 #define PCI_bridge_other 0x80 /* other bridge device */ 442 443 /* --- 444 values of the class_api field for 445 class_base = 0x06 (bridge), and 446 class_sub = 0x0b (Advanced Switching to PCI host bridge) 447 --- */ 448 449 #define PCI_bridge_as_pci_asi_sig 0x01 /* ASI-SIG Defined Portal Interface */ 450 451 /* --- 452 values for the class_sub field for class_base = 0x07 (simple 453 communications controllers) 454 --- */ 455 456 #define PCI_serial 0x00 /* serial port controller */ 457 #define PCI_parallel 0x01 /* parallel port */ 458 #define PCI_multiport_serial 0x02 /* multiport serial controller */ 459 #define PCI_modem 0x03 /* modem */ 460 #define PCI_gpib 0x04 /* GPIB controller */ 461 #define PCI_smart_card 0x05 /* Smard Card controller */ 462 #define PCI_simple_communications_other 0x80 /* other communications device */ 463 464 /* --- 465 values of the class_api field for 466 class_base = 0x07 (simple communications), and 467 class_sub = 0x00 (serial port controller) 468 --- */ 469 470 #define PCI_serial_xt 0x00 /* XT-compatible serial controller */ 471 #define PCI_serial_16450 0x01 /* 16450-compatible serial controller */ 472 #define PCI_serial_16550 0x02 /* 16550-compatible serial controller */ 473 474 475 /* --- 476 values of the class_api field for 477 class_base = 0x07 (simple communications), and 478 class_sub = 0x01 (parallel port) 479 --- */ 480 481 #define PCI_parallel_simple 0x00 /* simple (output-only) parallel port */ 482 #define PCI_parallel_bidirectional 0x01 /* bidirectional parallel port */ 483 #define PCI_parallel_ecp 0x02 /* ECP 1.x compliant parallel port */ 484 485 486 /* --- 487 values for the class_sub field for class_base = 0x08 (generic 488 system peripherals) 489 --- */ 490 491 #define PCI_pic 0x00 /* peripheral interrupt controller */ 492 #define PCI_dma 0x01 /* dma controller */ 493 #define PCI_timer 0x02 /* timers */ 494 #define PCI_rtc 0x03 /* real time clock */ 495 #define PCI_generic_hot_plug 0x04 /* generic PCI hot-plug controller */ 496 #define PCI_sd_host 0x05 /* SD Host controller */ 497 #define PCI_iommu 0x06 /* IOMMU */ 498 #define PCI_rcec 0x07 /* Root Complex Event Collector */ 499 #define PCI_system_peripheral_other 0x80 /* other generic system peripheral */ 500 501 /* --- 502 values of the class_api field for 503 class_base = 0x08 (generic system peripherals) 504 class_sub = 0x00 (peripheral interrupt controller) 505 --- */ 506 507 #define PCI_pic_8259 0x00 /* generic 8259 */ 508 #define PCI_pic_isa 0x01 /* ISA pic */ 509 #define PCI_pic_eisa 0x02 /* EISA pic */ 510 511 /* --- 512 values of the class_api field for 513 class_base = 0x08 (generic system peripherals) 514 class_sub = 0x01 (dma controller) 515 --- */ 516 517 #define PCI_dma_8237 0x00 /* generic 8237 */ 518 #define PCI_dma_isa 0x01 /* ISA dma */ 519 #define PCI_dma_eisa 0x02 /* EISA dma */ 520 521 /* --- 522 values of the class_api field for 523 class_base = 0x08 (generic system peripherals) 524 class_sub = 0x02 (timer) 525 --- */ 526 527 #define PCI_timer_8254 0x00 /* generic 8254 */ 528 #define PCI_timer_isa 0x01 /* ISA timer */ 529 #define PCI_timer_eisa 0x02 /* EISA timers (2 timers) */ 530 531 532 /* --- 533 values of the class_api field for 534 class_base = 0x08 (generic system peripherals) 535 class_sub = 0x03 (real time clock 536 --- */ 537 538 #define PCI_rtc_generic 0x00 /* generic real time clock */ 539 #define PCI_rtc_isa 0x01 /* ISA real time clock */ 540 541 542 /* --- 543 values for the class_sub field for class_base = 0x09 (input devices) 544 --- */ 545 546 #define PCI_keyboard 0x00 /* keyboard controller */ 547 #define PCI_pen 0x01 /* pen */ 548 #define PCI_mouse 0x02 /* mouse controller */ 549 #define PCI_scanner 0x03 /* scanner controller */ 550 #define PCI_gameport 0x04 /* gameport controller */ 551 #define PCI_input_other 0x80 /* other input controller */ 552 553 554 /* --- 555 values for the class_sub field for class_base = 0x0a (docking stations) 556 --- */ 557 558 #define PCI_docking_generic 0x00 /* generic docking station */ 559 #define PCI_docking_other 0x80 /* other docking stations */ 560 561 /* --- 562 values for the class_sub field for class_base = 0x0b (processor) 563 --- */ 564 565 #define PCI_386 0x00 /* 386 */ 566 #define PCI_486 0x01 /* 486 */ 567 #define PCI_pentium 0x02 /* Pentium */ 568 #define PCI_alpha 0x10 /* Alpha */ 569 #define PCI_PowerPC 0x20 /* PowerPC */ 570 #define PCI_mips 0x30 /* MIPS */ 571 #define PCI_coprocessor 0x40 /* co-processor */ 572 573 /* --- 574 values for the class_sub field for class_base = 0x0c (serial bus 575 controller) 576 --- */ 577 578 #define PCI_firewire 0x00 /* FireWire (IEEE 1394) */ 579 #define PCI_access 0x01 /* ACCESS bus */ 580 #define PCI_ssa 0x02 /* SSA */ 581 #define PCI_usb 0x03 /* Universal Serial Bus */ 582 #define PCI_fibre_channel 0x04 /* Fibre channel */ 583 #define PCI_smbus 0x05 584 #define PCI_infiniband 0x06 585 #define PCI_ipmi 0x07 586 #define PCI_sercos 0x08 587 #define PCI_canbus 0x09 588 #define PCI_mipi_i3c 0x0a /* MIPI I3C Host Controller Interface */ 589 590 /* --- 591 values of the class_api field for 592 class_base = 0x0c ( serial bus controller ) 593 class_sub = 0x03 ( Universal Serial Bus ) 594 --- */ 595 596 #define PCI_usb_uhci 0x00 /* Universal Host Controller Interface */ 597 #define PCI_usb_ohci 0x10 /* Open Host Controller Interface */ 598 #define PCI_usb_ehci 0x20 /* Enhanced Host Controller Interface */ 599 #define PCI_usb_xhci 0x30 /* Extensible Host Controller Interface */ 600 #define PCI_usb_usb4 0x40 /* USB4 Host Interface */ 601 602 /* --- 603 values for the class_sub field for class_base = 0x0d (wireless controller) 604 --- */ 605 #define PCI_wireless_irda 0x00 606 #define PCI_wireless_consumer_ir 0x01 607 #define PCI_wireless_rf 0x10 608 #define PCI_wireless_bluetooth 0x11 609 #define PCI_wireless_broadband 0x12 610 #define PCI_wireless_80211A 0x20 611 #define PCI_wireless_80211B 0x21 612 #define PCI_wireless_cellular 0x40 613 #define PCI_wireless_cellular_ethernet 0x41 614 #define PCI_wireless_other 0x80 615 616 /* --- 617 masks for command register bits 618 --- */ 619 620 #define PCI_command_io 0x001 /* 1/0 i/o space en/disabled */ 621 #define PCI_command_memory 0x002 /* 1/0 memory space en/disabled */ 622 #define PCI_command_master 0x004 /* 1/0 pci master en/disabled */ 623 #define PCI_command_special 0x008 /* 1/0 pci special cycles en/disabled */ 624 #define PCI_command_mwi 0x010 /* 1/0 memory write & invalidate en/disabled */ 625 #define PCI_command_vga_snoop 0x020 /* 1/0 vga pallette snoop en/disabled */ 626 #define PCI_command_parity 0x040 /* 1/0 parity check en/disabled */ 627 #define PCI_command_address_step 0x080 /* 1/0 address stepping en/disabled */ 628 #define PCI_command_serr 0x100 /* 1/0 SERR# en/disabled */ 629 #define PCI_command_fastback 0x200 /* 1/0 fast back-to-back en/disabled */ 630 #define PCI_command_int_disable 0x400 /* 1/0 interrupt generation dis/enabled */ 631 632 633 /* --- 634 masks for status register bits 635 --- */ 636 637 #define PCI_status_capabilities 0x0010 /* capabilities list */ 638 #define PCI_status_66_MHz_capable 0x0020 /* 66 Mhz capable */ 639 #define PCI_status_udf_supported 0x0040 /* user-definable-features (udf) supported */ 640 #define PCI_status_fastback 0x0080 /* fast back-to-back capable */ 641 #define PCI_status_parity_signalled 0x0100 /* parity error signalled */ 642 #define PCI_status_devsel 0x0600 /* devsel timing (see below) */ 643 #define PCI_status_target_abort_signalled 0x0800 /* signaled a target abort */ 644 #define PCI_status_target_abort_received 0x1000 /* received a target abort */ 645 #define PCI_status_master_abort_received 0x2000 /* received a master abort */ 646 #define PCI_status_serr_signalled 0x4000 /* signalled SERR# */ 647 #define PCI_status_parity_error_detected 0x8000 /* parity error detected */ 648 649 650 /* --- 651 masks for devsel field in status register 652 --- */ 653 654 #define PCI_status_devsel_fast 0x0000 /* fast */ 655 #define PCI_status_devsel_medium 0x0200 /* medium */ 656 #define PCI_status_devsel_slow 0x0400 /* slow */ 657 658 659 /* --- 660 masks for header type register 661 --- */ 662 663 #define PCI_header_type_mask 0x7F /* header type field */ 664 #define PCI_multifunction 0x80 /* multifunction device flag */ 665 666 667 /** types of PCI header */ 668 669 #define PCI_header_type_generic 0x00 670 #define PCI_header_type_PCI_to_PCI_bridge 0x01 671 #define PCI_header_type_cardbus 0x02 672 673 674 /* --- 675 masks for built in self test (bist) register bits 676 --- */ 677 678 #define PCI_bist_code 0x0F /* self-test completion code, 0 = success */ 679 #define PCI_bist_start 0x40 /* 1 = start self-test */ 680 #define PCI_bist_capable 0x80 /* 1 = self-test capable */ 681 682 683 /** masks for flags in the various base address registers */ 684 685 #define PCI_address_space 0x01 /* 0 = memory space, 1 = i/o space */ 686 #define PCI_register_start 0x10 687 #define PCI_register_end 0x24 688 #define PCI_register_ppb_end 0x18 689 #define PCI_register_pcb_end 0x14 690 691 /** masks for flags in memory space base address registers */ 692 693 #define PCI_address_type_32 0x00 /* locate anywhere in 32 bit space */ 694 #define PCI_address_type_32_low 0x02 /* locate below 1 Meg */ 695 #define PCI_address_type_64 0x04 /* locate anywhere in 64 bit space */ 696 #define PCI_address_type 0x06 /* type (see below) */ 697 #define PCI_address_prefetchable 0x08 /* 1 if prefetchable (see PCI spec) */ 698 699 #define PCI_address_memory_32_mask 0xFFFFFFF0 /* mask to get 32bit memory space base address */ 700 701 702 /* --- 703 masks for flags in i/o space base address registers 704 --- */ 705 706 #define PCI_address_io_mask 0xFFFFFFFC /* mask to get i/o space base address */ 707 708 #define PCI_range_memory_mask 0xFFFFFFF0 /* mask to get memory ranges */ 709 710 711 /* --- 712 masks for flags in expansion rom base address registers 713 --- */ 714 715 #define PCI_rom_enable 0x00000001 /* 1 expansion rom decode enabled */ 716 #define PCI_rom_shadow 0x00000010 /* 2 rom copied at shadow (C0000) */ 717 #define PCI_rom_copy 0x00000100 /* 4 rom is allocated copy */ 718 #define PCI_rom_bios 0x00001000 /* 8 rom is bios copy */ 719 #define PCI_rom_address_mask 0xFFFFF800 /* mask to get expansion rom addr */ 720 721 /** PCI interrupt pin values */ 722 #define PCI_pin_mask 0x07 723 #define PCI_pin_none 0x00 724 #define PCI_pin_a 0x01 725 #define PCI_pin_b 0x02 726 #define PCI_pin_c 0x03 727 #define PCI_pin_d 0x04 728 #define PCI_pin_max 0x04 729 730 /** PCI bridge control register bits */ 731 #define PCI_bridge_parity_error_response 0x0001 /* 1/0 Parity Error Response */ 732 #define PCI_bridge_serr 0x0002 /* 1/0 SERR# en/disabled */ 733 #define PCI_bridge_isa 0x0004 /* 1/0 ISA en/disabled */ 734 #define PCI_bridge_vga 0x0008 /* 1/0 VGA en/disabled */ 735 #define PCI_bridge_master_abort 0x0020 /* 1/0 Master Abort mode */ 736 #define PCI_bridge_secondary_bus_reset 0x0040 /* 1/0 Secondary bus reset */ 737 #define PCI_bridge_secondary_bus_fastback 0x0080 /* 1/0 fast back-to-back en/disabled */ 738 #define PCI_bridge_primary_discard_timeout 0x0100 /* 1/0 primary discard timeout */ 739 #define PCI_bridge_secondary_discard_timeout 0x0200 /* 1/0 secondary discard timeout */ 740 #define PCI_bridge_discard_timer_status 0x0400 /* 1/0 discard timer status */ 741 #define PCI_bridge_discard_timer_serr 0x0800 /* 1/0 discard timer serr */ 742 743 /** PCI Capability Codes */ 744 #define PCI_cap_id_reserved 0x00 745 #define PCI_cap_id_pm 0x01 /* Power management */ 746 #define PCI_cap_id_agp 0x02 /* AGP */ 747 #define PCI_cap_id_vpd 0x03 /* Vital product data */ 748 #define PCI_cap_id_slotid 0x04 /* Slot ID */ 749 #define PCI_cap_id_msi 0x05 /* Message signalled interrupt */ 750 #define PCI_cap_id_chswp 0x06 /* Compact PCI HotSwap */ 751 #define PCI_cap_id_pcix 0x07 /* PCI-X */ 752 #define PCI_cap_id_ht 0x08 /* HyperTransport */ 753 #define PCI_cap_id_vendspec 0x09 754 #define PCI_cap_id_debugport 0x0a 755 #define PCI_cap_id_cpci_rsrcctl 0x0b 756 #define PCI_cap_id_hotplug 0x0c 757 #define PCI_cap_id_subvendor 0x0d 758 #define PCI_cap_id_agp8x 0x0e 759 #define PCI_cap_id_secure_dev 0x0f 760 #define PCI_cap_id_pcie 0x10 /* PCIe (PCI express) */ 761 #define PCI_cap_id_msix 0x11 /* MSI-X */ 762 #define PCI_cap_id_sata 0x12 /* Serial ATA Capability */ 763 #define PCI_cap_id_pciaf 0x13 /* PCI Advanced Features */ 764 #define PCI_cap_id_ea 0x14 /* Extended Allocation */ 765 #define PCI_cap_id_fpb 0x15 /* Flattening Portal Bridge */ 766 767 /** PCI Extended Capabilities */ 768 #define PCI_extcap_id(x) (x & 0x0000ffff) 769 #define PCI_extcap_version(x) ((x & 0x000f0000) >> 16) 770 #define PCI_extcap_next_ptr(x) ((x & 0xfff00000) >> 20) 771 772 #define PCI_extcap_id_aer 0x0001 /* Advanced Error Reporting */ 773 #define PCI_extcap_id_vc 0x0002 /* Virtual Channel */ 774 #define PCI_extcap_id_serial 0x0003 /* Serial Number */ 775 #define PCI_extcap_id_power_budget 0x0004 /* Power Budgeting */ 776 #define PCI_extcap_id_rcl_decl 0x0005 /* Root Complex Link Declaration */ 777 #define PCI_extcap_id_rcil_ctl 0x0006 /* Root Complex Internal Link Control */ 778 #define PCI_extcap_id_rcec_assoc 0x0007 /* Root Complex Event Collector Association */ 779 #define PCI_extcap_id_mfvc 0x0008 /* MultiFunction Virtual Channel */ 780 #define PCI_extcap_id_vc2 0x0009 /* Virtual Channel 2 */ 781 #define PCI_extcap_id_rcrb_header 0x000a /* RCRB Header */ 782 #define PCI_extcap_id_vendor 0x000b /* Vendor Unique */ 783 #define PCI_extcap_id_acs 0x000d /* Access Control Services */ 784 #define PCI_extcap_id_ari 0x000e /* Alternative Routing Id Interpretation */ 785 #define PCI_extcap_id_ats 0x000f /* Address Translation Services */ 786 #define PCI_extcap_id_srio_virtual 0x0010 /* Single Root I/O Virtualization */ 787 #define PCI_extcap_id_mrio_virtual 0x0011 /* Multiple Root I/O Virtual */ 788 #define PCI_extcap_id_multicast 0x0012 /* Multicast */ 789 #define PCI_extcap_id_page_request 0x0013 /* Page Request */ 790 #define PCI_extcap_id_amd 0x0014 /* AMD Reserved */ 791 #define PCI_extcap_id_resizable_bar 0x0015 /* Resizable Bar */ 792 #define PCI_extcap_id_dyn_power_alloc 0x0016 /* Dynamic Power Allocation */ 793 #define PCI_extcap_id_tph_requester 0x0017 /* TPH Requester */ 794 #define PCI_extcap_id_latency_tolerance 0x0018 /* Latency Tolerance Reporting */ 795 #define PCI_extcap_id_2ndpcie 0x0019 /* Secondary PCIe */ 796 #define PCI_extcap_id_pmux 0x001a /* Protocol Multiplexing */ 797 #define PCI_extcap_id_pasid 0x001b /* Process Address Space Id */ 798 #define PCI_extcap_id_ln_requester 0x001c /* LN Requester */ 799 #define PCI_extcap_id_dpc 0x001d /* Downstream Porto Containment */ 800 #define PCI_extcap_id_l1pm 0x001e /* L1 Power Management Substates */ 801 #define PCI_extcap_id_ptm 0x001f /* Precision Time Measurement */ 802 #define PCI_extcap_id_m_pcie 0x0020 /* PCIe over M-PHY */ 803 #define PCI_extcap_id_frs 0x0021 /* FRS Queuing */ 804 #define PCI_extcap_id_rtr 0x0022 /* Readiness Time Reporting */ 805 #define PCI_extcap_id_dvsec 0x0023 /* Designated Vendor-Specific */ 806 #define PCI_extcap_id_vf_resizable_bar 0x0024 /* VF Resizable BAR */ 807 #define PCI_extcap_id_datalink 0x0025 /* Data Link Feature */ 808 #define PCI_extcap_id_16gt 0x0026 /* Physical Layer 16.0 GT/s */ 809 #define PCI_extcap_id_lmr 0x0027 /* Lane Marging at the Receiver */ 810 #define PCI_extcap_id_hierarchy_id 0x0028 /* Hierarchy ID */ 811 #define PCI_extcap_id_npem 0x0029 /* Native PCIe Enclosure Management */ 812 #define PCI_extcap_id_pl32 0x002a /* Physical Layer 32.0 GT/s */ 813 #define PCI_extcap_id_ap 0x002b /* Alternate Protocol */ 814 #define PCI_extcap_id_sfi 0x002c /* System Firmware Intermediary */ 815 #define PCI_extcap_id_sf 0x002d /* Shadow Functions */ 816 #define PCI_extcap_id_doe 0x002e /* Data Object Exchange */ 817 818 /** Power Management Control Status Register settings */ 819 #define PCI_pm_mask 0x03 820 #define PCI_pm_ctrl 0x02 821 #define PCI_pm_d1supp 0x0200 822 #define PCI_pm_d2supp 0x0400 823 #define PCI_pm_status 0x04 824 #define PCI_pm_state_d0 0x00 825 #define PCI_pm_state_d1 0x01 826 #define PCI_pm_state_d2 0x02 827 #define PCI_pm_state_d3 0x03 828 829 /** MSI registers **/ 830 #define PCI_msi_control 0x02 831 #define PCI_msi_address 0x04 832 #define PCI_msi_address_high 0x08 833 #define PCI_msi_data 0x08 834 #define PCI_msi_data_64bit 0x0c 835 #define PCI_msi_mask 0x10 836 #define PCI_msi_pending 0x14 837 838 /** MSI control register values **/ 839 #define PCI_msi_control_enable 0x0001 840 #define PCI_msi_control_vector 0x0100 841 #define PCI_msi_control_64bit 0x0080 842 #define PCI_msi_control_mme_mask 0x0070 843 #define PCI_msi_control_mme_1 0x0000 844 #define PCI_msi_control_mme_2 0x0010 845 #define PCI_msi_control_mme_4 0x0020 846 #define PCI_msi_control_mme_8 0x0030 847 #define PCI_msi_control_mme_16 0x0040 848 #define PCI_msi_control_mme_32 0x0050 849 #define PCI_msi_control_mmc_mask 0x000e 850 #define PCI_msi_control_mmc_1 0x0000 851 #define PCI_msi_control_mmc_2 0x0002 852 #define PCI_msi_control_mmc_4 0x0004 853 #define PCI_msi_control_mmc_8 0x0006 854 #define PCI_msi_control_mmc_16 0x0008 855 #define PCI_msi_control_mmc_32 0x000a 856 857 /** MSI-X registers **/ 858 #define PCI_msix_control 0x02 859 #define PCI_msix_table 0x04 860 #define PCI_msix_pba 0x08 861 862 #define PCI_msix_control_table_size 0x07ff 863 #define PCI_msix_control_function_mask 0x4000 864 #define PCI_msix_control_enable 0x8000 865 #define PCI_msix_bir_mask 0x0007 866 #define PCI_msix_bir_0 0x10 867 #define PCI_msix_bir_1 0x14 868 #define PCI_msix_bir_2 0x18 869 #define PCI_msix_bir_3 0x1c 870 #define PCI_msix_bir_4 0x20 871 #define PCI_msix_bir_5 0x24 872 #define PCI_msix_offset_mask 0xfff8 873 874 #define PCI_msix_vctrl_mask 0x0001 875 876 /** HyperTransport registers **/ 877 #define PCI_ht_command 0x02 878 #define PCI_ht_msi_address_low 0x04 879 #define PCI_ht_msi_address_high 0x08 880 881 #define PCI_ht_command_cap_mask_3_bits 0xe000 882 #define PCI_ht_command_cap_mask_5_bits 0xf800 883 #define PCI_ht_command_cap_slave 0x0000 884 #define PCI_ht_command_cap_host 0x2000 885 #define PCI_ht_command_cap_switch 0x4000 886 #define PCI_ht_command_cap_interrupt 0x8000 887 #define PCI_ht_command_cap_revision_id 0x8800 888 #define PCI_ht_command_cap_unit_id_clumping 0x9000 889 #define PCI_ht_command_cap_ext_config_space 0x9800 890 #define PCI_ht_command_cap_address_mapping 0xa000 891 #define PCI_ht_command_cap_msi_mapping 0xa800 892 #define PCI_ht_command_cap_direct_route 0xb000 893 #define PCI_ht_command_cap_vcset 0xb800 894 #define PCI_ht_command_cap_retry_mode 0xc000 895 #define PCI_ht_command_cap_x86_encoding 0xc800 896 #define PCI_ht_command_cap_gen3 0xd000 897 #define PCI_ht_command_cap_fle 0xd800 898 #define PCI_ht_command_cap_pm 0xe000 899 #define PCI_ht_command_cap_high_node_count 0xe800 900 901 #define PCI_ht_command_msi_enable 0x0001 902 #define PCI_ht_command_msi_fixed 0x0002 903 904 #ifdef __cplusplus 905 } 906 #endif 907 908 #endif /* _PCI_H */ 909