1*a5061eceSAdrien DestuguesSDHCI MMC Driver 2*a5061eceSAdrien Destugues================ 3*a5061eceSAdrien Destugues 4*a5061eceSAdrien DestuguesThis driver project is a part of GSoC’18 and is aimed at providing 5*a5061eceSAdrien Destuguessupport for PCI devices with class 8 and subclass 5 over x86 6*a5061eceSAdrien Destuguesarchitecture. This document will make you familiar with the `code 7*a5061eceSAdrien Destuguesproduced during GSoC <https://review.haiku-os.org/#/c/haiku/+/318/>`__, 8*a5061eceSAdrien Destuguesloading and testing the driver(including hardware emulation), insight 9*a5061eceSAdrien Destuguesinto the code and future tasks. 10*a5061eceSAdrien Destugues 11*a5061eceSAdrien DestuguesFor detailed explanations about the project, you can refer the `weekly 12*a5061eceSAdrien Destuguesreports <https://www.haiku-os.org/blog/krish_iyer>`__ and comment issues 13*a5061eceSAdrien Destuguesif any. For this project we have referred `SD Host Controller Spec 14*a5061eceSAdrien DestuguesVersion 15*a5061eceSAdrien Destugues1.00 <https://www.sdcard.org/downloads/pls/pdf/index.php?p=PartA2_SD_Host_Controller_Simplified_Specification_Ver1.00.jpg&f=PartA2_SD_Host_Controller_Simplified_Specification_Ver1.00.pdf&e=EN_A2100>`__ 16*a5061eceSAdrien Destuguesand `Physical Layer Spec Version 17*a5061eceSAdrien Destugues1.10 <https://www.sdcard.org/downloads/pls/pdf/index.php?p=Part1_Physical_Layer_Simplified_Specification_Ver1.10.jpg&f=Part1_Physical_Layer_Simplified_Specification_Ver1.10.pdf&e=EN_P1110>`__. 18*a5061eceSAdrien Destugues 19*a5061eceSAdrien DestuguesLoading and testing the driver 20*a5061eceSAdrien Destugues------------------------------ 21*a5061eceSAdrien Destugues 22*a5061eceSAdrien DestuguesEmulating the hardware 23*a5061eceSAdrien Destugues~~~~~~~~~~~~~~~~~~~~~~ 24*a5061eceSAdrien Destugues 25*a5061eceSAdrien DestuguesWe will emulate a SDHC device using qemu as all system may not have the 26*a5061eceSAdrien Destuguesdevice. These days systems provide transfer to SD/ MMC card over USB. 27*a5061eceSAdrien DestuguesThe document will not instruct you on how to build haiku but you can 28*a5061eceSAdrien Destuguesrefer the link to `compile and build the haiku 29*a5061eceSAdrien Destuguesimages <https://www.haiku-os.org/guides/building/>`__ or the `week #1 30*a5061eceSAdrien Destuguesand 31*a5061eceSAdrien Destugues#2 <https://www.haiku-os.org/blog/krish_iyer/2018-05-06_gsoc_2018_sdhci_mmc_driver_week_1_and_2/>`__ 32*a5061eceSAdrien Destuguesproject report will also work. 33*a5061eceSAdrien Destugues 34*a5061eceSAdrien DestuguesAfter building the image, we will emulate the hardware and host haiku on 35*a5061eceSAdrien Destuguestop of that. 36*a5061eceSAdrien Destugues 37*a5061eceSAdrien DestuguesEmulation 38*a5061eceSAdrien Destugues^^^^^^^^^ 39*a5061eceSAdrien Destugues 40*a5061eceSAdrien DestuguesFor emulating a sdhci-pci device 41*a5061eceSAdrien Destugues 42*a5061eceSAdrien Destugues:: 43*a5061eceSAdrien Destugues 44*a5061eceSAdrien Destugues qemu-img create sd-card.img 32M 45*a5061eceSAdrien Destugues qemu-system-x86_64 -drive index=0,file=haiku-nightly-anyboot.iso,format=raw \ 46*a5061eceSAdrien Destugues -device sdhci-pci -device sd-card,drive=mydrive \ 47*a5061eceSAdrien Destugues -drive if=sd,index=1,file=sd-card.img,format=raw,id=mydrive 48*a5061eceSAdrien Destugues -m 512M -enable-kvm -usbdevice tablet -machine q35 49*a5061eceSAdrien Destugues 50*a5061eceSAdrien DestuguesThis does the following: - Create an SD card image of 32MB - Run qemu 51*a5061eceSAdrien Destugueswith a bootable image in an IDE disk, and an SDHCI bus with an SD card 52*a5061eceSAdrien Destuguesin it - Have enough memory to boot Haiku, use KVM mode for speed, and a 53*a5061eceSAdrien Destuguestablet for ease of use - Use the Q35 chipset so the mouse and SDHCI 54*a5061eceSAdrien Destuguescontrollers don’t share an interrupt (not strictly required, but it 55*a5061eceSAdrien Destuguesavoids calls to the SDHCI interrupt handler on every mouse move). 56*a5061eceSAdrien Destugues 57*a5061eceSAdrien DestuguesTracing of SD operations can also be added to see how qemu is 58*a5061eceSAdrien Destuguesinterpreting our commands: 59*a5061eceSAdrien Destugues 60*a5061eceSAdrien Destugues:: 61*a5061eceSAdrien Destugues 62*a5061eceSAdrien Destugues -trace sdhci* -trace sdbus* -trace sdcard* 63*a5061eceSAdrien Destugues 64*a5061eceSAdrien DestuguesTesting and loading the driver 65*a5061eceSAdrien Destugues~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 66*a5061eceSAdrien Destugues 67*a5061eceSAdrien DestuguesThe code is merged and part of the default Haiku build. 68*a5061eceSAdrien Destugues 69*a5061eceSAdrien DestuguesInsight into the code and future tasks 70*a5061eceSAdrien Destugues-------------------------------------- 71*a5061eceSAdrien Destugues 72*a5061eceSAdrien DestuguesBus, bus manager, and drivers 73*a5061eceSAdrien Destugues~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 74*a5061eceSAdrien Destugues 75*a5061eceSAdrien DestuguesThe MMC stack is a device manager based “new style” driver. This 76*a5061eceSAdrien Destuguesrequires splitting the driver in different parts but allow easy reuse of 77*a5061eceSAdrien Destugueseach part (for example to support eMMC or SDIO with a large part of the 78*a5061eceSAdrien Destuguescode in common with plain SD/MMC). 79*a5061eceSAdrien Destugues 80*a5061eceSAdrien DestuguesMMC Bus drivers (src/add-ons/kernel/busses/mmc) 81*a5061eceSAdrien Destugues^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 82*a5061eceSAdrien Destugues 83*a5061eceSAdrien DestuguesThe bus driver provides the low level aspects: interrupts management, 84*a5061eceSAdrien DestuguesDMA transfer, accessing the hardware registers. It acts as a platform 85*a5061eceSAdrien Destuguesabstraction layer so that the bus manager and disk driver can be written 86*a5061eceSAdrien Destuguesindependently of the underlying hardare. 87*a5061eceSAdrien Destugues 88*a5061eceSAdrien DestuguesCurrently there is a single implementation for SDHCI (MMC bus over PCI). 89*a5061eceSAdrien DestuguesLater on, other drivers will be added for other ways to access the MMC 90*a5061eceSAdrien Destuguesbus (for example on ARM devices where it does not live on a PCI bus, and 91*a5061eceSAdrien Destuguesmay have a different register layout). 92*a5061eceSAdrien Destugues 93*a5061eceSAdrien DestuguesFor this reason, the bus drivers should only do the most low-level 94*a5061eceSAdrien Destuguesthings, trying to keep as much code as possible in the upper layers. 95*a5061eceSAdrien Destugues 96*a5061eceSAdrien DestuguesOne slightly confusing thing about SDHCI is that it allows a single PCI 97*a5061eceSAdrien Destuguesdevice to implement multiple separate MMC busses (each of which could 98*a5061eceSAdrien Destugueshave multiple devices attached). For this reason there is an SDHCI 99*a5061eceSAdrien Destugues“device” that attaches to the PCI device node for the controller, and 100*a5061eceSAdrien Destuguesthen publishes multiple device nodes for each available bus. The nodes 101*a5061eceSAdrien Destuguesthen work independently of each other. 102*a5061eceSAdrien Destugues 103*a5061eceSAdrien DestuguesThe Bus Manager (src/add-ons/kernel/bus_managers/mmc) 104*a5061eceSAdrien Destugues^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 105*a5061eceSAdrien Destugues 106*a5061eceSAdrien DestuguesThe bus manager is responsible for enumerating devices on the bus, 107*a5061eceSAdrien Destuguesassigning them addresses, and keeping track of which card is active at 108*a5061eceSAdrien Destuguesany given time. 109*a5061eceSAdrien Destugues 110*a5061eceSAdrien DestuguesEssentially it has everything that requires collaboration between 111*a5061eceSAdrien Destuguesmultiple MMC devices, as well as things that are not specific to a 112*a5061eceSAdrien Destuguesdevice type (common to SDIO, SD and MMC cards, for example) 113*a5061eceSAdrien Destugues 114*a5061eceSAdrien DestuguesDisk Driver (src/add-ons/kernel/drivers/disk/mmc) 115*a5061eceSAdrien Destugues^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 116*a5061eceSAdrien Destugues 117*a5061eceSAdrien DestuguesThis is a mass storage driver for MMC, SD and SDHC cards. Currently only 118*a5061eceSAdrien DestuguesSD and SDHC are tested, MMC and eMMC will have to be added (they are 119*a5061eceSAdrien Destuguessimilar but there are some differences). 120*a5061eceSAdrien Destugues 121*a5061eceSAdrien DestuguesWiring the driver in the device manager (src/system/kernel/device_manager/device_manager.cpp) 122*a5061eceSAdrien Destugues^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 123*a5061eceSAdrien Destugues 124*a5061eceSAdrien Destugues(note: possibly not accurate documentation, I did not check how things 125*a5061eceSAdrien Destuguesin the device manager are actually implemented, but this is my 126*a5061eceSAdrien Destuguesunderstanding of it). 127*a5061eceSAdrien Destugues 128*a5061eceSAdrien DestuguesThe device manager attempts to implement lazy, on-demand scanning of the 129*a5061eceSAdrien Destuguesdevices. The idea is to speed up booting by not spending a lot of time 130*a5061eceSAdrien Destuguesscanning everything first, and only scanning small parts of the device 131*a5061eceSAdrien Destuguestree as they are needed. 132*a5061eceSAdrien Destugues 133*a5061eceSAdrien DestuguesThe trigger is accesses to the devfs. For example, when an application 134*a5061eceSAdrien Destuguesopens /dev/disk, the device manager will start looking for disks so it 135*a5061eceSAdrien Destuguescan populate it. This means the device manager needs to know which 136*a5061eceSAdrien Destuguesbranches of the device tree to explore. Currently this knowledge is 137*a5061eceSAdrien Destugueshardcoded into the device tree sourcecode, and there’s a TODO item about 138*a5061eceSAdrien Destuguesmoving that knowledge to drivers instead. But it’s tricky, since the 139*a5061eceSAdrien Destugueswhole point is to avoid loading all the drivers. 140*a5061eceSAdrien Destugues 141*a5061eceSAdrien DestuguesAnyway, currently, the device manager is hardcoded to look for mass 142*a5061eceSAdrien Destuguesstorage devices under SDHCI busses, both standard ones and some 143*a5061eceSAdrien Destuguesnon-standard ones (for example, Ricoh provides SDHCI implenentations 144*a5061eceSAdrien Destuguesthat are conform to the spec, except they don’t have the right device 145*a5061eceSAdrien Destuguestype in the PCI registers). 146*a5061eceSAdrien Destugues 147*a5061eceSAdrien DestuguesInsight into the code 148*a5061eceSAdrien Destugues~~~~~~~~~~~~~~~~~~~~~ 149*a5061eceSAdrien Destugues 150*a5061eceSAdrien DestuguesMMC Bus management overview 151*a5061eceSAdrien Destugues^^^^^^^^^^^^^^^^^^^^^^^^^^^ 152*a5061eceSAdrien Destugues 153*a5061eceSAdrien DestuguesThe device tree for MMC support looks like this: 154*a5061eceSAdrien Destugues 155*a5061eceSAdrien Destugues- PCI bus manager 156*a5061eceSAdrien Destugues 157*a5061eceSAdrien Destugues - (other PCI devices) 158*a5061eceSAdrien Destugues - SDHCI controller 159*a5061eceSAdrien Destugues 160*a5061eceSAdrien Destugues - SDHCI bus 161*a5061eceSAdrien Destugues 162*a5061eceSAdrien Destugues - MMC bus manager 163*a5061eceSAdrien Destugues 164*a5061eceSAdrien Destugues - MMC device 165*a5061eceSAdrien Destugues 166*a5061eceSAdrien Destugues - mmc_disk device 167*a5061eceSAdrien Destugues 168*a5061eceSAdrien Destugues - MMC device 169*a5061eceSAdrien Destugues 170*a5061eceSAdrien Destugues - (other SDIO driver) 171*a5061eceSAdrien Destugues 172*a5061eceSAdrien Destugues - MMC bus manager (second MMC bus) 173*a5061eceSAdrien Destugues 174*a5061eceSAdrien Destugues - MMC device 175*a5061eceSAdrien Destugues 176*a5061eceSAdrien Destugues - mmc_disk device 177*a5061eceSAdrien Destugues 178*a5061eceSAdrien DestuguesAt the first level, the PCI bus manager publishes a device node for each 179*a5061eceSAdrien Destuguesdevice found. One of them is our SDHCI controller, identified either by 180*a5061eceSAdrien Destuguesthe PCI device class and subclass, or for not completely SDHCI 181*a5061eceSAdrien Destuguescompatible device, by the device and vendor IDs. 182*a5061eceSAdrien Destugues 183*a5061eceSAdrien DestuguesThe SDHCI bus driver attaches to this device and publishes his own node. 184*a5061eceSAdrien DestuguesIt then scans the device and publishes an MMC bus node for each slot 185*a5061eceSAdrien Destugues(there may be multiple SD slots attached to a single PCI controller). 186*a5061eceSAdrien Destugues 187*a5061eceSAdrien DestuguesThe MMC bus manager then attach to each of these slots, and send the 188*a5061eceSAdrien Destuguesappropriate commands for enumerating the SD cards (there may be multiple 189*a5061eceSAdrien Destuguescards in a “slot”), and publishes a device node for each of them. 190*a5061eceSAdrien DestuguesFinally, the mmc_disk driver can bind itself to one of these device 191*a5061eceSAdrien Destuguesnodes, and publish the corresponding disk node, which is also be made 192*a5061eceSAdrien Destuguesavailable in /dev/disk/mmc. 193*a5061eceSAdrien Destugues 194*a5061eceSAdrien DestuguesCurrently the mmc bus does not publish anything in the devfs, but this 195*a5061eceSAdrien Destuguescould be added if sending raw SD/MMC commands to SD cards from userland 196*a5061eceSAdrien Destuguesis considered desirable. 197*a5061eceSAdrien Destugues 198*a5061eceSAdrien DestuguesSDHCI driver 199*a5061eceSAdrien Destugues^^^^^^^^^^^^ 200*a5061eceSAdrien Destugues 201*a5061eceSAdrien DestuguesThe SDHCI driver is the lowest level of the MMC stack. It provides 202*a5061eceSAdrien Destuguesabstraction of the SDHCI device. Later on, different way to access an SD 203*a5061eceSAdrien Destuguesbus may be added, for example for ARM devices which decided to use a 204*a5061eceSAdrien Destuguesdifferent register interface. 205*a5061eceSAdrien Destugues 206*a5061eceSAdrien DestuguesThe entry point is as usual **supports_device()**. This method is called 207*a5061eceSAdrien Destuguesonly for devices which may be SDHCI controllers, thanks to filtering 208*a5061eceSAdrien Destuguesdone in the device manager to probe only the relevant devices. The 209*a5061eceSAdrien Destuguesprobing is done on-demand, currently when the system is enumerating 210*a5061eceSAdrien Destugues/dev/disk in the devfs. Later on, when we have SDIO support, probing 211*a5061eceSAdrien Destugueswill also be triggered in other cases. 212*a5061eceSAdrien Destugues 213*a5061eceSAdrien DestuguesThe function identifies the device by checking the class and subclass, 214*a5061eceSAdrien Destuguesas well as a limited set of hardcoded PCI device and vendor IDs for 215*a5061eceSAdrien Destuguesdevices that do not use the assigned subclass. 216*a5061eceSAdrien Destugues 217*a5061eceSAdrien DestuguesOnce a compatible device is found, **register_child_devices()** is used 218*a5061eceSAdrien Destuguesto publish device nodes for each slot to be controlled by the mmc bus 219*a5061eceSAdrien Destuguesmanager. The registers for each device are mapped into virtual memory, 220*a5061eceSAdrien Destuguesusing the information from the PCI bar registers. **struct registers** 221*a5061eceSAdrien Destuguesis defined so that it matches the register layout, and provide a little 222*a5061eceSAdrien Destuguesabstraction to raw register access. 223*a5061eceSAdrien Destugues 224*a5061eceSAdrien DestuguesAn SdhciBus object is created to manage each of these busses at the 225*a5061eceSAdrien DestuguesSDHCI level. It will be responsible for executing SD commands on that 226*a5061eceSAdrien Destuguesbus, and dealing with the resulting interrupts. 227*a5061eceSAdrien Destugues 228*a5061eceSAdrien DestuguesThe Bus Manager 229*a5061eceSAdrien Destugues^^^^^^^^^^^^^^^ 230*a5061eceSAdrien Destugues 231*a5061eceSAdrien DestuguesThe MMC bus manager manages the MMC bus (duh). Its tasks are: 232*a5061eceSAdrien Destugues 233*a5061eceSAdrien Destugues- enumerating SD cards on the bus 234*a5061eceSAdrien Destugues- assigning RCAs to the cards for identifying them when sending 235*a5061eceSAdrien Destugues commands 236*a5061eceSAdrien Destugues- setting the bus clock speed according to what the cards can handle 237*a5061eceSAdrien Destugues- remember which SD card is currently active (CMD7) 238*a5061eceSAdrien Destugues- manage cards state 239*a5061eceSAdrien Destugues- publish device nodes for each card 240*a5061eceSAdrien Destugues 241*a5061eceSAdrien DestuguesDisk Driver 242*a5061eceSAdrien Destugues^^^^^^^^^^^ 243*a5061eceSAdrien Destugues 244*a5061eceSAdrien DestuguesThe disk driver is attached to devices implementing SDSC or SDHC/SDXC 245*a5061eceSAdrien Destuguescommands. There will be other drivers for non-storage (SDIO) cards. 246*a5061eceSAdrien Destugues 247*a5061eceSAdrien DestuguesTo help with this, the MMC bus manager provides the device with the 248*a5061eceSAdrien Destuguesinformation it gathered while initializing the device. According to the 249*a5061eceSAdrien Destuguescommands recognized by the card during the initialization sequence, it’s 250*a5061eceSAdrien Destuguespossible to know if it’s SDSC, SDHC/SDXC, or something else (SDIO, 251*a5061eceSAdrien Destugueslegacy MMC, etc). 252*a5061eceSAdrien Destugues 253*a5061eceSAdrien DestuguesThe disk driver publishes devfs entries in /dev/disk/mmc and implements 254*a5061eceSAdrien Destuguesthe usual interface for disk devices. From this point on, the device can 255*a5061eceSAdrien Destuguesbe used just like any other mass storage device. 256*a5061eceSAdrien Destugues 257*a5061eceSAdrien DestuguesGetting everything loaded 258*a5061eceSAdrien Destugues^^^^^^^^^^^^^^^^^^^^^^^^^ 259*a5061eceSAdrien Destugues 260*a5061eceSAdrien DestuguesThe device manager is not completely implemented yet. As a result, some 261*a5061eceSAdrien Destuguesdecisions about which drivers to load are hardcoded in 262*a5061eceSAdrien Destuguesdevice_manager.cpp. 263*a5061eceSAdrien Destugues 264*a5061eceSAdrien DestuguesIt has been adjusted to handover SDHCI devices to the MMC bus. Whenever 265*a5061eceSAdrien Destuguesa “disk” device is requested, the MMC busses are searched, which results 266*a5061eceSAdrien Destuguesin loading the SDHCI driver and probing for SD cards. When we get 267*a5061eceSAdrien Destuguessupport for other types of SDIO devices, we will need to adjust the 268*a5061eceSAdrien Destuguesdevice manager to probe the SDHCI bus when these type of devices are 269*a5061eceSAdrien Destuguesrequested, too. 270*a5061eceSAdrien Destugues 271*a5061eceSAdrien DestuguesTasks to be completed 272*a5061eceSAdrien Destugues~~~~~~~~~~~~~~~~~~~~~ 273*a5061eceSAdrien Destugues 274*a5061eceSAdrien DestuguesThe SDHCI driver is able to send and receive commands. However it does 275*a5061eceSAdrien Destuguesnot handle card insertion and removal interrupts yet, so the card must 276*a5061eceSAdrien Destuguesbe already inserted when the driver is loaded. 277*a5061eceSAdrien Destugues 278*a5061eceSAdrien DestuguesThe mmc_disk driver is complete and working, but was not tested for MMC 279*a5061eceSAdrien Destuguesand eMMC devices. Some changes may be needed. 280*a5061eceSAdrien Destugues 281*a5061eceSAdrien DestuguesThere is also work to be done for better performance: making sure we 282*a5061eceSAdrien Destuguesswitch to the high-speed clock when an SD card supports it, and use the 283*a5061eceSAdrien Destugues4-bit data transfer mode instead of the default 1-bit if possible. 284*a5061eceSAdrien Destugues 285*a5061eceSAdrien DestuguesDrivers for SDIO devices should also be added. The mmc_bus and SDHCI 286*a5061eceSAdrien Destuguesdrivers have been tested only with one card on the bus at a time (for 287*a5061eceSAdrien Destugueslack of hardware allowing more complex setups). 288*a5061eceSAdrien Destugues 289*a5061eceSAdrien DestuguesIf you find it difficult to understand the driver development and it’s 290*a5061eceSAdrien Destuguesfunctioning and role, please refer 291*a5061eceSAdrien Destugues*docs/develop/kernel/device_manager_introduction.html* 292