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Searched refs:NV_REG32 (Results 1 – 13 of 13) sorted by relevance

/haiku/src/add-ons/accelerants/nvidia/engine/
H A Dnv_i2c.c37 NV_REG32(NV32_FUNCSEL) &= ~0x00000010; in i2c_select_bus_set()
38 NV_REG32(NV32_2FUNCSEL) |= 0x00000010; in i2c_select_bus_set()
41 NV_REG32(NV32_2FUNCSEL) &= ~0x00000010; in i2c_select_bus_set()
42 NV_REG32(NV32_FUNCSEL) |= 0x00000010; in i2c_select_bus_set()
55 data32 = NV_REG32(NV32_NV4E_I2CBUS_0) & ~0x2f; in OutSCL()
57 NV_REG32(NV32_NV4E_I2CBUS_0) = data32 | 0x21; in OutSCL()
59 NV_REG32(NV32_NV4E_I2CBUS_0) = data32 | 0x01; in OutSCL()
62 data32 = NV_REG32(NV32_NV4E_I2CBUS_1) & ~0x2f; in OutSCL()
64 NV_REG32(NV32_NV4E_I2CBUS_1) = data32 | 0x21; in OutSCL()
66 NV_REG32(NV32_NV4E_I2CBUS_1) = data32 | 0x01; in OutSCL()
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H A Dnv_info.c326 fb_mrs2 = NV_REG32(NV32_FB_MRS2); in coldstart_card_516_up()
327 fb_mrs1 = NV_REG32(NV32_FB_MRS1); in coldstart_card_516_up()
396 NV_REG32(NV32_FB_MRS2) = fb_mrs2; in coldstart_card_516_up()
397 NV_REG32(NV32_FB_MRS1) = fb_mrs1; in coldstart_card_516_up()
463 NV_REG32(reg) = ((p << 16) | (n << 8) | m); in exec_type1_script()
485 if (exec) NV_REG32(reg) = data2; in exec_type1_script()
524 NV_REG32(reg) = data; in exec_type1_script()
525 NV_REG32(reg) = data2; in exec_type1_script()
569 data = NV_REG32(NV32_NV4STRAPINFO); in exec_type1_script()
609 data = NV_REG32(reg); in exec_type1_script()
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H A Dnv_acc_dma.c48 while ((NV_REG32(NVACC_FIFO + NV_GENERAL_DMAGET) != (si->engine.dma.put << 2)) && in nv_acc_wait_idle_dma()
83 NV_REG32(NV32_PWRUPCTRL) = 0xffff00ff; in nv_acc_init_dma()
85 NV_REG32(NV32_PWRUPCTRL) = 0xffffffff; in nv_acc_init_dma()
104 NV_REG32(cnt) = 0x00000000; in nv_acc_init_dma()
134 NV_REG32(NV32_PFB_CONFIG_0) = 0x00001114; in nv_acc_init_dma()
211 NV_REG32(NVACC_HT_HANDL_00 + (cnt << 2)) = 0; in nv_acc_init_dma()
647 NV_REG32(NVACC_NV10_TIL0AD + (cnt << 2)) = in nv_acc_init_dma()
648 NV_REG32(NVACC_NV10_FBTIL0AD + (cnt << 2)); in nv_acc_init_dma()
679 tmp = (NV_REG32(NV32_NV4X_WHAT0) & 0x000000ff); in nv_acc_init_dma()
714 NV_REG32(NV32_NV44_WHAT10) = NV_REG32(NV32_NV10STRAPINFO); in nv_acc_init_dma()
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H A Dnv_agp.c32 LOG(4, ("AGP: STRAPINFO2 contains $%08x\n", NV_REG32(NV32_NVSTRAPINFO2))); in nv_agp_setup()
36 reg = (NV_REG32(NV32_NVSTRAPINFO2) & ~0x00000800); in nv_agp_setup()
38 NV_REG32(NV32_NVSTRAPINFO2) = (reg | 0x80000000); in nv_agp_setup()
40 LOG(4, ("AGP: STRAPINFO2 now contains $%08x\n", NV_REG32(NV32_NVSTRAPINFO2))); in nv_agp_setup()
H A Dnv_acc.c88 NV_REG32(NV32_PWRUPCTRL) = 0xffff00ff; in nv_acc_init()
90 NV_REG32(NV32_PWRUPCTRL) = 0xffffffff; in nv_acc_init()
108 NV_REG32(NV32_PFB_CONFIG_0) = 0x00001114; in nv_acc_init()
196 NV_REG32(NVACC_HT_HANDL_00 + (cnt << 2)) = 0; in nv_acc_init()
472 NV_REG32(NV32_NV44_WHAT10) = NV_REG32(NV32_NV10STRAPINFO); in nv_acc_init()
473 NV_REG32(NV32_NV44_WHAT11) = 0x00000000; in nv_acc_init()
474 NV_REG32(NV32_NV44_WHAT12) = 0x00000000; in nv_acc_init()
475 NV_REG32(NV32_NV44_WHAT13) = NV_REG32(NV32_NV10STRAPINFO); in nv_acc_init()
864 ACCW(NV40P_WHAT_T0, NV_REG32(NV32_PFB_CONFIG_0)); in nv_acc_init()
865 ACCW(NV40P_WHAT_T1, NV_REG32(NV32_PFB_CONFIG_1)); in nv_acc_init()
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H A Dnv_crtc.c657 NV_REG32(NV32_LVDS_PWR) = 0x00000003; in nv_crtc_dpms()
700 NV_REG32(NV32_LVDS_PWR) = 0x00000007; in nv_crtc_dpms()
770 while (((NV_REG32(NV32_RASTER) & 0x000007ff) < si->dm.timing.v_display) && in nv_crtc_set_display_start()
806 NV_REG32(NV32_NV10FBSTADD32) = (startadd & 0xfffffffc); in nv_crtc_set_display_start()
846 NV_REG32(NV32_NV10CURADD32) = (curadd & 0xfffff800); in nv_crtc_cursor_init()
859 NV_REG32(NV32_CURCONF) = 0x02000100; in nv_crtc_cursor_init()
988 while ((((uint16)(NV_REG32(NV32_RASTER) & 0x000007ff)) < (yhigh + 16)) && in nv_crtc_cursor_position()
1000 while (((NV_REG32(NV32_RASTER) & 0x000007ff) < si->dm.timing.v_display) && in nv_crtc_cursor_position()
1098 NV_REG32(NV32_2FUNCSEL) &= ~0x00000100; in nv_crtc_start_tvout()
1099 NV_REG32(NV32_FUNCSEL) |= 0x00000100; in nv_crtc_start_tvout()
H A Dnv_crtc2.c639 NV_REG32(NV32_LVDS_PWR) = 0x00000003; in nv_crtc2_dpms()
681 NV_REG32(NV32_LVDS_PWR) = 0x00000007; in nv_crtc2_dpms()
750 while (((NV_REG32(NV32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) && in nv_crtc2_set_display_start()
767 NV_REG32(NV32_NV10FB2STADD32) = (startadd & 0xfffffffc); in nv_crtc2_set_display_start()
806 NV_REG32(NV32_NV10CUR2ADD32) = (curadd & 0xfffff800); in nv_crtc2_cursor_init()
819 NV_REG32(NV32_2CURCONF) = 0x02000100; in nv_crtc2_cursor_init()
1008 NV_REG32(NV32_FUNCSEL) &= ~0x00000100; in nv_crtc2_start_tvout()
1009 NV_REG32(NV32_2FUNCSEL) |= 0x00000100; in nv_crtc2_start_tvout()
H A Dnv_bes.c360 NV_REG32(NV32_FUNCSEL) &= ~0x00001000; in nv_bes_to_crtc()
361 NV_REG32(NV32_2FUNCSEL) |= 0x00001000; in nv_bes_to_crtc()
368 NV_REG32(NV32_2FUNCSEL) &= ~0x00001000; in nv_bes_to_crtc()
369 NV_REG32(NV32_FUNCSEL) |= 0x00001000; in nv_bes_to_crtc()
H A Dnv_general.c1730 NV_REG32(NV32_PWRUPCTRL) = 0xffffffff; in unlock_card()
1755 NV_REG32(NV32_PWRUPCTRL) = 0xffff00ff; in nv_general_bios_to_powergraphics()
1757 NV_REG32(NV32_PWRUPCTRL) = 0xffffffff; in nv_general_bios_to_powergraphics()
1779 NV_REG32(NV32_2FUNCSEL) &= ~0x00001100; in nv_general_bios_to_powergraphics()
1780 NV_REG32(NV32_FUNCSEL) |= 0x00001100; in nv_general_bios_to_powergraphics()
1883 NV_REG32(NV32_PFB_CLS_PAGE2) &= 0xffff7fff; in nv_general_bios_to_powergraphics()
H A Dnv_dac2.c187 LOG(4,("DAC2: current (0x0000c040) settings: $%08x\n", NV_REG32(0x0000c040))); in nv_dac2_set_pix_pll()
H A Dnv_dac.c222 LOG(4,("DAC: current (0x0000c040) settings: $%08x\n", NV_REG32(0x0000c040))); in nv_dac_set_pix_pll()
/haiku/src/add-ons/kernel/drivers/graphics/nvidia/
H A Ddriver.c427 return (NV_REG32(NV32_CRTC_INTS) & 0x00000001); in caused_vbi_crtc1()
435 NV_REG32(NV32_CRTC_INTS) = 0x00000001; in clear_vbi_crtc1()
443 NV_REG32(NV32_CRTC_INTS) = 0x00000001; in enable_vbi_crtc1()
445 NV_REG32(NV32_CRTC_INTE) |= 0x00000001; in enable_vbi_crtc1()
447 NV_REG32(NV32_MAIN_INTE) = 0x00000001; in enable_vbi_crtc1()
455 NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe; in disable_vbi_crtc1()
457 NV_REG32(NV32_CRTC_INTS) = 0x00000001; in disable_vbi_crtc1()
465 return (NV_REG32(NV32_CRTC2_INTS) & 0x00000001); in caused_vbi_crtc2()
473 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; in clear_vbi_crtc2()
481 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; in enable_vbi_crtc2()
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/haiku/headers/private/graphics/nvidia/
H A Dnv_macros.h890 #define NV_REG32(r_) ((vuint32 *)regs)[(r_) >> 2] macro
903 #define DACR(A) (NV_REG32(NVDAC_##A))
904 #define DACW(A,B) (NV_REG32(NVDAC_##A)=B)
907 #define DAC2R(A) (NV_REG32(NVDAC2_##A))
908 #define DAC2W(A,B) (NV_REG32(NVDAC2_##A)=B)
911 #define BESR(A) (NV_REG32(NVBES_##A))
912 #define BESW(A,B) (NV_REG32(NVBES_##A)=B)
939 #define ACCR(A) (NV_REG32(NVACC_##A))
940 #define ACCW(A,B) (NV_REG32(NVACC_##A)=B)