Home
last modified time | relevance | path

Searched refs:AR_PHY_GC_DYN2040_PRI_CH (Results 1 – 2 of 2) sorted by relevance

/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/contrib/ath_hal/ar9300/
H A Dar9300_reset.c886 phymode |= AR_PHY_GC_DYN2040_PRI_CH; in ar9300_set_11n_regs()
961 if (OS_REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, AR_PHY_GC_DYN2040_PRI_CH) in ar9300_spur_mitigate_mrc_cck()
1063 if (OS_REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, AR_PHY_GC_DYN2040_PRI_CH) in ar9300_spur_mitigate_ofdm()
1119 ah, AR_PHY_GEN_CTRL, AR_PHY_GC_DYN2040_PRI_CH) == 0x0) in ar9300_spur_mitigate_ofdm()
1128 AR_PHY_GEN_CTRL, AR_PHY_GC_DYN2040_PRI_CH) == 0x0) in ar9300_spur_mitigate_ofdm()
H A Dar9300phy.h986 #define AR_PHY_GC_DYN2040_PRI_CH 0x00000010 /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-10MHz… macro