Home
last modified time | relevance | path

Searched refs:x86_write_msr (Results 1 – 16 of 16) sorted by relevance

/haiku/src/system/kernel/arch/x86/64/
H A Dsyscalls.cpp54 x86_write_msr(IA32_MSR_EFER, x86_read_msr(IA32_MSR_EFER) in init_syscall_registers()
59 x86_write_msr(IA32_MSR_FMASK, X86_EFLAGS_INTERRUPT | X86_EFLAGS_DIRECTION in init_syscall_registers()
64 x86_write_msr(IA32_MSR_LSTAR, (addr_t)x86_64_syscall_entry); in init_syscall_registers()
68 x86_write_msr(IA32_MSR_CSTAR, (addr_t)x86_64_syscall32_entry); in init_syscall_registers()
83 x86_write_msr(IA32_MSR_STAR, ((uint64)(USER32_CODE_SELECTOR) << 48) in init_syscall_registers()
105 x86_write_msr(IA32_MSR_SYSENTER_ESP, stackTop); in set_intel_syscall_stack()
112 x86_write_msr(IA32_MSR_SYSENTER_CS, KERNEL_CODE_SELECTOR); in init_intel_syscall_registers()
113 x86_write_msr(IA32_MSR_SYSENTER_ESP, 0); in init_intel_syscall_registers()
114 x86_write_msr(IA32_MSR_SYSENTER_EIP, (addr_t)x86_64_sysenter32_entry); in init_intel_syscall_registers()
H A Derrata.cpp59 x86_write_msr(0xc0011029, x86_read_msr(0xc0011029) | 1); in patch_errata_percpu_amd()
72 x86_write_msr(0xc0011020, x86_read_msr(0xc0011020) | ((uint64)1 << 15)); in patch_errata_percpu_amd()
83 x86_write_msr(0xc0011029, x86_read_msr(0xc0011029) | (1 << 13)); in patch_errata_percpu_amd()
89 x86_write_msr(0xc0011020, x86_read_msr(0xc0011020) | (1 << 4)); in patch_errata_percpu_amd()
99 x86_write_msr(0xc0011028, x86_read_msr(0xc0011028) | (1 << 4)); in patch_errata_percpu_amd()
114 x86_write_msr(0xc0011020, x86_read_msr(0xc0011020) | ((uint64)1 << 57)); in patch_errata_percpu_amd()
121 x86_write_msr(MSR_F10H_DE_CFG, x86_read_msr(MSR_F10H_DE_CFG) | (1 << 9)); in patch_errata_percpu_amd()
H A Dthread.cpp102 x86_write_msr(IA32_MSR_FS_BASE, thread->user_local_storage); in x86_set_tls_context()
103 x86_write_msr(IA32_MSR_KERNEL_GS_BASE, thread->arch_info.user_gs_base); in x86_set_tls_context()
161 x86_write_msr(IA32_MSR_KERNEL_GS_BASE, base); in arch_thread_control()
/haiku/src/system/kernel/arch/x86/
H A Dapic.cpp90 x86_write_msr(IA32_MSR_APIC_TASK_PRIORITY, config); in apic_set_task_priority()
100 x86_write_msr(IA32_MSR_APIC_EOI, 0); in apic_end_of_interrupt()
121 x86_write_msr(IA32_MSR_APIC_LVT_LINT0, APIC_LVT_MASKED); in apic_disable_local_ints()
122 x86_write_msr(IA32_MSR_APIC_LVT_LINT1, APIC_LVT_MASKED); in apic_disable_local_ints()
144 x86_write_msr(IA32_MSR_APIC_SPURIOUS_INTR_VECTOR, config); in apic_set_spurious_intr_vector()
157 x86_write_msr(IA32_MSR_APIC_INTR_COMMAND, command); in apic_set_interrupt_command()
193 x86_write_msr(IA32_MSR_APIC_LVT_TIMER, config); in apic_set_lvt_timer()
213 x86_write_msr(IA32_MSR_APIC_LVT_ERROR, config); in apic_set_lvt_error()
233 x86_write_msr(IA32_MSR_APIC_INITIAL_TIMER_COUNT, config); in apic_set_lvt_initial_timer_count()
253 x86_write_msr(IA32_MSR_APIC_TIMER_DIVIDE_CONFIG, config); in apic_set_lvt_timer_divide_config()
[all …]
H A Darch_cpu.cpp338 x86_write_msr(IA32_MSR_PAT, value); in init_pat()
1021 x86_write_msr(IA32_MSR_UCODE_REV, 0); in detect_intel_patch_level()
1143 x86_write_msr(IA32_MSR_UCODE_WRITE, data); in load_microcode_intel()
1262 x86_write_msr(MSR_K8_UCODE_UPDATE, data); in load_microcode_amd()
1576 x86_write_msr(IA32_MSR_TSC, 0); in arch_cpu_preboot_init_percpu()
1597 x86_write_msr(K8_MSR_IPM, msr & ~K8_CMPHALT); in amdc1e_noarat_idle()
1783 x86_write_msr(IA32_MSR_TSC_AUX, cpu); in arch_cpu_init_percpu()
1792 x86_write_msr(MSR_F10H_DE_CFG, value | DE_CFG_SERIALIZE_LFENCE); in arch_cpu_init_percpu()
H A Darch_debug.cpp1224 x86_write_msr(IA32_MSR_GS_BASE, (addr_t)&unsetThread); in arch_debug_unset_current_thread()
/haiku/src/add-ons/kernel/cpu/x86/
H A Dgeneric_x86.cpp85 x86_write_msr(IA32_MSR_MTRR_PHYSICAL_MASK_0 + index, 0); in set_mtrr()
90 x86_write_msr(IA32_MSR_MTRR_PHYSICAL_BASE_0 + index, in set_mtrr()
92 x86_write_msr(IA32_MSR_MTRR_PHYSICAL_MASK_0 + index, in set_mtrr()
96 x86_write_msr(IA32_MSR_MTRR_PHYSICAL_BASE_0 + index, 0); in set_mtrr()
143 x86_write_msr(IA32_MSR_MTRR_DEFAULT_TYPE, in generic_init_mtrrs()
190 x86_write_msr(IA32_MSR_MTRR_DEFAULT_TYPE, defaultType); in generic_set_mtrrs()
202 x86_write_msr(IA32_MSR_MTRR_DEFAULT_TYPE, defaultType | IA32_MTRR_ENABLE); in generic_set_mtrrs()
/haiku/src/system/kernel/arch/x86/32/
H A Dsyscalls.cpp55 x86_write_msr(IA32_MSR_SYSENTER_ESP, stackTop); in set_intel_syscall_stack()
62 x86_write_msr(IA32_MSR_SYSENTER_CS, KERNEL_CODE_SELECTOR); in init_intel_syscall_registers()
63 x86_write_msr(IA32_MSR_SYSENTER_ESP, 0); in init_intel_syscall_registers()
64 x86_write_msr(IA32_MSR_SYSENTER_EIP, (addr_t)x86_sysenter); in init_intel_syscall_registers()
H A Darch.S88 FUNCTION(x86_write_msr):
94 FUNCTION_END(x86_write_msr)
/haiku/src/add-ons/kernel/power/cpufreq/intel_pstates/
H A Dintel_pstates.cpp106 x86_write_msr(IA32_MSR_PERF_CTL, pstate << 8); in set_pstate()
190 x86_write_msr(IA32_MSR_HWP_INTERRUPT, 0); in set_normal_pstate()
191 x86_write_msr(IA32_MSR_PM_ENABLE, 1); in set_normal_pstate()
215 x86_write_msr(IA32_MSR_ENERGY_PERF_BIAS, perfBias); in set_normal_pstate()
219 x86_write_msr(IA32_MSR_HWP_REQUEST, hwpRequest in set_normal_pstate()
221 x86_write_msr(IA32_MSR_HWP_REQUEST_PKG, hwpRequest); in set_normal_pstate()
223 x86_write_msr(IA32_MSR_HWP_REQUEST, hwpRequest); in set_normal_pstate()
/haiku/src/add-ons/kernel/power/cpufreq/amd_pstates/
H A Damd_pstates.cpp69 x86_write_msr(MSR_AMD_CPPC_ENABLE, 1); in set_normal_pstate()
81 x86_write_msr(MSR_AMD_CPPC_REQ, request & 0xffffffff); in set_normal_pstate()
/haiku/headers/private/kernel/arch/x86/64/
H A Dcpu.h26 x86_write_msr(uint32_t msr, uint64_t value) in x86_write_msr() function
/haiku/headers/private/kernel/arch/x86/
H A Darch_thread.h50 x86_write_msr(IA32_MSR_GS_BASE, (addr_t)&t->arch_info); in arch_thread_set_current_thread()
H A Darch_cpu.h700 void x86_write_msr(uint32 registerNumber, uint64 value);
/haiku/src/system/kernel/arch/x86/paging/64bit/
H A DX86PagingMethod64Bit.cpp435 x86_write_msr(IA32_MSR_EFER, x86_read_msr(IA32_MSR_EFER) in _EnableExecutionDisable()
/haiku/src/system/kernel/arch/x86/paging/pae/
H A DX86PagingMethodPAE.cpp183 x86_write_msr(IA32_MSR_EFER, x86_read_msr(IA32_MSR_EFER) in _EnableExecutionDisable()