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Searched refs:reg32 (Results 1 – 15 of 15) sorted by relevance

/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/contrib/ath_hal/ar9300/
H A Dar9300_radio.c85 u_int32_t freq, channel_sel, reg32; in ar9300_set_channel() local
213 reg32 = (b_mode << 29); in ar9300_set_channel()
214 OS_REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); in ar9300_set_channel()
221 reg32 = in ar9300_set_channel()
227 reg32 += CHANSEL_5G_DOT5MHZ; in ar9300_set_channel()
229 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); in ar9300_set_channel()
232 reg32 |= load_synth_channel << 31; in ar9300_set_channel()
233 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); in ar9300_set_channel()
/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/
H A Dar5212_rfgain.c94 uint32_t reg32 = 0, mask, arrayEntry, lastBit; in ar5212GetRfField() local
111 reg32 |= (((rfBuf[arrayEntry] & mask) >> (column * 8)) >> in ar5212GetRfField()
118 reg32 = ath_hal_reverseBits(reg32, numBits); in ar5212GetRfField()
119 return reg32; in ar5212GetRfField()
H A Dar5111.c59 extern void ar5212ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32,
81 uint32_t refClk, reg32, data2111; in ar5111SetChannel() local
172 reg32 = ath_hal_reverseBits(chan5111 - 24, 8) & 0xff; in ar5111SetChannel()
175 reg32 = ath_hal_reverseBits(((chan5111 - 24)/2), 8) & 0xff; in ar5111SetChannel()
179 reg32 = (reg32 << 2) | (refClk << 1) | (1 << 10) | 0x1; in ar5111SetChannel()
180 OS_REG_WRITE(ah, AR_PHY(0x27), ((data2111 & 0xff) << 8) | (reg32 & 0xff)); in ar5111SetChannel()
181 reg32 >>= 8; in ar5111SetChannel()
182 OS_REG_WRITE(ah, AR_PHY(0x34), (data2111 & 0xff00) | (reg32 & 0xff)); in ar5111SetChannel()
H A Dar2317.c64 extern void ar5212ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32,
88 uint32_t reg32 = 0; in ar2317SetChannel() local
124 reg32 = (channelSel << 4) | (aModeRefSel << 2) | (bModeSynth << 1) | in ar2317SetChannel()
126 OS_REG_WRITE(ah, AR_PHY(0x27), reg32 & 0xff); in ar2317SetChannel()
128 reg32 >>= 8; in ar2317SetChannel()
129 OS_REG_WRITE(ah, AR_PHY(0x36), reg32 & 0x7f); in ar2317SetChannel()
492 uint32_t reg32, regoffset; in ar2317SetPowerTable() local
567 reg32 = ((pdadcValues[4*i + 0] & 0xFF) << 0) | in ar2317SetPowerTable()
571 OS_REG_WRITE(ah, regoffset, reg32); in ar2317SetPowerTable()
H A Dar2425.c48 extern void ar5212ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32,
91 uint32_t reg32 = 0; in ar2425SetChannel() local
134 reg32 = (channelSel << 4) | (aModeRefSel << 2) | (bModeSynth << 1) | in ar2425SetChannel()
136 OS_REG_WRITE(ah, AR_PHY(0x27), reg32 & 0xff); in ar2425SetChannel()
138 reg32 >>= 8; in ar2425SetChannel()
139 OS_REG_WRITE(ah, AR_PHY(0x36), reg32 & 0x7f); in ar2425SetChannel()
508 uint32_t i, reg32, regoffset; in ar2425SetPowerTable() local
545 reg32 = ((pdadcValues[4*i + 0] & 0xFF) << 0) | in ar2425SetPowerTable()
549 OS_REG_WRITE(ah, regoffset, reg32); in ar2425SetPowerTable()
H A Dar2413.c60 extern void ar5212ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32,
84 uint32_t reg32 = 0; in ar2413SetChannel() local
139 reg32 = (channelSel << 4) | (aModeRefSel << 2) | (bModeSynth << 1) | in ar2413SetChannel()
141 OS_REG_WRITE(ah, AR_PHY(0x27), reg32 & 0xff); in ar2413SetChannel()
143 reg32 >>= 8; in ar2413SetChannel()
144 OS_REG_WRITE(ah, AR_PHY(0x36), reg32 & 0x7f); in ar2413SetChannel()
509 uint32_t reg32, regoffset; in ar2413SetPowerTable() local
584 reg32 = ((pdadcValues[4*i + 0] & 0xFF) << 0) | in ar2413SetPowerTable()
588 OS_REG_WRITE(ah, regoffset, reg32); in ar2413SetPowerTable()
H A Dar2316.c64 extern void ar5212ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32,
97 uint32_t reg32 = 0; in ar2316SetChannel() local
147 reg32 = (channelSel << 4) | (aModeRefSel << 2) | (bModeSynth << 1) | in ar2316SetChannel()
149 OS_REG_WRITE(ah, AR_PHY(0x27), reg32 & 0xff); in ar2316SetChannel()
151 reg32 >>= 8; in ar2316SetChannel()
152 OS_REG_WRITE(ah, AR_PHY(0x36), reg32 & 0x7f); in ar2316SetChannel()
514 uint32_t reg32, regoffset; in ar2316SetPowerTable() local
589 reg32 = ((pdadcValues[4*i + 0] & 0xFF) << 0) | in ar2316SetPowerTable()
593 OS_REG_WRITE(ah, regoffset, reg32); in ar2316SetPowerTable()
H A Dar5413.c60 extern void ar5212ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32,
84 uint32_t reg32 = 0; in ar5413SetChannel() local
139 reg32 = (channelSel << 4) | (aModeRefSel << 2) | (bModeSynth << 1) | in ar5413SetChannel()
141 OS_REG_WRITE(ah, AR_PHY(0x27), reg32 & 0xff); in ar5413SetChannel()
143 reg32 >>= 8; in ar5413SetChannel()
144 OS_REG_WRITE(ah, AR_PHY(0x36), reg32 & 0x7f); in ar5413SetChannel()
552 uint32_t reg32, regoffset; in ar5413SetPowerTable() local
627 reg32 = ((pdadcValues[4*i + 0] & 0xFF) << 0) | in ar5413SetPowerTable()
631 OS_REG_WRITE(ah, regoffset, reg32); in ar5413SetPowerTable()
H A Dar5112.c60 extern void ar5212ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32,
84 uint32_t reg32 = 0; in ar5112SetChannel() local
139 reg32 = (channelSel << 4) | (aModeRefSel << 2) | (bModeSynth << 1) | in ar5112SetChannel()
141 OS_REG_WRITE(ah, AR_PHY(0x27), reg32 & 0xff); in ar5112SetChannel()
143 reg32 >>= 8; in ar5112SetChannel()
144 OS_REG_WRITE(ah, AR_PHY(0x36), reg32 & 0x7f); in ar5112SetChannel()
H A Dar5212_reset.c68 void ar5212ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32,
2672 ar5212ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32, uint32_t numBits, in ar5212ModifyRfBuffer() argument
2683 tmp32 = ath_hal_reverseBits(reg32, numBits); in ar5212ModifyRfBuffer()
/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar9002/
H A Dar9287.c76 uint32_t freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0; in ar9287SetChannel() local
85 reg32 = OS_REG_READ(ah, AR_PHY_SYNTH_CONTROL); in ar9287SetChannel()
86 reg32 &= 0xc0000000; in ar9287SetChannel()
148 reg32 = reg32 | (bMode << 29) | (fracMode << 28) | in ar9287SetChannel()
151 OS_REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); in ar9287SetChannel()
H A Dar9280.c76 uint32_t freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0; in ar9280SetChannel() local
86 reg32 = OS_REG_READ(ah, AR_PHY_SYNTH_CONTROL); in ar9280SetChannel()
87 reg32 &= 0xc0000000; in ar9280SetChannel()
206 reg32 = reg32 | (bMode << 29) | (fracMode << 28) | in ar9280SetChannel()
209 OS_REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); in ar9280SetChannel()
/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5416/
H A Dar2133.c49 void ar5416ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32,
130 uint32_t reg32 = 0; in ar2133SetChannel() local
219 reg32 = (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) | in ar2133SetChannel()
222 OS_REG_WRITE(ah, AR_PHY(0x37), reg32); in ar2133SetChannel()
H A Dar5416_reset.c2314 int reg32; in ar5416WritePdadcValues() local
2320 reg32 = ((pdadcValues[4*j + 0] & 0xFF) << 0) | in ar5416WritePdadcValues()
2324 OS_REG_WRITE(ah, regOffset, reg32); in ar5416WritePdadcValues()
/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5211/
H A Dar5211_reset.c787 uint32_t refClk, reg32, data2111; in ar5211SetChannel() local
806 reg32 = ath_hal_reverseBits(chan5111 - 24, 8) & 0xFF; in ar5211SetChannel()
809 reg32 = ath_hal_reverseBits(((chan5111 - 24) / 2), 8) & 0xFF; in ar5211SetChannel()
813 reg32 = (reg32 << 2) | (refClk << 1) | (1 << 10) | 0x1; in ar5211SetChannel()
814 OS_REG_WRITE(ah, AR_PHY(0x27), ((data2111 & 0xff) << 8) | (reg32 & 0xff)); in ar5211SetChannel()
815 reg32 >>= 8; in ar5211SetChannel()
816 OS_REG_WRITE(ah, AR_PHY(0x34), (data2111 & 0xff00) | (reg32 & 0xff)); in ar5211SetChannel()