Searched refs:mmioIndex (Results 1 – 2 of 2) sorted by relevance
671 int mmioIndex = 1; in intel_map() local675 mmioIndex = 0; in intel_map()679 phys_addr_t addr = info.display.u.h0.base_registers[mmioIndex]; in intel_map()680 uint64 barSize = info.display.u.h0.base_register_sizes[mmioIndex]; in intel_map()681 if ((info.display.u.h0.base_register_flags[mmioIndex] & PCI_address_type) == PCI_address_type_64) { in intel_map()682 addr |= (uint64)info.display.u.h0.base_registers[mmioIndex + 1] << 32; in intel_map()683 barSize |= (uint64)info.display.u.h0.base_register_sizes[mmioIndex + 1] << 32; in intel_map()722 info.gtt_physical_base = info.display.u.h0.base_registers[mmioIndex] in intel_map()767 info.display.u.h0.base_registers[mmioIndex]); in intel_map()
629 int mmioIndex = 1; in intel_extreme_init() local633 mmioIndex = 0; in intel_extreme_init()646 phys_addr_t addr = info.pci->u.h0.base_registers[mmioIndex]; in intel_extreme_init()647 uint64 barSize = info.pci->u.h0.base_register_sizes[mmioIndex]; in intel_extreme_init()648 if ((info.pci->u.h0.base_register_flags[mmioIndex] & PCI_address_type) == PCI_address_type_64) { in intel_extreme_init()649 addr |= (uint64)info.pci->u.h0.base_registers[mmioIndex + 1] << 32; in intel_extreme_init()650 barSize |= (uint64)info.pci->u.h0.base_register_sizes[mmioIndex + 1] << 32; in intel_extreme_init()