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Searched refs:Write32 (Results 1 – 11 of 11) sorted by relevance

/haiku/src/add-ons/accelerants/radeon_hd/
H A Dgpu.cpp113 Write32(OUT, CP_ME_CNTL, CP_ME_HALT); in radeon_gpu_reset()
175 Write32(OUT, GRBM_SOFT_RESET, tmp); in radeon_gpu_reset()
178 Write32(OUT, GRBM_SOFT_RESET, 0); in radeon_gpu_reset()
183 Write32(OUT, GRBM_SOFT_RESET, tmp); in radeon_gpu_reset()
186 Write32(OUT, GRBM_SOFT_RESET, 0); in radeon_gpu_reset()
193 Write32(OUT, CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); in radeon_gpu_reset()
211 Write32(OUT, GRBM_SOFT_RESET, grbmReset); in radeon_gpu_reset()
215 Write32(OUT, GRBM_SOFT_RESET, 0); in radeon_gpu_reset()
281 Write32(OUT, AVIVO_VGA_RENDER_CONTROL, 0); in radeon_gpu_mc_halt()
282 Write32(OUT, AVIVO_D1CRTC_UPDATE_LOCK, 1); in radeon_gpu_mc_halt()
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H A Ddisplay.cpp606 Write32(OUT, NI_INPUT_CSC_CONTROL + regs->crtcOffset, in display_dce45_crtc_load_lut()
609 Write32(OUT, NI_PRESCALE_GRPH_CONTROL + regs->crtcOffset, in display_dce45_crtc_load_lut()
611 Write32(OUT, NI_PRESCALE_OVL_CONTROL + regs->crtcOffset, in display_dce45_crtc_load_lut()
613 Write32(OUT, NI_INPUT_GAMMA_CONTROL + regs->crtcOffset, in display_dce45_crtc_load_lut()
618 Write32(OUT, EVERGREEN_DC_LUT_CONTROL + regs->crtcOffset, 0); in display_dce45_crtc_load_lut()
620 Write32(OUT, EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + regs->crtcOffset, 0); in display_dce45_crtc_load_lut()
621 Write32(OUT, EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + regs->crtcOffset, 0); in display_dce45_crtc_load_lut()
622 Write32(OUT, EVERGREEN_DC_LUT_BLACK_OFFSET_RED + regs->crtcOffset, 0); in display_dce45_crtc_load_lut()
624 Write32(OUT, EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + regs->crtcOffset, 0xffff); in display_dce45_crtc_load_lut()
625 Write32(OUT, EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + regs->crtcOffset, 0xffff); in display_dce45_crtc_load_lut()
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H A Dbios.cpp53 Write32(OUT, R600_SCRATCH_REG2, biosScratch2); in radeon_bios_init_scratch()
54 Write32(OUT, R600_SCRATCH_REG6, biosScratch6); in radeon_bios_init_scratch()
56 Write32(OUT, RADEON_BIOS_2_SCRATCH, biosScratch2); in radeon_bios_init_scratch()
57 Write32(OUT, RADEON_BIOS_6_SCRATCH, biosScratch6); in radeon_bios_init_scratch()
H A Dconnector.cpp48 Write32(OUT, info->i2c.sclMaskReg, buffer); in gpio_lock_i2c()
53 Write32(OUT, info->i2c.sclAReg, buffer); in gpio_lock_i2c()
55 Write32(OUT, info->i2c.sdaAReg, buffer); in gpio_lock_i2c()
60 Write32(OUT, info->i2c.sclEnReg, buffer); in gpio_lock_i2c()
62 Write32(OUT, info->i2c.sdaEnReg, buffer); in gpio_lock_i2c()
71 Write32(OUT, info->i2c.sclMaskReg, buffer); in gpio_lock_i2c()
81 Write32(OUT, info->i2c.sdaMaskReg, buffer); in gpio_lock_i2c()
108 Write32(OUT, info->i2c.sclEnReg, scl); in gpio_set_i2c_bit()
113 Write32(OUT, info->i2c.sdaEnReg, sda); in gpio_set_i2c_bit()
H A Daccelerant.h267 Write32(uint32 subsystem, uint32 offset, uint32 value) in Write32() function
H A Dencoder.cpp382 Write32(OUT, regs->modeDataFormat, 0); in encoder_apply_quirks()
1812 Write32(OUT, R600_SCRATCH_REG3, biosScratch3); in encoder_crtc_scratch()
1887 Write32(OUT, R600_SCRATCH_REG2, biosScratch2); in encoder_dpms_scratch()
2046 Write32(OUT, AVIVO_DP_VID_STREAM_CNTL, 0x201); in encoder_dpms_set_dig()
2121 Write32(OUT, R600_SCRATCH_REG6, biosScratch6); in encoder_output_lock()
H A Dmode.cpp477 Write32(OUT, backlightReg, level); in radeon_set_brightness()
/haiku/src/add-ons/kernel/drivers/audio/hda/
H A Dhda_controller.cpp451 controller->Write32(HDAC_INTR_CONTROL, 0); in reset_controller()
487 controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 0); in reset_controller()
488 controller->Write32(HDAC_DMA_POSITION_BASE_UPPER, 0); in reset_controller()
494 controller->Write32(HDAC_GLOBAL_CONTROL, control & ~GLOBAL_CONTROL_RESET); in reset_controller()
507 controller->Write32(HDAC_GLOBAL_CONTROL, control | GLOBAL_CONTROL_RESET); in reset_controller()
520 controller->Write32(HDAC_GLOBAL_CONTROL, in reset_controller()
608 controller->Write32(HDAC_CORB_BASE_LOWER, (uint32)pe.address); in init_corb_rirb_pos()
610 controller->Write32(HDAC_CORB_BASE_UPPER, in init_corb_rirb_pos()
614 controller->Write32(HDAC_RIRB_BASE_LOWER, (uint32)pe.address + rirbOffset); in init_corb_rirb_pos()
616 controller->Write32(HDAC_RIRB_BASE_UPPER, in init_corb_rirb_pos()
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H A Ddriver.h114 void Write32(uint32 reg, uint32 value) in Write32() function
140 Write32(reg, temp); in ReadModifyWrite32()
212 void Write32(uint32 reg, uint32 value) in Write32() function
/haiku/src/add-ons/kernel/drivers/audio/ac97/geode/
H A Ddriver.h93 void Write32(uint32 reg, uint32 value) in Write32() function
160 void Write32(uint32 reg, uint32 value) in Write32() function
162 controller->Write32(ACC_BM0_CMD + offset + reg, value); in Write32()
H A Dgeode_controller.cpp56 controller->Write32(ACC_CODEC_CNTL, in geode_codec_read()
88 controller->Write32(ACC_CODEC_CNTL, in geode_codec_write()
157 controller->Write32(ACC_CODEC_CNTL, ACC_CODEC_CNTL_LNK_WRM_RST in reset_controller()
382 stream->Write32(STREAM_PRD, stream->physical_buffer_descriptors); in geode_stream_setup_buffers()