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Searched refs:WR4 (Results 1 – 2 of 2) sorted by relevance

/haiku/src/add-ons/kernel/drivers/network/wlan/marvell88w8363/dev/mwl/
H A Dmwlhal.c221 WR4(struct mwl_hal_priv *mh, bus_size_t off, uint32_t val) in WR4() function
491 WR4(mh, MACREG_REG_A2H_INTERRUPT_CAUSE,
507 WR4(mh, MACREG_REG_A2H_INTERRUPT_MASK, 0); in mwl_hal_intrset()
511 WR4(mh, MACREG_REG_A2H_INTERRUPT_MASK, mask); in mwl_hal_intrset()
528 WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, MACREG_H2ARIC_BIT_PPA_READY);
2174 WR4(mh, MACREG_REG_PROMISCUOUS, ena ? v | 1 : v &~ 1); in mwl_hal_setpromisc()
2350 WR4(mh, MACREG_REG_GEN_PTR, mh->mh_cmdaddr); in mwlSendCmd()
2353 WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, MACREG_H2ARIC_BIT_DOOR_BELL); in mwlSendCmd()
2439 WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, ISR_RESET); in mwlFwReset()
2449 WR4(mh, MACREG_REG_GEN_PTR, mh->mh_cmdaddr); in mwlTriggerPciCmd()
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H A Dif_mwl.c281 WR4(struct mwl_softc *sc, bus_size_t off, uint32_t val) in WR4() function
974 WR4(sc, sc->sc_hwspecs.rxDescRead, sc->sc_hwdma.rxDescRead); in mwl_setupdma()
975 WR4(sc, sc->sc_hwspecs.rxDescWrite, sc->sc_hwdma.rxDescRead); in mwl_setupdma()
980 WR4(sc, sc->sc_hwspecs.wcbBase[i], sc->sc_hwdma.wcbBase[i]); in mwl_setupdma()