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Searched refs:SetPLLReg (Results 1 – 4 of 4) sorted by relevance

/haiku/src/add-ons/accelerants/ati/
H A Drage128_mode.cpp261 SetPLLReg(R128_PPLL_REF_DIV, R128_PPLL_ATOMIC_UPDATE_W, R128_PPLL_ATOMIC_UPDATE_W); in PLLWriteUpdate()
321 SetPLLReg(R128_VCLK_ECP_CNTL, R128_VCLK_SRC_SEL_CPUCLK, R128_VCLK_SRC_SEL_MASK); in SetRegisters()
323 SetPLLReg(R128_PPLL_CNTL, 0xffffffff, in SetRegisters()
327 SetPLLReg(R128_PPLL_REF_DIV, params.ppll_ref_div, R128_PPLL_REF_DIV_MASK); in SetRegisters()
331 SetPLLReg(R128_PPLL_DIV_3, params.ppll_div_3, in SetRegisters()
336 SetPLLReg(R128_HTOTAL_CNTL, 0); in SetRegisters()
339 SetPLLReg(R128_PPLL_CNTL, 0, R128_PPLL_RESET in SetRegisters()
346 SetPLLReg(R128_VCLK_ECP_CNTL, R128_VCLK_SRC_SEL_PPLLCLK, in SetRegisters()
H A Drage128.h288 SetPLLReg(uint8 index, uint32 value) in SetPLLReg() function
296 SetPLLReg(uint8 index, uint32 value, uint32 mask) in SetPLLReg() function
301 SetPLLReg(index, (GetPLLReg(index) & ~mask) | (value & mask)); in SetPLLReg()
H A Drage128_draw.cpp46 SetPLLReg(R128_MCLK_CNTL, mclkCntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP); in Rage128_EngineReset()
55 SetPLLReg(R128_MCLK_CNTL, mclkCntl); in Rage128_EngineReset()
H A Drage128_overlay.cpp104 SetPLLReg(R128_VCLK_ECP_CNTL, ecpDiv << 8, R128_ECP_DIV_MASK); in Rage128_DisplayOverlay()