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Searched refs:SHOW_FLOW (Results 1 – 25 of 47) sorted by relevance

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/haiku/src/add-ons/accelerants/radeon/
H A DSetDisplayMode.c283 SHOW_FLOW( 0, "RADEON_DAC_CNTL %08X ", INREG( regs, RADEON_DAC_CNTL )); in Radeon_SetMode()
284 SHOW_FLOW( 0, "RADEON_DAC_CNTL2 %08X ", INREG( regs, RADEON_DAC_CNTL2 )); in Radeon_SetMode()
285 SHOW_FLOW( 0, "RADEON_TV_DAC_CNTL %08X ", INREG( regs, RADEON_TV_DAC_CNTL )); in Radeon_SetMode()
286 SHOW_FLOW( 0, "RADEON_DISP_OUTPUT_CNTL %08X ", INREG( regs, RADEON_DISP_OUTPUT_CNTL )); in Radeon_SetMode()
287 SHOW_FLOW( 0, "RADEON_AUX_SC_CNTL %08X ", INREG( regs, RADEON_AUX_SC_CNTL )); in Radeon_SetMode()
288 SHOW_FLOW( 0, "RADEON_CRTC_EXT_CNTL %08X ", INREG( regs, RADEON_CRTC_EXT_CNTL )); in Radeon_SetMode()
289 SHOW_FLOW( 0, "RADEON_CRTC_GEN_CNTL %08X ", INREG( regs, RADEON_CRTC_GEN_CNTL )); in Radeon_SetMode()
290 SHOW_FLOW( 0, "RADEON_CRTC2_GEN_CNTL %08X ", INREG( regs, RADEON_CRTC2_GEN_CNTL )); in Radeon_SetMode()
291 SHOW_FLOW( 0, "RADEON_DISP_MISC_CNTL %08X ", INREG( regs, RADEON_DISP_MISC_CNTL )); in Radeon_SetMode()
292 SHOW_FLOW( 0, "RADEON_FP_GEN_CNTL %08X ", INREG( regs, RADEON_FP_GEN_CNTL )); in Radeon_SetMode()
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H A DCP.c68 SHOW_FLOW( 3, "head=%ld, tail=%ld, space=%ld", in getAvailRingBuffer()
91 SHOW_FLOW( 3, "processed_tag=%d", cur_processed_tag ); in Radeon_FreeIndirectBuffers()
99 SHOW_FLOW( 3, "oldset buffer's tag: %d", oldest_buffer->send_tag ); in Radeon_FreeIndirectBuffers()
106 SHOW_FLOW( 3, "mark %d as being free", oldest_buffer->send_tag ); in Radeon_FreeIndirectBuffers()
188 SHOW_FLOW( 3, "got %d", buffer_idx ); in Radeon_AllocIndirectBuffer()
205 SHOW_FLOW( 3, "buffer_idx=%d, never_used=%d", buffer_idx, never_used ); in Radeon_FreeIndirectBuffer()
248 SHOW_FLOW( 3, "@%d: %x", ring_tail, val ); \
274 SHOW_FLOW( 3, "buffer_idx=%d, buffer_size=%d, state_buffer_idx=%d, state_buffer_size=%d", in Radeon_SendIndirectBuffer()
278 SHOW_FLOW( 3, "buffer has uneven size (%d)", buffer_size ); in Radeon_SendIndirectBuffer()
316 SHOW_FLOW( 3, "Assigned tag %d", cp->buffers.buffers[buffer_idx].send_tag ); in Radeon_SendIndirectBuffer()
H A Doverlay.c307 SHOW_FLOW( 3, "key=%lx", res ); in colourKey2RGB32()
494 SHOW_FLOW( 3, "p1_4tap_allowed=%d, p23_4t_allowed=%d", in getHScaleFactor()
518 SHOW_FLOW( 3, "group_size=%d, p1_step_by=%d, p23_step_by=%d", in getHScaleFactor()
606 SHOW_FLOW( 3, "ow: h=%d, v=%d, width=%d, height=%d", in Radeon_ShowOverlay()
610 SHOW_FLOW( 3, "offset_left=%d, offset_right=%d, offset_top=%d, offset_bottom=%d", in Radeon_ShowOverlay()
631 SHOW_FLOW( 3, "mode: w=%d, h=%d", in Radeon_ShowOverlay()
639 SHOW_FLOW( 3, "src=(%d, %d, %d, %d)", in Radeon_ShowOverlay()
641 SHOW_FLOW( 3, "dest=(%d, %d, %d, %d)", in Radeon_ShowOverlay()
655 SHOW_FLOW( 3, "ati_space=%d", node->ati_space ); in Radeon_ShowOverlay()
670 SHOW_FLOW( 3, "p1_h_inc=%x, p23_h_inc=%x", p1_h_inc, p23_h_inc ); in Radeon_ShowOverlay()
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H A Dimpactv.c65 SHOW_FLOW( 3, "f_first=%d, v_first=%d, h_first=%d", f_first, v_first, h_first ); in Radeon_CalcImpacTVRestart()
75 SHOW_FLOW( 3, "first_num=%d", first_num ); in Radeon_CalcImpacTVRestart()
81 SHOW_FLOW( 3, "time_to_active=%d, crt_freq=%d, tv_freq=%d", in Radeon_CalcImpacTVRestart()
95 SHOW_FLOW( 3, "restart_to_first_active_pixel_to_FIFO=%d", restart_to_first_active_pixel_to_FIFO ); in Radeon_CalcImpacTVRestart()
97 SHOW_FLOW( 3, "after delay compensation first_num=%d", first_num ); in Radeon_CalcImpacTVRestart()
117 SHOW_FLOW( 2, "Restart in frame %d, line %d, pixel %d", in Radeon_CalcImpacTVRestart()
164 SHOW_FLOW( 3, "flicker removal=%d", flicker_removal ); in Radeon_CalcImpacTVFlickerFixer()
170 SHOW_FLOW( 3, "%d < %d ?", in Radeon_CalcImpacTVFlickerFixer()
332 SHOW_FLOW( 2, "internal_encoder=%s, format=%d", in Radeon_CalcImpacTVParams()
374 SHOW_FLOW( 3, "lines_before_active=%d, start_line=%d", lines_before_active, start_line ); in Radeon_CalcImpacTVParams()
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H A DProposeDisplayMode.c157 SHOW_FLOW( 4, "CRTC %d, DVI %d", (crtc == &si->crtc[0]) ? 0 : 1, crtc->flatpanel_port ); in Radeon_ProposeDisplayMode()
158 SHOW_FLOW( 4, "X %d, virtX %d", target->timing.h_display, target->virtual_width); in Radeon_ProposeDisplayMode()
159 SHOW_FLOW( 4, "fpRes %dx%d", flatpanel->panel_xres, flatpanel->panel_yres); in Radeon_ProposeDisplayMode()
508 SHOW_FLOW( 4, "%ld, %ld not supported", dst->virtual_width, dst->virtual_height ); in checkAndAddMode()
520 SHOW_FLOW( 4, "%ld, %ld", mode->virtual_width, mode->virtual_height ); in checkAndAddMultiMode()
573 SHOW_FLOW( 2, "H: %4d %4d %4d %4d (v=%4d)", in addFPMode()
576 SHOW_FLOW( 2, "V: %4d %4d %4d %4d (h=%4d)", in addFPMode()
579 SHOW_FLOW( 2, "clk: %ld", mode.timing.pixel_clock ); in addFPMode()
659 SHOW_FLOW( 2, "H: %4d %4d %4d %4d (v=%4d)", in PROPOSE_DISPLAY_MODE()
662 SHOW_FLOW( 2, "V: %4d %4d %4d %4d (h=%4d)", in PROPOSE_DISPLAY_MODE()
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H A Dcrtc.c124 SHOW_FLOW( 2, "crtc_pitch=%ld", values->crtc_pitch ); in Radeon_CalcCRTCRegisters()
140 SHOW_FLOW( 3, "Setting address %x on port %d", in moveOneDisplay()
152 SHOW_FLOW( 4, "h_display_start=%ld, v_display_start=%ld", in Radeon_MoveDisplay()
H A DEngineManagment.c165 SHOW_FLOW( 4, "got counter=%d", si->engine.count ); in GET_SYNC_TOKEN()
200 SHOW_FLOW( 4, "passed counter=%d", in SYNC_TO_TOKEN()
H A Dmonitor_routing.c552 SHOW_FLOW( 2, "display_devices=%x, whished_num_heads=%d", in assignDefaultMonitorRoute()
563 SHOW_FLOW( 2, "after restriction: %x", display_devices ); in assignDefaultMonitorRoute()
641 SHOW_FLOW( 2, "CRTC1: 0x%x, CRTC2: 0x%x", crtc1_displays, crtc2_displays ); in assignDefaultMonitorRoute()
662 SHOW_FLOW( 2, "display_devices=%x, whished_num_heads=%d, use_laptop_panel=%d", in Radeon_SetupDefaultMonitorRouting()
679 SHOW_FLOW( 2, "num_crtc: %d, CRTC1 (%s): 0x%x, CRTC2 (%s): 0x%x", in Radeon_SetupDefaultMonitorRouting()
H A Doverlay_management.c119 SHOW_FLOW( 3, "Unsupported format (%x)", (int)cs ); in ALLOCATE_OVERLAY_BUFFER()
164 SHOW_FLOW( 0, "success: mem_handle=%x, offset=%x, CPU-address=%x, phys-address=%x", in ALLOCATE_OVERLAY_BUFFER()
200 SHOW_FLOW( 3, "ups - couldn't free memory (handle=%x, status=%s)", in RELEASE_OVERLAY_BUFFER()
/haiku/src/add-ons/kernel/bus_managers/scsi/
H A Dvirtual_memory.cpp35 SHOW_FLOW(3, "vec_count=%" B_PRIuSIZE ", vec_offset=%" B_PRIuSIZE ", len=%" in get_iovec_memory_map()
54 SHOW_FLOW( 3, "left_len=%d, vec_count=%d, cur_idx=%" B_PRIu32, in get_iovec_memory_map()
61 SHOW_FLOW( 3, "range_start=%" B_PRIxADDR ", range_len=%" B_PRIxSIZE, in get_iovec_memory_map()
88 SHOW_FLOW( 3, "cur_num_entries=%" B_PRIu32 ", cur_mapped_len=%x", in get_iovec_memory_map()
115 SHOW_FLOW( 3, "num_entries=%" B_PRIu32 ", mapped_len=%" B_PRIxSIZE, in get_iovec_memory_map()
H A Ddma_buffer.cpp66 SHOW_FLOW(0, "S/G-entry crosses DMA boundary @%" B_PRIxPHYSADDR, in is_sg_list_dma_safe()
73 SHOW_FLOW(0, "S/G-entry has bad alignment @%#" B_PRIxPHYSADDR, in is_sg_list_dma_safe()
79 SHOW_FLOW(0, "end of S/G-entry has bad alignment @%" B_PRIxPHYSADDR, in is_sg_list_dma_safe()
85 SHOW_FLOW(0, "S/G-entry above high address @%" B_PRIxPHYSADDR, in is_sg_list_dma_safe()
92 SHOW_FLOW(0, "S/G-entry is too long (%" B_PRIuPHYSADDR "/%" B_PRIu32 in is_sg_list_dma_safe()
112 SHOW_FLOW(1, "to_buffer=%d, %" B_PRIu32 " bytes", to_buffer, size); in scsi_copy_dma_buffer()
320 SHOW_FLOW(1, "count=%" B_PRIu32, sg_list_count); in dump_sg_table()
323 SHOW_FLOW(1, "addr=%" B_PRIxPHYSADDR ", size=%" B_PRIuPHYSADDR, in dump_sg_table()
443 SHOW_FLOW(1, "Buffering finished, %x, %" B_PRIx32, in scsi_release_dma_buffer()
H A Ddevice_scan.cpp48 SHOW_FLOW( 3, "status=%x", worker_req->subsys_status ); in scsi_scan_send_tur()
167 SHOW_FLOW(3, "%d:%d:%d", bus->path_id, target_id, target_lun); in scsi_scan_lun()
265 SHOW_FLOW(3, "initiator_id=%d", initiator_id); in scsi_scan_bus()
272 SHOW_FLOW(3, "target: %d", target_id); in scsi_scan_bus()
281 SHOW_FLOW(3, "lun: %d", lun); in scsi_scan_bus()
H A Dscatter_gather.cpp54 SHOW_FLOW(3, "Checking violation of dma boundary 0x%" B_PRIx32 in fill_temp_sg()
66 SHOW_FLOW(4, "addr=%#" B_PRIxPHYSADDR ", size=%" B_PRIxPHYSADDR in fill_temp_sg()
105 SHOW_FLOW(3, "ccb=%p, data=%p, data_length=%" B_PRIu32, ccb, ccb->data, in create_temp_sg()
140 SHOW_FLOW(3, "ccb=%p, data=%p, data_length=%" B_PRId32, in cleanup_temp_sg()
H A Demulation.cpp93 SHOW_FLOW(3, "physical = %#" B_PRIxPHYSADDR ", address = %p", in scsi_init_emulation_buffer()
186 SHOW_FLOW(3, "allocation_length=%" B_PRIuSIZE, allocationLength); in scsi_start_mode_sense_6()
238 SHOW_FLOW(3, "param_list_length=%ld", param_list_length_6); in scsi_start_mode_select_6()
281 SHOW_FLOW(3, "command=%x", request->cdb[0]); in scsi_start_emulation()
325 SHOW_FLOW(0, "fixing MODE SENSE(6) (%d bytes)", transfer_size_6); in scsi_finish_mode_sense_10_6()
388 SHOW_FLOW(3, "ANSI version: %d, response data format: %d", in scsi_finish_inquiry()
430 SHOW_FLOW( 3, "sense_key=%d, sense_asc=%d", sense_key, sense_asc ); in set_sense()
472 SHOW_FLOW(3, "offset=%u, req_size_limit=%d, size=%d, sg_list=%p, sg_count=%d, %s buffer", in copy_sg_data()
495 SHOW_FLOW(0, "buffer = %p, virt_addr = %#" B_PRIxPHYSADDR ", bytes = %" in copy_sg_data()
H A Dqueuing.h28 SHOW_FLOW( 3, "request=%p", request ); in scsi_add_req_queue_first()
37 SHOW_FLOW( 3, "request=%p", request ); in scsi_add_req_queue_last()
46 SHOW_FLOW( 3, "request=%p", request ); in scsi_remove_req_queue()
H A Ddpc.cpp49 SHOW_FLOW(3, "bus=%p, dpc=%p", bus, dpc); in scsi_schedule_dpc()
75 SHOW_FLOW(3, "bus=%p, dpc_list=%p", bus, bus->dpc_list); in scsi_check_exec_dpc()
H A Dscsi_io.cpp185 SHOW_FLOW(3, "Got sense: %d bytes", sense_len); in finish_autosense()
244 SHOW_FLOW(3, "%p", request); in scsi_request_finished()
280 SHOW_FLOW(3, "subsys=%x, device=%x, flags=%" B_PRIx32 in scsi_request_finished()
370 SHOW_FLOW(1, "%" B_PRId64, device->last_sort); in scsi_check_enqueue_request()
470 SHOW_FLOW(3, "ordered=%d", request->ordered); in scsi_async_io()
624 SHOW_FLOW(1, "%" B_PRId64, device->last_sort); in scsi_check_exec_service()
H A Dqueuing.cpp58 SHOW_FLOW( 3, "inserting new_request=%p, pos=%" B_PRId64, new_request, in scsi_insert_new_request()
69 SHOW_FLOW( 3, "first=%p, pos=%" B_PRId64 ", last_pos=%" B_PRId64, in scsi_insert_new_request()
157 SHOW_FLOW( 1, "inserting after %p (pos=%" B_PRId64 ") and before %p (pos=%" B_PRId64 ")", in scsi_insert_new_request()
H A Dbusses.cpp60 SHOW_FLOW(3, "bus = %p", bus); in scsi_service_threadproc()
261 SHOW_FLOW( 3, "Bus has %d slots", bus->left_slots ); in scsi_init_bus()
283 SHOW_FLOW(4, "path_id=%d", bus->path_id); in scsi_inquiry_path()
H A Dccb.cpp47 SHOW_FLOW(3, "path=%d", ccb->path_id); in scsi_alloc_ccb()
/haiku/src/add-ons/kernel/drivers/graphics/radeon/
H A Dvip.c108 SHOW_FLOW( 2, "address=%" B_PRIx32 ", count=%" B_PRIu32 " ", in do_VIPFifoRead()
235 SHOW_FLOW( 2, "address=%" B_PRIx32 ", count=%" B_PRIu32 ", ", in do_VIPFifoWrite()
247 SHOW_FLOW( 2 ,"cannot write %x to VIPH_REG_ADDR\n", in do_VIPFifoWrite()
256 SHOW_FLOW( 2, "count %" B_PRIu32, count); in do_VIPFifoWrite()
430 SHOW_FLOW( 3, "No device found on channel %d", channel); in Radeon_FindVIPDevice()
436 SHOW_FLOW( 3, "Device %08" B_PRIx32 " found on channel %d", in Radeon_FindVIPDevice()
/haiku/src/add-ons/kernel/generic/scsi_periph/
H A Derror_handling.cpp211 SHOW_FLOW(3, "%d", request->device_status & SCSI_STATUS_MASK); in check_scsi_status()
245 SHOW_FLOW(4, "%d", request->subsys_status & SCSI_SUBSYS_STATUS_MASK); in periph_check_error()
H A Dremovable.cpp140 SHOW_FLOW( 3, "action: %x, error: %x", (int)res.action, (int)res.error_code); in wait_for_ready()
186 SHOW_FLOW(3, "error_code: %x", (int)res.error_code); in periph_get_media_status()
/haiku/src/add-ons/kernel/drivers/bus/scsi/
H A Dscsi_raw.c141 SHOW_FLOW(4, "%x: %s", op, strerror(res)); in raw_ioctl()
209 SHOW_FLOW(3, "name=%s", name); in raw_device_added()
/haiku/headers/private/graphics/common/
H A Ddebug_ext.h78 #define SHOW_FLOW(seriousness, format, param...) \ macro

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