1 /* 2 * Copyright 2006-2022, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Axel Dörfler, axeld@pinc-software.de 7 * Alexander von Gluck IV, kallisti5@unixzen.com 8 */ 9 #ifndef RADEON_HD_H 10 #define RADEON_HD_H 11 12 13 #include "lock.h" 14 15 #include "radeon_reg.h" 16 17 //#include "r500_reg.h" // Not used atm. DCE 0 18 #include "avivo_reg.h" // DCE 1 19 #include "r600_reg.h" // DCE 2 20 #include "r700_reg.h" // DCE 3 21 #include "evergreen_reg.h" // DCE 4 22 #include "ni_reg.h" // DCE 5 23 #include "si_reg.h" // DCE 6 24 #include "sea_reg.h" // DCE 8 25 #include "vol_reg.h" // DCE 10 26 #include "car_reg.h" // DCE 11 27 #include "pol_reg.h" // DCE 12 28 29 #include <Accelerant.h> 30 #include <Drivers.h> 31 #include <edid.h> 32 #include <PCI.h> 33 34 35 #define VENDOR_ID_ATI 0x1002 36 37 // Card chipset flags 38 #define CHIP_STD (1 << 0) // Standard chipset 39 #define CHIP_X2 (1 << 1) // Dual cpu 40 #define CHIP_IGP (1 << 2) // IGP chipset 41 #define CHIP_MOBILE (1 << 3) // Mobile chipset 42 #define CHIP_DISCREET (1 << 4) // Discreet chipset 43 #define CHIP_APU (1 << 5) // APU chipset 44 45 #define DEVICE_NAME "radeon_hd" 46 #define RADEON_ACCELERANT_NAME "radeon_hd.accelerant" 47 48 #define MAX_NAME_LENGTH 32 49 50 // Used to collect EDID from boot loader 51 #define EDID_BOOT_INFO "vesa_edid/v1" 52 #define MODES_BOOT_INFO "vesa_modes/v1" 53 54 #define RHD_POWER_ON 0 55 #define RHD_POWER_RESET 1 /* off temporarily */ 56 #define RHD_POWER_SHUTDOWN 2 /* long term shutdown */ 57 #define RHD_POWER_UNKNOWN 3 /* initial state */ 58 59 60 // Radeon Chipsets 61 // !! Must match chipset names below 62 enum radeon_chipset { 63 RADEON_R420 = 0, //r400, Radeon X700-X850 64 RADEON_R423, 65 RADEON_RV410, 66 RADEON_RS400, 67 RADEON_RS480, 68 RADEON_RS600, 69 RADEON_RS690, 70 RADEON_RS740, 71 RADEON_RV515, 72 RADEON_R520, //r500, DCE 1.0 73 RADEON_RV530, // DCE 1.0 74 RADEON_RV560, // DCE 1.0 75 RADEON_RV570, // DCE 1.0 76 RADEON_R580, // DCE 1.0 77 RADEON_R600, //r600, DCE 2.0 78 RADEON_RV610, // DCE 2.0 79 RADEON_RV630, // DCE 2.0 80 RADEON_RV670, // DCE 2.0 81 RADEON_RV620, // DCE 3.0 82 RADEON_RV635, // DCE 3.0 83 RADEON_RS780, // DCE 3.0 84 RADEON_RS880, // DCE 3.0 85 RADEON_RV770, //r700, DCE 3.1 86 RADEON_RV730, // DCE 3.2 87 RADEON_RV710, // DCE 3.2 88 RADEON_RV740, // DCE 3.2 89 RADEON_CEDAR, //Evergreen, DCE 4.0 90 RADEON_REDWOOD, // DCE 4.0 91 RADEON_JUNIPER, // DCE 4.0 92 RADEON_CYPRESS, // DCE 4.0 93 RADEON_HEMLOCK, // DCE 4.0? 94 RADEON_PALM, //Fusion APU (NI), DCE 4.1 95 RADEON_SUMO, // DCE 4.1 96 RADEON_SUMO2, // DCE 4.1 97 RADEON_CAICOS, //Nothern Islands, DCE 5.0 98 RADEON_TURKS, // DCE 5.0 99 RADEON_BARTS, // DCE 5.0 100 RADEON_CAYMAN, // DCE 5.0 101 RADEON_ANTILLES, // DCE 5.0? 102 RADEON_CAPEVERDE, //Southern Islands, DCE 6.0 103 RADEON_PITCAIRN, // DCE 6.0 104 RADEON_TAHITI, // DCE 6.0 105 RADEON_ARUBA, // DCE 6.1 Trinity/Richland 106 RADEON_OLAND, // DCE 6.4 107 RADEON_HAINAN, // NO DCE, only compute 108 RADEON_KAVERI, //Sea Islands, DCE 8.1 109 RADEON_BONAIRE, // DCE 8.2 110 RADEON_KABINI, // DCE 8.3 111 RADEON_MULLINS, // DCE 8.3 112 RADEON_HAWAII, // DCE 8.5 113 RADEON_TOPAZ, //Volcanic Islands, NO DCE 114 RADEON_TONGA, // DCE 10.0 115 RADEON_FIJI, // DCE 10.1? 116 RADEON_CARRIZO, // DCE 11.0 117 RADEON_STONEY, // DCE 11.1? 118 RADEON_POLARIS11, //Artic Islands, DCE 12.1? 119 RADEON_POLARIS10, // DCE 12.0? 120 RADEON_POLARIS12, // DCE 12.2? 121 RADEON_VEGAM, // DCE 13.0? 122 RADEON_VEGA10, // DCE 13.0? 123 RADEON_VEGA12, // DCE 13.0? 124 RADEON_VEGA20, // DCE 13.0? 125 RADEON_RAVEN, // DCE 13? 126 RADEON_NAVI, // DCE 13.0? 127 }; 128 129 // !! Must match chipset families above 130 static const char radeon_chip_name[][MAX_NAME_LENGTH] = { 131 "R420", 132 "R423", 133 "RV410", 134 "RS400", 135 "RS480", 136 "RS600", 137 "RS690", 138 "RS740", 139 "RV515", 140 "R520", 141 "RV530", 142 "RV560", 143 "RV570", 144 "R580", 145 "R600", 146 "RV610", 147 "RV630", 148 "RV670", 149 "RV620", 150 "RV635", 151 "RS780", 152 "RS880", 153 "RV770", 154 "RV730", 155 "RV710", 156 "RV740", 157 "Cedar", 158 "Redwood", 159 "Juniper", 160 "Cypress", 161 "Hemlock", 162 "Palm", 163 "Sumo", 164 "Sumo2", 165 "Caicos", 166 "Turks", 167 "Barts", 168 "Cayman", 169 "Antilles", 170 "Cape Verde", 171 "Pitcairn", 172 "Tahiti", 173 "Aruba", 174 "Oland", 175 "Hainan", 176 "Kaveri", 177 "Bonaire", 178 "Kabini", 179 "Mullins", 180 "Hawaii", 181 "Topaz", 182 "Tonga", 183 "Fiji", 184 "Carrizo", 185 "Stoney Ridge", 186 "Polaris 11", 187 "Polaris 10", 188 "Polaris 12", 189 "Vega Mobile", 190 "Vega 10", 191 "Vega 12", 192 "Vega 20", 193 "Raven", 194 "Navi", 195 }; 196 197 198 struct ring_buffer { 199 struct lock lock; 200 uint32 register_base; 201 uint32 offset; 202 uint32 size; 203 uint32 position; 204 uint32 space_left; 205 uint8* base; 206 }; 207 208 209 struct radeon_shared_info { 210 uint32 deviceIndex; // accelerant index 211 uint32 pciID; // device pci id 212 uint32 pciRev; // device pci revision 213 area_id mode_list_area; // area containing display mode list 214 uint32 mode_count; 215 216 bool has_rom; // was rom mapped? 217 area_id rom_area; // area of mapped rom 218 uint32 rom_phys; // rom base location 219 uint32 rom_size; // rom size 220 uint8* rom; // cloned, memory mapped PCI ROM 221 222 display_mode current_mode; 223 uint32 bytes_per_row; 224 uint32 bits_per_pixel; 225 uint32 dpms_mode; 226 227 area_id registers_area; // area of memory mapped registers 228 uint8* status_page; 229 addr_t physical_status_page; 230 uint32 graphics_memory_size; 231 232 uint8* frame_buffer; // virtual memory mapped FB 233 area_id frame_buffer_area; // area of memory mapped FB 234 addr_t frame_buffer_phys; // card PCI BAR address of FB 235 uint32 frame_buffer_size; // FB size mapped 236 237 bool has_edid; 238 edid1_info edid_info; 239 240 struct lock accelerant_lock; 241 struct lock engine_lock; 242 243 ring_buffer primary_ring_buffer; 244 245 char deviceName[MAX_NAME_LENGTH]; 246 uint16 chipsetID; 247 char chipsetName[MAX_NAME_LENGTH]; 248 uint32 chipsetFlags; 249 uint8 dceMajor; 250 uint8 dceMinor; 251 252 uint16 color_data[3 * 256]; // colour lookup table 253 }; 254 255 //----------------- ioctl() interface ---------------- 256 257 // magic code for ioctls 258 #define RADEON_PRIVATE_DATA_MAGIC 'rdhd' 259 260 // list ioctls 261 enum { 262 RADEON_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 263 264 RADEON_GET_DEVICE_NAME, 265 RADEON_ALLOCATE_GRAPHICS_MEMORY, 266 RADEON_FREE_GRAPHICS_MEMORY 267 }; 268 269 // retrieve the area_id of the kernel/accelerant shared info 270 struct radeon_get_private_data { 271 uint32 magic; // magic number 272 area_id shared_info_area; 273 }; 274 275 // allocate graphics memory 276 struct radeon_allocate_graphics_memory { 277 uint32 magic; 278 uint32 size; 279 uint32 alignment; 280 uint32 flags; 281 uint32 buffer_base; 282 }; 283 284 // free graphics memory 285 struct radeon_free_graphics_memory { 286 uint32 magic; 287 uint32 buffer_base; 288 }; 289 290 // registers 291 #define R6XX_CONFIG_APER_SIZE 0x5430 // r600> 292 #define OLD_CONFIG_APER_SIZE 0x0108 // <r600 293 #define CONFIG_MEMSIZE 0x5428 // r600> 294 #define CONFIG_MEMSIZE_TAHITI 0x03de // tahiti> 295 296 297 #endif /* RADEON_HD_H */ 298