1 /*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 /* 31 * PCIM_xxx: mask to locate subfield in register 32 * PCIR_xxx: config register offset 33 * PCIC_xxx: device class 34 * PCIS_xxx: device subclass 35 * PCIP_xxx: device programming interface 36 * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices) 37 * PCID_xxx: device ID 38 * PCIY_xxx: capability identification number 39 * PCIZ_xxx: extended capability identification number 40 */ 41 42 /* some PCI bus constants */ 43 #define PCI_DOMAINMAX 65535 /* highest supported domain number */ 44 #define PCI_BUSMAX 255 /* highest supported bus number */ 45 #define PCI_SLOTMAX 31 /* highest supported slot number */ 46 #define PCI_FUNCMAX 7 /* highest supported function number */ 47 #define PCI_REGMAX 255 /* highest supported config register addr. */ 48 #define PCIE_REGMAX 4095 /* highest supported config register addr. */ 49 #define PCI_MAXHDRTYPE 2 50 51 /* PCI config header registers for all devices */ 52 53 #define PCIR_DEVVENDOR 0x00 54 #define PCIR_VENDOR 0x00 55 #define PCIR_DEVICE 0x02 56 #define PCIR_COMMAND 0x04 57 #define PCIM_CMD_PORTEN 0x0001 58 #define PCIM_CMD_MEMEN 0x0002 59 #define PCIM_CMD_BUSMASTEREN 0x0004 60 #define PCIM_CMD_SPECIALEN 0x0008 61 #define PCIM_CMD_MWRICEN 0x0010 62 #define PCIM_CMD_PERRESPEN 0x0040 63 #define PCIM_CMD_SERRESPEN 0x0100 64 #define PCIM_CMD_BACKTOBACK 0x0200 65 #define PCIM_CMD_INTxDIS 0x0400 66 #define PCIR_STATUS 0x06 67 #define PCIM_STATUS_INTxSTATE 0x0008 68 #define PCIM_STATUS_CAPPRESENT 0x0010 69 #define PCIM_STATUS_66CAPABLE 0x0020 70 #define PCIM_STATUS_BACKTOBACK 0x0080 71 #define PCIM_STATUS_MDPERR 0x0100 72 #define PCIM_STATUS_SEL_FAST 0x0000 73 #define PCIM_STATUS_SEL_MEDIMUM 0x0200 74 #define PCIM_STATUS_SEL_SLOW 0x0400 75 #define PCIM_STATUS_SEL_MASK 0x0600 76 #define PCIM_STATUS_STABORT 0x0800 77 #define PCIM_STATUS_RTABORT 0x1000 78 #define PCIM_STATUS_RMABORT 0x2000 79 #define PCIM_STATUS_SERR 0x4000 80 #define PCIM_STATUS_PERR 0x8000 81 #define PCIR_REVID 0x08 82 #define PCIR_PROGIF 0x09 83 #define PCIR_SUBCLASS 0x0a 84 #define PCIR_CLASS 0x0b 85 #define PCIR_CACHELNSZ 0x0c 86 #define PCIR_LATTIMER 0x0d 87 #define PCIR_HDRTYPE 0x0e 88 #define PCIM_HDRTYPE 0x7f 89 #define PCIM_HDRTYPE_NORMAL 0x00 90 #define PCIM_HDRTYPE_BRIDGE 0x01 91 #define PCIM_HDRTYPE_CARDBUS 0x02 92 #define PCIM_MFDEV 0x80 93 #define PCIR_BIST 0x0f 94 95 /* Capability Register Offsets */ 96 97 #define PCICAP_ID 0x0 98 #define PCICAP_NEXTPTR 0x1 99 100 /* Capability Identification Numbers */ 101 102 #define PCIY_PMG 0x01 /* PCI Power Management */ 103 #define PCIY_AGP 0x02 /* AGP */ 104 #define PCIY_VPD 0x03 /* Vital Product Data */ 105 #define PCIY_SLOTID 0x04 /* Slot Identification */ 106 #define PCIY_MSI 0x05 /* Message Signaled Interrupts */ 107 #define PCIY_CHSWP 0x06 /* CompactPCI Hot Swap */ 108 #define PCIY_PCIX 0x07 /* PCI-X */ 109 #define PCIY_HT 0x08 /* HyperTransport */ 110 #define PCIY_VENDOR 0x09 /* Vendor Unique */ 111 #define PCIY_DEBUG 0x0a /* Debug port */ 112 #define PCIY_CRES 0x0b /* CompactPCI central resource control */ 113 #define PCIY_HOTPLUG 0x0c /* PCI Hot-Plug */ 114 #define PCIY_SUBVENDOR 0x0d /* PCI-PCI bridge subvendor ID */ 115 #define PCIY_AGP8X 0x0e /* AGP 8x */ 116 #define PCIY_SECDEV 0x0f /* Secure Device */ 117 #define PCIY_EXPRESS 0x10 /* PCI Express */ 118 #define PCIY_MSIX 0x11 /* MSI-X */ 119 #define PCIY_SATA 0x12 /* SATA */ 120 #define PCIY_PCIAF 0x13 /* PCI Advanced Features */ 121 122 /* Extended Capability Register Fields */ 123 124 #define PCIR_EXTCAP 0x100 125 #define PCIM_EXTCAP_ID 0x0000ffff 126 #define PCIM_EXTCAP_VER 0x000f0000 127 #define PCIM_EXTCAP_NEXTPTR 0xfff00000 128 #define PCI_EXTCAP_ID(ecap) ((ecap) & PCIM_EXTCAP_ID) 129 #define PCI_EXTCAP_VER(ecap) (((ecap) & PCIM_EXTCAP_VER) >> 16) 130 #define PCI_EXTCAP_NEXTPTR(ecap) (((ecap) & PCIM_EXTCAP_NEXTPTR) >> 20) 131 132 /* Extended Capability Identification Numbers */ 133 134 #define PCIZ_AER 0x0001 /* Advanced Error Reporting */ 135 #define PCIZ_VC 0x0002 /* Virtual Channel */ 136 #define PCIZ_SERNUM 0x0003 /* Device Serial Number */ 137 #define PCIZ_PWRBDGT 0x0004 /* Power Budgeting */ 138 #define PCIZ_RCLINK_DCL 0x0005 /* Root Complex Link Declaration */ 139 #define PCIZ_RCLINK_CTL 0x0006 /* Root Complex Internal Link Control */ 140 #define PCIZ_RCEC_ASSOC 0x0007 /* Root Complex Event Collector Association */ 141 #define PCIZ_MFVC 0x0008 /* Multi-Function Virtual Channel */ 142 #define PCIZ_RCRB 0x000a /* RCRB Header */ 143 #define PCIZ_VENDOR 0x000b /* Vendor Unique */ 144 #define PCIZ_ACS 0x000d /* Access Control Services */ 145 #define PCIZ_ARI 0x000e /* Alternative Routing-ID Interpretation */ 146 #define PCIZ_ATS 0x000f /* Address Translation Services */ 147 #define PCIZ_SRIOV 0x0010 /* Single Root IO Virtualization */ 148 #define PCIZ_MULTICAST 0x0012 /* Multicast */ 149 #define PCIZ_RESIZE_BAR 0x0015 /* Resizable BAR */ 150 #define PCIZ_DPA 0x0016 /* Dynamic Power Allocation */ 151 #define PCIZ_TPH_REQ 0x0017 /* TPH Requester */ 152 #define PCIZ_LTR 0x0018 /* Latency Tolerance Reporting */ 153 #define PCIZ_SEC_PCIE 0x0019 /* Secondary PCI Express */ 154 155 /* config registers for header type 0 devices */ 156 157 #define PCIR_BARS 0x10 158 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4) 159 #define PCIR_MAX_BAR_0 5 160 #define PCI_RID2BAR(rid) (((rid) - PCIR_BARS) / 4) 161 #define PCI_BAR_IO(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE) 162 #define PCI_BAR_MEM(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_MEM_SPACE) 163 #define PCIM_BAR_SPACE 0x00000001 164 #define PCIM_BAR_MEM_SPACE 0 165 #define PCIM_BAR_IO_SPACE 1 166 #define PCIM_BAR_MEM_TYPE 0x00000006 167 #define PCIM_BAR_MEM_32 0 168 #define PCIM_BAR_MEM_1MB 2 /* Locate below 1MB in PCI <= 2.1 */ 169 #define PCIM_BAR_MEM_64 4 170 #define PCIM_BAR_MEM_PREFETCH 0x00000008 171 #define PCIM_BAR_MEM_BASE 0xfffffffffffffff0ULL 172 #define PCIM_BAR_IO_RESERVED 0x00000002 173 #define PCIM_BAR_IO_BASE 0xfffffffc 174 #define PCIR_CIS 0x28 175 #define PCIM_CIS_ASI_MASK 0x00000007 176 #define PCIM_CIS_ASI_CONFIG 0 177 #define PCIM_CIS_ASI_BAR0 1 178 #define PCIM_CIS_ASI_BAR1 2 179 #define PCIM_CIS_ASI_BAR2 3 180 #define PCIM_CIS_ASI_BAR3 4 181 #define PCIM_CIS_ASI_BAR4 5 182 #define PCIM_CIS_ASI_BAR5 6 183 #define PCIM_CIS_ASI_ROM 7 184 #define PCIM_CIS_ADDR_MASK 0x0ffffff8 185 #define PCIM_CIS_ROM_MASK 0xf0000000 186 #define PCIM_CIS_CONFIG_MASK 0xff 187 #define PCIR_SUBVEND_0 0x2c 188 #define PCIR_SUBDEV_0 0x2e 189 #define PCIR_BIOS 0x30 190 #define PCIM_BIOS_ENABLE 0x01 191 #define PCIM_BIOS_ADDR_MASK 0xfffff800 192 #define PCIR_CAP_PTR 0x34 193 #define PCIR_INTLINE 0x3c 194 #define PCIR_INTPIN 0x3d 195 #define PCIR_MINGNT 0x3e 196 #define PCIR_MAXLAT 0x3f 197 198 /* config registers for header type 1 (PCI-to-PCI bridge) devices */ 199 200 #define PCIR_MAX_BAR_1 1 201 #define PCIR_SECSTAT_1 0x1e 202 203 #define PCIR_PRIBUS_1 0x18 204 #define PCIR_SECBUS_1 0x19 205 #define PCIR_SUBBUS_1 0x1a 206 #define PCIR_SECLAT_1 0x1b 207 208 #define PCIR_IOBASEL_1 0x1c 209 #define PCIR_IOLIMITL_1 0x1d 210 #define PCIR_IOBASEH_1 0x30 211 #define PCIR_IOLIMITH_1 0x32 212 #define PCIM_BRIO_16 0x0 213 #define PCIM_BRIO_32 0x1 214 #define PCIM_BRIO_MASK 0xf 215 216 #define PCIR_MEMBASE_1 0x20 217 #define PCIR_MEMLIMIT_1 0x22 218 219 #define PCIR_PMBASEL_1 0x24 220 #define PCIR_PMLIMITL_1 0x26 221 #define PCIR_PMBASEH_1 0x28 222 #define PCIR_PMLIMITH_1 0x2c 223 #define PCIM_BRPM_32 0x0 224 #define PCIM_BRPM_64 0x1 225 #define PCIM_BRPM_MASK 0xf 226 227 #define PCIR_BIOS_1 0x38 228 #define PCIR_BRIDGECTL_1 0x3e 229 230 /* config registers for header type 2 (CardBus) devices */ 231 232 #define PCIR_MAX_BAR_2 0 233 #define PCIR_CAP_PTR_2 0x14 234 #define PCIR_SECSTAT_2 0x16 235 236 #define PCIR_PRIBUS_2 0x18 237 #define PCIR_SECBUS_2 0x19 238 #define PCIR_SUBBUS_2 0x1a 239 #define PCIR_SECLAT_2 0x1b 240 241 #define PCIR_MEMBASE0_2 0x1c 242 #define PCIR_MEMLIMIT0_2 0x20 243 #define PCIR_MEMBASE1_2 0x24 244 #define PCIR_MEMLIMIT1_2 0x28 245 #define PCIR_IOBASE0_2 0x2c 246 #define PCIR_IOLIMIT0_2 0x30 247 #define PCIR_IOBASE1_2 0x34 248 #define PCIR_IOLIMIT1_2 0x38 249 250 #define PCIR_BRIDGECTL_2 0x3e 251 252 #define PCIR_SUBVEND_2 0x40 253 #define PCIR_SUBDEV_2 0x42 254 255 #define PCIR_PCCARDIF_2 0x44 256 257 /* PCI device class, subclass and programming interface definitions */ 258 259 #define PCIC_OLD 0x00 260 #define PCIS_OLD_NONVGA 0x00 261 #define PCIS_OLD_VGA 0x01 262 263 #define PCIC_STORAGE 0x01 264 #define PCIS_STORAGE_SCSI 0x00 265 #define PCIS_STORAGE_IDE 0x01 266 #define PCIP_STORAGE_IDE_MODEPRIM 0x01 267 #define PCIP_STORAGE_IDE_PROGINDPRIM 0x02 268 #define PCIP_STORAGE_IDE_MODESEC 0x04 269 #define PCIP_STORAGE_IDE_PROGINDSEC 0x08 270 #define PCIP_STORAGE_IDE_MASTERDEV 0x80 271 #define PCIS_STORAGE_FLOPPY 0x02 272 #define PCIS_STORAGE_IPI 0x03 273 #define PCIS_STORAGE_RAID 0x04 274 #define PCIS_STORAGE_ATA_ADMA 0x05 275 #define PCIS_STORAGE_SATA 0x06 276 #define PCIP_STORAGE_SATA_AHCI_1_0 0x01 277 #define PCIS_STORAGE_SAS 0x07 278 #define PCIS_STORAGE_NVM 0x08 279 #define PCIP_STORAGE_NVM_NVMHCI_1_0 0x01 280 #define PCIP_STORAGE_NVM_ENTERPRISE_NVMHCI_1_0 0x02 281 #define PCIS_STORAGE_OTHER 0x80 282 283 #define PCIC_NETWORK 0x02 284 #define PCIS_NETWORK_ETHERNET 0x00 285 #define PCIS_NETWORK_TOKENRING 0x01 286 #define PCIS_NETWORK_FDDI 0x02 287 #define PCIS_NETWORK_ATM 0x03 288 #define PCIS_NETWORK_ISDN 0x04 289 #define PCIS_NETWORK_WORLDFIP 0x05 290 #define PCIS_NETWORK_PICMG 0x06 291 #define PCIS_NETWORK_OTHER 0x80 292 293 #define PCIC_DISPLAY 0x03 294 #define PCIS_DISPLAY_VGA 0x00 295 #define PCIS_DISPLAY_XGA 0x01 296 #define PCIS_DISPLAY_3D 0x02 297 #define PCIS_DISPLAY_OTHER 0x80 298 299 #define PCIC_MULTIMEDIA 0x04 300 #define PCIS_MULTIMEDIA_VIDEO 0x00 301 #define PCIS_MULTIMEDIA_AUDIO 0x01 302 #define PCIS_MULTIMEDIA_TELE 0x02 303 #define PCIS_MULTIMEDIA_HDA 0x03 304 #define PCIS_MULTIMEDIA_OTHER 0x80 305 306 #define PCIC_MEMORY 0x05 307 #define PCIS_MEMORY_RAM 0x00 308 #define PCIS_MEMORY_FLASH 0x01 309 #define PCIS_MEMORY_OTHER 0x80 310 311 #define PCIC_BRIDGE 0x06 312 #define PCIS_BRIDGE_HOST 0x00 313 #define PCIS_BRIDGE_ISA 0x01 314 #define PCIS_BRIDGE_EISA 0x02 315 #define PCIS_BRIDGE_MCA 0x03 316 #define PCIS_BRIDGE_PCI 0x04 317 #define PCIP_BRIDGE_PCI_SUBTRACTIVE 0x01 318 #define PCIS_BRIDGE_PCMCIA 0x05 319 #define PCIS_BRIDGE_NUBUS 0x06 320 #define PCIS_BRIDGE_CARDBUS 0x07 321 #define PCIS_BRIDGE_RACEWAY 0x08 322 #define PCIS_BRIDGE_PCI_TRANSPARENT 0x09 323 #define PCIS_BRIDGE_INFINIBAND 0x0a 324 #define PCIS_BRIDGE_OTHER 0x80 325 326 #define PCIC_SIMPLECOMM 0x07 327 #define PCIS_SIMPLECOMM_UART 0x00 328 #define PCIP_SIMPLECOMM_UART_8250 0x00 329 #define PCIP_SIMPLECOMM_UART_16450A 0x01 330 #define PCIP_SIMPLECOMM_UART_16550A 0x02 331 #define PCIP_SIMPLECOMM_UART_16650A 0x03 332 #define PCIP_SIMPLECOMM_UART_16750A 0x04 333 #define PCIP_SIMPLECOMM_UART_16850A 0x05 334 #define PCIP_SIMPLECOMM_UART_16950A 0x06 335 #define PCIS_SIMPLECOMM_PAR 0x01 336 #define PCIS_SIMPLECOMM_MULSER 0x02 337 #define PCIS_SIMPLECOMM_MODEM 0x03 338 #define PCIS_SIMPLECOMM_GPIB 0x04 339 #define PCIS_SIMPLECOMM_SMART_CARD 0x05 340 #define PCIS_SIMPLECOMM_OTHER 0x80 341 342 #define PCIC_BASEPERIPH 0x08 343 #define PCIS_BASEPERIPH_PIC 0x00 344 #define PCIP_BASEPERIPH_PIC_8259A 0x00 345 #define PCIP_BASEPERIPH_PIC_ISA 0x01 346 #define PCIP_BASEPERIPH_PIC_EISA 0x02 347 #define PCIP_BASEPERIPH_PIC_IO_APIC 0x10 348 #define PCIP_BASEPERIPH_PIC_IOX_APIC 0x20 349 #define PCIS_BASEPERIPH_DMA 0x01 350 #define PCIS_BASEPERIPH_TIMER 0x02 351 #define PCIS_BASEPERIPH_RTC 0x03 352 #define PCIS_BASEPERIPH_PCIHOT 0x04 353 #define PCIS_BASEPERIPH_SDHC 0x05 354 #define PCIS_BASEPERIPH_OTHER 0x80 355 356 #define PCIC_INPUTDEV 0x09 357 #define PCIS_INPUTDEV_KEYBOARD 0x00 358 #define PCIS_INPUTDEV_DIGITIZER 0x01 359 #define PCIS_INPUTDEV_MOUSE 0x02 360 #define PCIS_INPUTDEV_SCANNER 0x03 361 #define PCIS_INPUTDEV_GAMEPORT 0x04 362 #define PCIS_INPUTDEV_OTHER 0x80 363 364 #define PCIC_DOCKING 0x0a 365 #define PCIS_DOCKING_GENERIC 0x00 366 #define PCIS_DOCKING_OTHER 0x80 367 368 #define PCIC_PROCESSOR 0x0b 369 #define PCIS_PROCESSOR_386 0x00 370 #define PCIS_PROCESSOR_486 0x01 371 #define PCIS_PROCESSOR_PENTIUM 0x02 372 #define PCIS_PROCESSOR_ALPHA 0x10 373 #define PCIS_PROCESSOR_POWERPC 0x20 374 #define PCIS_PROCESSOR_MIPS 0x30 375 #define PCIS_PROCESSOR_COPROC 0x40 376 377 #define PCIC_SERIALBUS 0x0c 378 #define PCIS_SERIALBUS_FW 0x00 379 #define PCIS_SERIALBUS_ACCESS 0x01 380 #define PCIS_SERIALBUS_SSA 0x02 381 #define PCIS_SERIALBUS_USB 0x03 382 #define PCIP_SERIALBUS_USB_UHCI 0x00 383 #define PCIP_SERIALBUS_USB_OHCI 0x10 384 #define PCIP_SERIALBUS_USB_EHCI 0x20 385 #define PCIP_SERIALBUS_USB_XHCI 0x30 386 #define PCIP_SERIALBUS_USB_DEVICE 0xfe 387 #define PCIS_SERIALBUS_FC 0x04 388 #define PCIS_SERIALBUS_SMBUS 0x05 389 #define PCIS_SERIALBUS_INFINIBAND 0x06 390 #define PCIS_SERIALBUS_IPMI 0x07 391 #define PCIP_SERIALBUS_IPMI_SMIC 0x00 392 #define PCIP_SERIALBUS_IPMI_KCS 0x01 393 #define PCIP_SERIALBUS_IPMI_BT 0x02 394 #define PCIS_SERIALBUS_SERCOS 0x08 395 #define PCIS_SERIALBUS_CANBUS 0x09 396 397 #define PCIC_WIRELESS 0x0d 398 #define PCIS_WIRELESS_IRDA 0x00 399 #define PCIS_WIRELESS_IR 0x01 400 #define PCIS_WIRELESS_RF 0x10 401 #define PCIS_WIRELESS_BLUETOOTH 0x11 402 #define PCIS_WIRELESS_BROADBAND 0x12 403 #define PCIS_WIRELESS_80211A 0x20 404 #define PCIS_WIRELESS_80211B 0x21 405 #define PCIS_WIRELESS_OTHER 0x80 406 407 #define PCIC_INTELLIIO 0x0e 408 #define PCIS_INTELLIIO_I2O 0x00 409 410 #define PCIC_SATCOM 0x0f 411 #define PCIS_SATCOM_TV 0x01 412 #define PCIS_SATCOM_AUDIO 0x02 413 #define PCIS_SATCOM_VOICE 0x03 414 #define PCIS_SATCOM_DATA 0x04 415 416 #define PCIC_CRYPTO 0x10 417 #define PCIS_CRYPTO_NETCOMP 0x00 418 #define PCIS_CRYPTO_ENTERTAIN 0x10 419 #define PCIS_CRYPTO_OTHER 0x80 420 421 #define PCIC_DASP 0x11 422 #define PCIS_DASP_DPIO 0x00 423 #define PCIS_DASP_PERFCNTRS 0x01 424 #define PCIS_DASP_COMM_SYNC 0x10 425 #define PCIS_DASP_MGMT_CARD 0x20 426 #define PCIS_DASP_OTHER 0x80 427 428 #define PCIC_OTHER 0xff 429 430 /* Bridge Control Values. */ 431 #define PCIB_BCR_PERR_ENABLE 0x0001 432 #define PCIB_BCR_SERR_ENABLE 0x0002 433 #define PCIB_BCR_ISA_ENABLE 0x0004 434 #define PCIB_BCR_VGA_ENABLE 0x0008 435 #define PCIB_BCR_MASTER_ABORT_MODE 0x0020 436 #define PCIB_BCR_SECBUS_RESET 0x0040 437 #define PCIB_BCR_SECBUS_BACKTOBACK 0x0080 438 #define PCIB_BCR_PRI_DISCARD_TIMEOUT 0x0100 439 #define PCIB_BCR_SEC_DISCARD_TIMEOUT 0x0200 440 #define PCIB_BCR_DISCARD_TIMER_STATUS 0x0400 441 #define PCIB_BCR_DISCARD_TIMER_SERREN 0x0800 442 443 /* PCI power manangement */ 444 #define PCIR_POWER_CAP 0x2 445 #define PCIM_PCAP_SPEC 0x0007 446 #define PCIM_PCAP_PMEREQCLK 0x0008 447 #define PCIM_PCAP_DEVSPECINIT 0x0020 448 #define PCIM_PCAP_AUXPWR_0 0x0000 449 #define PCIM_PCAP_AUXPWR_55 0x0040 450 #define PCIM_PCAP_AUXPWR_100 0x0080 451 #define PCIM_PCAP_AUXPWR_160 0x00c0 452 #define PCIM_PCAP_AUXPWR_220 0x0100 453 #define PCIM_PCAP_AUXPWR_270 0x0140 454 #define PCIM_PCAP_AUXPWR_320 0x0180 455 #define PCIM_PCAP_AUXPWR_375 0x01c0 456 #define PCIM_PCAP_AUXPWRMASK 0x01c0 457 #define PCIM_PCAP_D1SUPP 0x0200 458 #define PCIM_PCAP_D2SUPP 0x0400 459 #define PCIM_PCAP_D0PME 0x0800 460 #define PCIM_PCAP_D1PME 0x1000 461 #define PCIM_PCAP_D2PME 0x2000 462 #define PCIM_PCAP_D3PME_HOT 0x4000 463 #define PCIM_PCAP_D3PME_COLD 0x8000 464 465 #define PCIR_POWER_STATUS 0x4 466 #define PCIM_PSTAT_D0 0x0000 467 #define PCIM_PSTAT_D1 0x0001 468 #define PCIM_PSTAT_D2 0x0002 469 #define PCIM_PSTAT_D3 0x0003 470 #define PCIM_PSTAT_DMASK 0x0003 471 #define PCIM_PSTAT_NOSOFTRESET 0x0008 472 #define PCIM_PSTAT_PMEENABLE 0x0100 473 #define PCIM_PSTAT_D0POWER 0x0000 474 #define PCIM_PSTAT_D1POWER 0x0200 475 #define PCIM_PSTAT_D2POWER 0x0400 476 #define PCIM_PSTAT_D3POWER 0x0600 477 #define PCIM_PSTAT_D0HEAT 0x0800 478 #define PCIM_PSTAT_D1HEAT 0x0a00 479 #define PCIM_PSTAT_D2HEAT 0x0c00 480 #define PCIM_PSTAT_D3HEAT 0x0e00 481 #define PCIM_PSTAT_DATASELMASK 0x1e00 482 #define PCIM_PSTAT_DATAUNKN 0x0000 483 #define PCIM_PSTAT_DATADIV10 0x2000 484 #define PCIM_PSTAT_DATADIV100 0x4000 485 #define PCIM_PSTAT_DATADIV1000 0x6000 486 #define PCIM_PSTAT_DATADIVMASK 0x6000 487 #define PCIM_PSTAT_PME 0x8000 488 489 #define PCIR_POWER_BSE 0x6 490 #define PCIM_PMCSR_BSE_D3B3 0x00 491 #define PCIM_PMCSR_BSE_D3B2 0x40 492 #define PCIM_PMCSR_BSE_BPCCE 0x80 493 494 #define PCIR_POWER_DATA 0x7 495 496 /* VPD capability registers */ 497 #define PCIR_VPD_ADDR 0x2 498 #define PCIR_VPD_DATA 0x4 499 500 /* PCI Message Signalled Interrupts (MSI) */ 501 #define PCIR_MSI_CTRL 0x2 502 #define PCIM_MSICTRL_VECTOR 0x0100 503 #define PCIM_MSICTRL_64BIT 0x0080 504 #define PCIM_MSICTRL_MME_MASK 0x0070 505 #define PCIM_MSICTRL_MME_1 0x0000 506 #define PCIM_MSICTRL_MME_2 0x0010 507 #define PCIM_MSICTRL_MME_4 0x0020 508 #define PCIM_MSICTRL_MME_8 0x0030 509 #define PCIM_MSICTRL_MME_16 0x0040 510 #define PCIM_MSICTRL_MME_32 0x0050 511 #define PCIM_MSICTRL_MMC_MASK 0x000E 512 #define PCIM_MSICTRL_MMC_1 0x0000 513 #define PCIM_MSICTRL_MMC_2 0x0002 514 #define PCIM_MSICTRL_MMC_4 0x0004 515 #define PCIM_MSICTRL_MMC_8 0x0006 516 #define PCIM_MSICTRL_MMC_16 0x0008 517 #define PCIM_MSICTRL_MMC_32 0x000A 518 #define PCIM_MSICTRL_MSI_ENABLE 0x0001 519 #define PCIR_MSI_ADDR 0x4 520 #define PCIR_MSI_ADDR_HIGH 0x8 521 #define PCIR_MSI_DATA 0x8 522 #define PCIR_MSI_DATA_64BIT 0xc 523 #define PCIR_MSI_MASK 0x10 524 #define PCIR_MSI_PENDING 0x14 525 526 /* PCI-X definitions */ 527 528 /* For header type 0 devices */ 529 #define PCIXR_COMMAND 0x2 530 #define PCIXM_COMMAND_DPERR_E 0x0001 /* Data Parity Error Recovery */ 531 #define PCIXM_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */ 532 #define PCIXM_COMMAND_MAX_READ 0x000c /* Maximum Burst Read Count */ 533 #define PCIXM_COMMAND_MAX_READ_512 0x0000 534 #define PCIXM_COMMAND_MAX_READ_1024 0x0004 535 #define PCIXM_COMMAND_MAX_READ_2048 0x0008 536 #define PCIXM_COMMAND_MAX_READ_4096 0x000c 537 #define PCIXM_COMMAND_MAX_SPLITS 0x0070 /* Maximum Split Transactions */ 538 #define PCIXM_COMMAND_MAX_SPLITS_1 0x0000 539 #define PCIXM_COMMAND_MAX_SPLITS_2 0x0010 540 #define PCIXM_COMMAND_MAX_SPLITS_3 0x0020 541 #define PCIXM_COMMAND_MAX_SPLITS_4 0x0030 542 #define PCIXM_COMMAND_MAX_SPLITS_8 0x0040 543 #define PCIXM_COMMAND_MAX_SPLITS_12 0x0050 544 #define PCIXM_COMMAND_MAX_SPLITS_16 0x0060 545 #define PCIXM_COMMAND_MAX_SPLITS_32 0x0070 546 #define PCIXM_COMMAND_VERSION 0x3000 547 #define PCIXR_STATUS 0x4 548 #define PCIXM_STATUS_DEVFN 0x000000FF 549 #define PCIXM_STATUS_BUS 0x0000FF00 550 #define PCIXM_STATUS_64BIT 0x00010000 551 #define PCIXM_STATUS_133CAP 0x00020000 552 #define PCIXM_STATUS_SC_DISCARDED 0x00040000 553 #define PCIXM_STATUS_UNEXP_SC 0x00080000 554 #define PCIXM_STATUS_COMPLEX_DEV 0x00100000 555 #define PCIXM_STATUS_MAX_READ 0x00600000 556 #define PCIXM_STATUS_MAX_READ_512 0x00000000 557 #define PCIXM_STATUS_MAX_READ_1024 0x00200000 558 #define PCIXM_STATUS_MAX_READ_2048 0x00400000 559 #define PCIXM_STATUS_MAX_READ_4096 0x00600000 560 #define PCIXM_STATUS_MAX_SPLITS 0x03800000 561 #define PCIXM_STATUS_MAX_SPLITS_1 0x00000000 562 #define PCIXM_STATUS_MAX_SPLITS_2 0x00800000 563 #define PCIXM_STATUS_MAX_SPLITS_3 0x01000000 564 #define PCIXM_STATUS_MAX_SPLITS_4 0x01800000 565 #define PCIXM_STATUS_MAX_SPLITS_8 0x02000000 566 #define PCIXM_STATUS_MAX_SPLITS_12 0x02800000 567 #define PCIXM_STATUS_MAX_SPLITS_16 0x03000000 568 #define PCIXM_STATUS_MAX_SPLITS_32 0x03800000 569 #define PCIXM_STATUS_MAX_CUM_READ 0x1C000000 570 #define PCIXM_STATUS_RCVD_SC_ERR 0x20000000 571 #define PCIXM_STATUS_266CAP 0x40000000 572 #define PCIXM_STATUS_533CAP 0x80000000 573 574 /* For header type 1 devices (PCI-X bridges) */ 575 #define PCIXR_SEC_STATUS 0x2 576 #define PCIXM_SEC_STATUS_64BIT 0x0001 577 #define PCIXM_SEC_STATUS_133CAP 0x0002 578 #define PCIXM_SEC_STATUS_SC_DISC 0x0004 579 #define PCIXM_SEC_STATUS_UNEXP_SC 0x0008 580 #define PCIXM_SEC_STATUS_SC_OVERRUN 0x0010 581 #define PCIXM_SEC_STATUS_SR_DELAYED 0x0020 582 #define PCIXM_SEC_STATUS_BUS_MODE 0x03c0 583 #define PCIXM_SEC_STATUS_VERSION 0x3000 584 #define PCIXM_SEC_STATUS_266CAP 0x4000 585 #define PCIXM_SEC_STATUS_533CAP 0x8000 586 #define PCIXR_BRIDGE_STATUS 0x4 587 #define PCIXM_BRIDGE_STATUS_DEVFN 0x000000FF 588 #define PCIXM_BRIDGE_STATUS_BUS 0x0000FF00 589 #define PCIXM_BRIDGE_STATUS_64BIT 0x00010000 590 #define PCIXM_BRIDGE_STATUS_133CAP 0x00020000 591 #define PCIXM_BRIDGE_STATUS_SC_DISCARDED 0x00040000 592 #define PCIXM_BRIDGE_STATUS_UNEXP_SC 0x00080000 593 #define PCIXM_BRIDGE_STATUS_SC_OVERRUN 0x00100000 594 #define PCIXM_BRIDGE_STATUS_SR_DELAYED 0x00200000 595 #define PCIXM_BRIDGE_STATUS_DEVID_MSGCAP 0x20000000 596 #define PCIXM_BRIDGE_STATUS_266CAP 0x40000000 597 #define PCIXM_BRIDGE_STATUS_533CAP 0x80000000 598 599 /* HT (HyperTransport) Capability definitions */ 600 #define PCIR_HT_COMMAND 0x2 601 #define PCIM_HTCMD_CAP_MASK 0xf800 /* Capability type. */ 602 #define PCIM_HTCAP_SLAVE 0x0000 /* 000xx */ 603 #define PCIM_HTCAP_HOST 0x2000 /* 001xx */ 604 #define PCIM_HTCAP_SWITCH 0x4000 /* 01000 */ 605 #define PCIM_HTCAP_INTERRUPT 0x8000 /* 10000 */ 606 #define PCIM_HTCAP_REVISION_ID 0x8800 /* 10001 */ 607 #define PCIM_HTCAP_UNITID_CLUMPING 0x9000 /* 10010 */ 608 #define PCIM_HTCAP_EXT_CONFIG_SPACE 0x9800 /* 10011 */ 609 #define PCIM_HTCAP_ADDRESS_MAPPING 0xa000 /* 10100 */ 610 #define PCIM_HTCAP_MSI_MAPPING 0xa800 /* 10101 */ 611 #define PCIM_HTCAP_DIRECT_ROUTE 0xb000 /* 10110 */ 612 #define PCIM_HTCAP_VCSET 0xb800 /* 10111 */ 613 #define PCIM_HTCAP_RETRY_MODE 0xc000 /* 11000 */ 614 #define PCIM_HTCAP_X86_ENCODING 0xc800 /* 11001 */ 615 #define PCIM_HTCAP_GEN3 0xd000 /* 11010 */ 616 #define PCIM_HTCAP_FLE 0xd800 /* 11011 */ 617 #define PCIM_HTCAP_PM 0xe000 /* 11100 */ 618 #define PCIM_HTCAP_HIGH_NODE_COUNT 0xe800 /* 11101 */ 619 620 /* HT MSI Mapping Capability definitions. */ 621 #define PCIM_HTCMD_MSI_ENABLE 0x0001 622 #define PCIM_HTCMD_MSI_FIXED 0x0002 623 #define PCIR_HTMSI_ADDRESS_LO 0x4 624 #define PCIR_HTMSI_ADDRESS_HI 0x8 625 626 /* PCI Vendor capability definitions */ 627 #define PCIR_VENDOR_LENGTH 0x2 628 #define PCIR_VENDOR_DATA 0x3 629 630 /* PCI EHCI Debug Port definitions */ 631 #define PCIR_DEBUG_PORT 0x2 632 #define PCIM_DEBUG_PORT_OFFSET 0x1FFF 633 #define PCIM_DEBUG_PORT_BAR 0xe000 634 635 /* PCI-PCI Bridge Subvendor definitions */ 636 #define PCIR_SUBVENDCAP_ID 0x4 637 638 /* PCI Express definitions */ 639 #define PCIER_FLAGS 0x2 640 #define PCIEM_FLAGS_VERSION 0x000F 641 #define PCIEM_FLAGS_TYPE 0x00F0 642 #define PCIEM_TYPE_ENDPOINT 0x0000 643 #define PCIEM_TYPE_LEGACY_ENDPOINT 0x0010 644 #define PCIEM_TYPE_ROOT_PORT 0x0040 645 #define PCIEM_TYPE_UPSTREAM_PORT 0x0050 646 #define PCIEM_TYPE_DOWNSTREAM_PORT 0x0060 647 #define PCIEM_TYPE_PCI_BRIDGE 0x0070 648 #define PCIEM_TYPE_PCIE_BRIDGE 0x0080 649 #define PCIEM_TYPE_ROOT_INT_EP 0x0090 650 #define PCIEM_TYPE_ROOT_EC 0x00a0 651 #define PCIEM_FLAGS_SLOT 0x0100 652 #define PCIEM_FLAGS_IRQ 0x3e00 653 #define PCIER_DEVICE_CAP 0x4 654 #define PCIEM_CAP_MAX_PAYLOAD 0x00000007 655 #define PCIEM_CAP_PHANTHOM_FUNCS 0x00000018 656 #define PCIEM_CAP_EXT_TAG_FIELD 0x00000020 657 #define PCIEM_CAP_L0S_LATENCY 0x000001c0 658 #define PCIEM_CAP_L1_LATENCY 0x00000e00 659 #define PCIEM_CAP_ROLE_ERR_RPT 0x00008000 660 #define PCIEM_CAP_SLOT_PWR_LIM_VAL 0x03fc0000 661 #define PCIEM_CAP_SLOT_PWR_LIM_SCALE 0x0c000000 662 #define PCIEM_CAP_FLR 0x10000000 663 #define PCIER_DEVICE_CTL 0x8 664 #define PCIEM_CTL_COR_ENABLE 0x0001 665 #define PCIEM_CTL_NFER_ENABLE 0x0002 666 #define PCIEM_CTL_FER_ENABLE 0x0004 667 #define PCIEM_CTL_URR_ENABLE 0x0008 668 #define PCIEM_CTL_RELAXED_ORD_ENABLE 0x0010 669 #define PCIEM_CTL_MAX_PAYLOAD 0x00e0 670 #define PCIEM_CTL_EXT_TAG_FIELD 0x0100 671 #define PCIEM_CTL_PHANTHOM_FUNCS 0x0200 672 #define PCIEM_CTL_AUX_POWER_PM 0x0400 673 #define PCIEM_CTL_NOSNOOP_ENABLE 0x0800 674 #define PCIEM_CTL_MAX_READ_REQUEST 0x7000 675 #define PCIEM_CTL_BRDG_CFG_RETRY 0x8000 /* PCI-E - PCI/PCI-X bridges */ 676 #define PCIEM_CTL_INITIATE_FLR 0x8000 /* FLR capable endpoints */ 677 #define PCIER_DEVICE_STA 0xa 678 #define PCIEM_STA_CORRECTABLE_ERROR 0x0001 679 #define PCIEM_STA_NON_FATAL_ERROR 0x0002 680 #define PCIEM_STA_FATAL_ERROR 0x0004 681 #define PCIEM_STA_UNSUPPORTED_REQ 0x0008 682 #define PCIEM_STA_AUX_POWER 0x0010 683 #define PCIEM_STA_TRANSACTION_PND 0x0020 684 #define PCIER_LINK_CAP 0xc 685 #define PCIEM_LINK_CAP_MAX_SPEED 0x0000000f 686 #define PCIEM_LINK_CAP_MAX_WIDTH 0x000003f0 687 #define PCIEM_LINK_CAP_ASPM 0x00000c00 688 #define PCIEM_LINK_CAP_L0S_EXIT 0x00007000 689 #define PCIEM_LINK_CAP_L1_EXIT 0x00038000 690 #define PCIEM_LINK_CAP_CLOCK_PM 0x00040000 691 #define PCIEM_LINK_CAP_SURPRISE_DOWN 0x00080000 692 #define PCIEM_LINK_CAP_DL_ACTIVE 0x00100000 693 #define PCIEM_LINK_CAP_LINK_BW_NOTIFY 0x00200000 694 #define PCIEM_LINK_CAP_ASPM_COMPLIANCE 0x00400000 695 #define PCIEM_LINK_CAP_PORT 0xff000000 696 #define PCIER_LINK_CTL 0x10 697 #define PCIEM_LINK_CTL_ASPMC_DIS 0x0000 698 #define PCIEM_LINK_CTL_ASPMC_L0S 0x0001 699 #define PCIEM_LINK_CTL_ASPMC_L1 0x0002 700 #define PCIEM_LINK_CTL_ASPMC 0x0003 701 #define PCIEM_LINK_CTL_RCB 0x0008 702 #define PCIEM_LINK_CTL_LINK_DIS 0x0010 703 #define PCIEM_LINK_CTL_RETRAIN_LINK 0x0020 704 #define PCIEM_LINK_CTL_COMMON_CLOCK 0x0040 705 #define PCIEM_LINK_CTL_EXTENDED_SYNC 0x0080 706 #define PCIEM_LINK_CTL_ECPM 0x0100 707 #define PCIEM_LINK_CTL_HAWD 0x0200 708 #define PCIEM_LINK_CTL_LBMIE 0x0400 709 #define PCIEM_LINK_CTL_LABIE 0x0800 710 #define PCIER_LINK_STA 0x12 711 #define PCIEM_LINK_STA_SPEED 0x000f 712 #define PCIEM_LINK_STA_WIDTH 0x03f0 713 #define PCIEM_LINK_STA_TRAINING_ERROR 0x0400 714 #define PCIEM_LINK_STA_TRAINING 0x0800 715 #define PCIEM_LINK_STA_SLOT_CLOCK 0x1000 716 #define PCIEM_LINK_STA_DL_ACTIVE 0x2000 717 #define PCIEM_LINK_STA_LINK_BW_MGMT 0x4000 718 #define PCIEM_LINK_STA_LINK_AUTO_BW 0x8000 719 #define PCIER_SLOT_CAP 0x14 720 #define PCIEM_SLOT_CAP_APB 0x00000001 721 #define PCIEM_SLOT_CAP_PCP 0x00000002 722 #define PCIEM_SLOT_CAP_MRLSP 0x00000004 723 #define PCIEM_SLOT_CAP_AIP 0x00000008 724 #define PCIEM_SLOT_CAP_PIP 0x00000010 725 #define PCIEM_SLOT_CAP_HPS 0x00000020 726 #define PCIEM_SLOT_CAP_HPC 0x00000040 727 #define PCIEM_SLOT_CAP_SPLV 0x00007f80 728 #define PCIEM_SLOT_CAP_SPLS 0x00018000 729 #define PCIEM_SLOT_CAP_EIP 0x00020000 730 #define PCIEM_SLOT_CAP_NCCS 0x00040000 731 #define PCIEM_SLOT_CAP_PSN 0xfff80000 732 #define PCIER_SLOT_CTL 0x18 733 #define PCIEM_SLOT_CTL_ABPE 0x0001 734 #define PCIEM_SLOT_CTL_PFDE 0x0002 735 #define PCIEM_SLOT_CTL_MRLSCE 0x0004 736 #define PCIEM_SLOT_CTL_PDCE 0x0008 737 #define PCIEM_SLOT_CTL_CCIE 0x0010 738 #define PCIEM_SLOT_CTL_HPIE 0x0020 739 #define PCIEM_SLOT_CTL_AIC 0x00c0 740 #define PCIEM_SLOT_CTL_PIC 0x0300 741 #define PCIEM_SLOT_CTL_PCC 0x0400 742 #define PCIEM_SLOT_CTL_EIC 0x0800 743 #define PCIEM_SLOT_CTL_DLLSCE 0x1000 744 #define PCIER_SLOT_STA 0x1a 745 #define PCIEM_SLOT_STA_ABP 0x0001 746 #define PCIEM_SLOT_STA_PFD 0x0002 747 #define PCIEM_SLOT_STA_MRLSC 0x0004 748 #define PCIEM_SLOT_STA_PDC 0x0008 749 #define PCIEM_SLOT_STA_CC 0x0010 750 #define PCIEM_SLOT_STA_MRLSS 0x0020 751 #define PCIEM_SLOT_STA_PDS 0x0040 752 #define PCIEM_SLOT_STA_EIS 0x0080 753 #define PCIEM_SLOT_STA_DLLSC 0x0100 754 #define PCIER_ROOT_CTL 0x1c 755 #define PCIER_ROOT_CAP 0x1e 756 #define PCIER_ROOT_STA 0x20 757 #define PCIER_DEVICE_CAP2 0x24 758 #define PCIER_DEVICE_CTL2 0x28 759 #define PCIEM_CTL2_COMP_TIMEOUT_VAL 0x000f 760 #define PCIEM_CTL2_COMP_TIMEOUT_DIS 0x0010 761 #define PCIEM_CTL2_ARI 0x0020 762 #define PCIEM_CTL2_ATOMIC_REQ_ENABLE 0x0040 763 #define PCIEM_CTL2_ATOMIC_EGR_BLOCK 0x0080 764 #define PCIEM_CTL2_ID_ORDERED_REQ_EN 0x0100 765 #define PCIEM_CTL2_ID_ORDERED_CMP_EN 0x0200 766 #define PCIEM_CTL2_LTR_ENABLE 0x0400 767 #define PCIEM_CTL2_OBFF 0x6000 768 #define PCIEM_OBFF_DISABLE 0x0000 769 #define PCIEM_OBFF_MSGA_ENABLE 0x2000 770 #define PCIEM_OBFF_MSGB_ENABLE 0x4000 771 #define PCIEM_OBFF_WAKE_ENABLE 0x6000 772 #define PCIEM_CTL2_END2END_TLP 0x8000 773 #define PCIER_DEVICE_STA2 0x2a 774 #define PCIER_LINK_CAP2 0x2c 775 #define PCIER_LINK_CTL2 0x30 776 #define PCIER_LINK_STA2 0x32 777 #define PCIER_SLOT_CAP2 0x34 778 #define PCIER_SLOT_CTL2 0x38 779 #define PCIER_SLOT_STA2 0x3a 780 781 /* Old compatibility definitions for PCI Express registers */ 782 #define PCIR_EXPRESS_FLAGS PCIER_FLAGS 783 #define PCIM_EXP_FLAGS_VERSION PCIEM_FLAGS_VERSION 784 #define PCIM_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE 785 #define PCIM_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT 786 #define PCIM_EXP_TYPE_LEGACY_ENDPOINT PCIEM_TYPE_LEGACY_ENDPOINT 787 #define PCIM_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT 788 #define PCIM_EXP_TYPE_UPSTREAM_PORT PCIEM_TYPE_UPSTREAM_PORT 789 #define PCIM_EXP_TYPE_DOWNSTREAM_PORT PCIEM_TYPE_DOWNSTREAM_PORT 790 #define PCIM_EXP_TYPE_PCI_BRIDGE PCIEM_TYPE_PCI_BRIDGE 791 #define PCIM_EXP_TYPE_PCIE_BRIDGE PCIEM_TYPE_PCIE_BRIDGE 792 #define PCIM_EXP_TYPE_ROOT_INT_EP PCIEM_TYPE_ROOT_INT_EP 793 #define PCIM_EXP_TYPE_ROOT_EC PCIEM_TYPE_ROOT_EC 794 #define PCIM_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT 795 #define PCIM_EXP_FLAGS_IRQ PCIEM_FLAGS_IRQ 796 #define PCIR_EXPRESS_DEVICE_CAP PCIER_DEVICE_CAP 797 #define PCIM_EXP_CAP_MAX_PAYLOAD PCIEM_CAP_MAX_PAYLOAD 798 #define PCIM_EXP_CAP_PHANTHOM_FUNCS PCIEM_CAP_PHANTHOM_FUNCS 799 #define PCIM_EXP_CAP_EXT_TAG_FIELD PCIEM_CAP_EXT_TAG_FIELD 800 #define PCIM_EXP_CAP_L0S_LATENCY PCIEM_CAP_L0S_LATENCY 801 #define PCIM_EXP_CAP_L1_LATENCY PCIEM_CAP_L1_LATENCY 802 #define PCIM_EXP_CAP_ROLE_ERR_RPT PCIEM_CAP_ROLE_ERR_RPT 803 #define PCIM_EXP_CAP_SLOT_PWR_LIM_VAL PCIEM_CAP_SLOT_PWR_LIM_VAL 804 #define PCIM_EXP_CAP_SLOT_PWR_LIM_SCALE PCIEM_CAP_SLOT_PWR_LIM_SCALE 805 #define PCIM_EXP_CAP_FLR PCIEM_CAP_FLR 806 #define PCIR_EXPRESS_DEVICE_CTL PCIER_DEVICE_CTL 807 #define PCIM_EXP_CTL_COR_ENABLE PCIEM_CTL_COR_ENABLE 808 #define PCIM_EXP_CTL_NFER_ENABLE PCIEM_CTL_NFER_ENABLE 809 #define PCIM_EXP_CTL_FER_ENABLE PCIEM_CTL_FER_ENABLE 810 #define PCIM_EXP_CTL_URR_ENABLE PCIEM_CTL_URR_ENABLE 811 #define PCIM_EXP_CTL_RELAXED_ORD_ENABLE PCIEM_CTL_RELAXED_ORD_ENABLE 812 #define PCIM_EXP_CTL_MAX_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 813 #define PCIM_EXP_CTL_EXT_TAG_FIELD PCIEM_CTL_EXT_TAG_FIELD 814 #define PCIM_EXP_CTL_PHANTHOM_FUNCS PCIEM_CTL_PHANTHOM_FUNCS 815 #define PCIM_EXP_CTL_AUX_POWER_PM PCIEM_CTL_AUX_POWER_PM 816 #define PCIM_EXP_CTL_NOSNOOP_ENABLE PCIEM_CTL_NOSNOOP_ENABLE 817 #define PCIM_EXP_CTL_MAX_READ_REQUEST PCIEM_CTL_MAX_READ_REQUEST 818 #define PCIM_EXP_CTL_BRDG_CFG_RETRY PCIEM_CTL_BRDG_CFG_RETRY 819 #define PCIM_EXP_CTL_INITIATE_FLR PCIEM_CTL_INITIATE_FLR 820 #define PCIR_EXPRESS_DEVICE_STA PCIER_DEVICE_STA 821 #define PCIM_EXP_STA_CORRECTABLE_ERROR PCIEM_STA_CORRECTABLE_ERROR 822 #define PCIM_EXP_STA_NON_FATAL_ERROR PCIEM_STA_NON_FATAL_ERROR 823 #define PCIM_EXP_STA_FATAL_ERROR PCIEM_STA_FATAL_ERROR 824 #define PCIM_EXP_STA_UNSUPPORTED_REQ PCIEM_STA_UNSUPPORTED_REQ 825 #define PCIM_EXP_STA_AUX_POWER PCIEM_STA_AUX_POWER 826 #define PCIM_EXP_STA_TRANSACTION_PND PCIEM_STA_TRANSACTION_PND 827 #define PCIR_EXPRESS_LINK_CAP PCIER_LINK_CAP 828 #define PCIM_LINK_CAP_MAX_SPEED PCIEM_LINK_CAP_MAX_SPEED 829 #define PCIM_LINK_CAP_MAX_WIDTH PCIEM_LINK_CAP_MAX_WIDTH 830 #define PCIM_LINK_CAP_ASPM PCIEM_LINK_CAP_ASPM 831 #define PCIM_LINK_CAP_L0S_EXIT PCIEM_LINK_CAP_L0S_EXIT 832 #define PCIM_LINK_CAP_L1_EXIT PCIEM_LINK_CAP_L1_EXIT 833 #define PCIM_LINK_CAP_CLOCK_PM PCIEM_LINK_CAP_CLOCK_PM 834 #define PCIM_LINK_CAP_SURPRISE_DOWN PCIEM_LINK_CAP_SURPRISE_DOWN 835 #define PCIM_LINK_CAP_DL_ACTIVE PCIEM_LINK_CAP_DL_ACTIVE 836 #define PCIM_LINK_CAP_LINK_BW_NOTIFY PCIEM_LINK_CAP_LINK_BW_NOTIFY 837 #define PCIM_LINK_CAP_ASPM_COMPLIANCE PCIEM_LINK_CAP_ASPM_COMPLIANCE 838 #define PCIM_LINK_CAP_PORT PCIEM_LINK_CAP_PORT 839 #define PCIR_EXPRESS_LINK_CTL PCIER_LINK_CTL 840 #define PCIM_EXP_LINK_CTL_ASPMC_DIS PCIEM_LINK_CTL_ASPMC_DIS 841 #define PCIM_EXP_LINK_CTL_ASPMC_L0S PCIEM_LINK_CTL_ASPMC_L0S 842 #define PCIM_EXP_LINK_CTL_ASPMC_L1 PCIEM_LINK_CTL_ASPMC_L1 843 #define PCIM_EXP_LINK_CTL_ASPMC PCIEM_LINK_CTL_ASPMC 844 #define PCIM_EXP_LINK_CTL_RCB PCIEM_LINK_CTL_RCB 845 #define PCIM_EXP_LINK_CTL_LINK_DIS PCIEM_LINK_CTL_LINK_DIS 846 #define PCIM_EXP_LINK_CTL_RETRAIN_LINK PCIEM_LINK_CTL_RETRAIN_LINK 847 #define PCIM_EXP_LINK_CTL_COMMON_CLOCK PCIEM_LINK_CTL_COMMON_CLOCK 848 #define PCIM_EXP_LINK_CTL_EXTENDED_SYNC PCIEM_LINK_CTL_EXTENDED_SYNC 849 #define PCIM_EXP_LINK_CTL_ECPM PCIEM_LINK_CTL_ECPM 850 #define PCIM_EXP_LINK_CTL_HAWD PCIEM_LINK_CTL_HAWD 851 #define PCIM_EXP_LINK_CTL_LBMIE PCIEM_LINK_CTL_LBMIE 852 #define PCIM_EXP_LINK_CTL_LABIE PCIEM_LINK_CTL_LABIE 853 #define PCIR_EXPRESS_LINK_STA PCIER_LINK_STA 854 #define PCIM_LINK_STA_SPEED PCIEM_LINK_STA_SPEED 855 #define PCIM_LINK_STA_WIDTH PCIEM_LINK_STA_WIDTH 856 #define PCIM_LINK_STA_TRAINING_ERROR PCIEM_LINK_STA_TRAINING_ERROR 857 #define PCIM_LINK_STA_TRAINING PCIEM_LINK_STA_TRAINING 858 #define PCIM_LINK_STA_SLOT_CLOCK PCIEM_LINK_STA_SLOT_CLOCK 859 #define PCIM_LINK_STA_DL_ACTIVE PCIEM_LINK_STA_DL_ACTIVE 860 #define PCIM_LINK_STA_LINK_BW_MGMT PCIEM_LINK_STA_LINK_BW_MGMT 861 #define PCIM_LINK_STA_LINK_AUTO_BW PCIEM_LINK_STA_LINK_AUTO_BW 862 #define PCIR_EXPRESS_SLOT_CAP PCIER_SLOT_CAP 863 #define PCIR_EXPRESS_SLOT_CTL PCIER_SLOT_CTL 864 #define PCIR_EXPRESS_SLOT_STA PCIER_SLOT_STA 865 #define PCIR_EXPRESS_ROOT_CTL PCIER_ROOT_CTL 866 #define PCIR_EXPRESS_ROOT_CAP PCIER_ROOT_CAP 867 #define PCIR_EXPRESS_ROOT_STA PCIER_ROOT_STA 868 #define PCIR_EXPRESS_DEVICE_CAP2 PCIER_DEVICE_CAP2 869 #define PCIR_EXPRESS_DEVICE_CTL2 PCIER_DEVICE_CTL2 870 #define PCIM_EXP_CTL2_COMP_TIMEOUT_VAL PCIEM_CTL2_COMP_TIMEOUT_VAL 871 #define PCIM_EXP_CTL2_COMP_TIMEOUT_DIS PCIEM_CTL2_COMP_TIMEOUT_DIS 872 #define PCIM_EXP_CTL2_ARI PCIEM_CTL2_ARI 873 #define PCIM_EXP_CTL2_ATOMIC_REQ_ENABLE PCIEM_CTL2_ATOMIC_REQ_ENABLE 874 #define PCIM_EXP_CTL2_ATOMIC_EGR_BLOCK PCIEM_CTL2_ATOMIC_EGR_BLOCK 875 #define PCIM_EXP_CTL2_ID_ORDERED_REQ_EN PCIEM_CTL2_ID_ORDERED_REQ_EN 876 #define PCIM_EXP_CTL2_ID_ORDERED_CMP_EN PCIEM_CTL2_ID_ORDERED_CMP_EN 877 #define PCIM_EXP_CTL2_LTR_ENABLE PCIEM_CTL2_LTR_ENABLE 878 #define PCIM_EXP_CTL2_OBFF PCIEM_CTL2_OBFF 879 #define PCIM_EXP_OBFF_DISABLE PCIEM_OBFF_DISABLE 880 #define PCIM_EXP_OBFF_MSGA_ENABLE PCIEM_OBFF_MSGA_ENABLE 881 #define PCIM_EXP_OBFF_MSGB_ENABLE PCIEM_OBFF_MSGB_ENABLE 882 #define PCIM_EXP_OBFF_WAKE_ENABLE PCIEM_OBFF_WAKE_ENABLE 883 #define PCIM_EXP_CTL2_END2END_TLP PCIEM_CTL2_END2END_TLP 884 #define PCIR_EXPRESS_DEVICE_STA2 PCIER_DEVICE_STA2 885 #define PCIR_EXPRESS_LINK_CAP2 PCIER_LINK_CAP2 886 #define PCIR_EXPRESS_LINK_CTL2 PCIER_LINK_CTL2 887 #define PCIR_EXPRESS_LINK_STA2 PCIER_LINK_STA2 888 #define PCIR_EXPRESS_SLOT_CAP2 PCIER_SLOT_CAP2 889 #define PCIR_EXPRESS_SLOT_CTL2 PCIER_SLOT_CTL2 890 #define PCIR_EXPRESS_SLOT_STA2 PCIER_SLOT_STA2 891 892 /* MSI-X definitions */ 893 #define PCIR_MSIX_CTRL 0x2 894 #define PCIM_MSIXCTRL_MSIX_ENABLE 0x8000 895 #define PCIM_MSIXCTRL_FUNCTION_MASK 0x4000 896 #define PCIM_MSIXCTRL_TABLE_SIZE 0x07FF 897 #define PCIR_MSIX_TABLE 0x4 898 #define PCIR_MSIX_PBA 0x8 899 #define PCIM_MSIX_BIR_MASK 0x7 900 #define PCIM_MSIX_BIR_BAR_10 0 901 #define PCIM_MSIX_BIR_BAR_14 1 902 #define PCIM_MSIX_BIR_BAR_18 2 903 #define PCIM_MSIX_BIR_BAR_1C 3 904 #define PCIM_MSIX_BIR_BAR_20 4 905 #define PCIM_MSIX_BIR_BAR_24 5 906 #define PCIM_MSIX_VCTRL_MASK 0x1 907 908 /* PCI Advanced Features definitions */ 909 #define PCIR_PCIAF_CAP 0x3 910 #define PCIM_PCIAFCAP_TP 0x01 911 #define PCIM_PCIAFCAP_FLR 0x02 912 #define PCIR_PCIAF_CTRL 0x4 913 #define PCIR_PCIAFCTRL_FLR 0x01 914 #define PCIR_PCIAF_STATUS 0x5 915 #define PCIR_PCIAFSTATUS_TP 0x01 916 917 /* Advanced Error Reporting */ 918 #define PCIR_AER_UC_STATUS 0x04 919 #define PCIM_AER_UC_TRAINING_ERROR 0x00000001 920 #define PCIM_AER_UC_DL_PROTOCOL_ERROR 0x00000010 921 #define PCIM_AER_UC_SURPRISE_LINK_DOWN 0x00000020 922 #define PCIM_AER_UC_POISONED_TLP 0x00001000 923 #define PCIM_AER_UC_FC_PROTOCOL_ERROR 0x00002000 924 #define PCIM_AER_UC_COMPLETION_TIMEOUT 0x00004000 925 #define PCIM_AER_UC_COMPLETER_ABORT 0x00008000 926 #define PCIM_AER_UC_UNEXPECTED_COMPLETION 0x00010000 927 #define PCIM_AER_UC_RECEIVER_OVERFLOW 0x00020000 928 #define PCIM_AER_UC_MALFORMED_TLP 0x00040000 929 #define PCIM_AER_UC_ECRC_ERROR 0x00080000 930 #define PCIM_AER_UC_UNSUPPORTED_REQUEST 0x00100000 931 #define PCIM_AER_UC_ACS_VIOLATION 0x00200000 932 #define PCIM_AER_UC_INTERNAL_ERROR 0x00400000 933 #define PCIM_AER_UC_MC_BLOCKED_TLP 0x00800000 934 #define PCIM_AER_UC_ATOMIC_EGRESS_BLK 0x01000000 935 #define PCIM_AER_UC_TLP_PREFIX_BLOCKED 0x02000000 936 #define PCIR_AER_UC_MASK 0x08 /* Shares bits with UC_STATUS */ 937 #define PCIR_AER_UC_SEVERITY 0x0c /* Shares bits with UC_STATUS */ 938 #define PCIR_AER_COR_STATUS 0x10 939 #define PCIM_AER_COR_RECEIVER_ERROR 0x00000001 940 #define PCIM_AER_COR_BAD_TLP 0x00000040 941 #define PCIM_AER_COR_BAD_DLLP 0x00000080 942 #define PCIM_AER_COR_REPLAY_ROLLOVER 0x00000100 943 #define PCIM_AER_COR_REPLAY_TIMEOUT 0x00001000 944 #define PCIM_AER_COR_ADVISORY_NF_ERROR 0x00002000 945 #define PCIM_AER_COR_INTERNAL_ERROR 0x00004000 946 #define PCIM_AER_COR_HEADER_LOG_OVFLOW 0x00008000 947 #define PCIR_AER_COR_MASK 0x14 /* Shares bits with COR_STATUS */ 948 #define PCIR_AER_CAP_CONTROL 0x18 949 #define PCIM_AER_FIRST_ERROR_PTR 0x0000001f 950 #define PCIM_AER_ECRC_GEN_CAPABLE 0x00000020 951 #define PCIM_AER_ECRC_GEN_ENABLE 0x00000040 952 #define PCIM_AER_ECRC_CHECK_CAPABLE 0x00000080 953 #define PCIM_AER_ECRC_CHECK_ENABLE 0x00000100 954 #define PCIM_AER_MULT_HDR_CAPABLE 0x00000200 955 #define PCIM_AER_MULT_HDR_ENABLE 0x00000400 956 #define PCIM_AER_TLP_PREFIX_LOG_PRESENT 0x00000800 957 #define PCIR_AER_HEADER_LOG 0x1c 958 #define PCIR_AER_ROOTERR_CMD 0x2c /* Only for root complex ports */ 959 #define PCIM_AER_ROOTERR_COR_ENABLE 0x00000001 960 #define PCIM_AER_ROOTERR_NF_ENABLE 0x00000002 961 #define PCIM_AER_ROOTERR_F_ENABLE 0x00000004 962 #define PCIR_AER_ROOTERR_STATUS 0x30 /* Only for root complex ports */ 963 #define PCIM_AER_ROOTERR_COR_ERR 0x00000001 964 #define PCIM_AER_ROOTERR_MULTI_COR_ERR 0x00000002 965 #define PCIM_AER_ROOTERR_UC_ERR 0x00000004 966 #define PCIM_AER_ROOTERR_MULTI_UC_ERR 0x00000008 967 #define PCIM_AER_ROOTERR_FIRST_UC_FATAL 0x00000010 968 #define PCIM_AER_ROOTERR_NF_ERR 0x00000020 969 #define PCIM_AER_ROOTERR_F_ERR 0x00000040 970 #define PCIM_AER_ROOTERR_INT_MESSAGE 0xf8000000 971 #define PCIR_AER_COR_SOURCE_ID 0x34 /* Only for root complex ports */ 972 #define PCIR_AER_ERR_SOURCE_ID 0x36 /* Only for root complex ports */ 973 #define PCIR_AER_TLP_PREFIX_LOG 0x38 /* Only for TLP prefix functions */ 974 975 /* Virtual Channel definitions */ 976 #define PCIR_VC_CAP1 0x04 977 #define PCIM_VC_CAP1_EXT_COUNT 0x00000007 978 #define PCIM_VC_CAP1_LOWPRI_EXT_COUNT 0x00000070 979 #define PCIR_VC_CAP2 0x08 980 #define PCIR_VC_CONTROL 0x0C 981 #define PCIR_VC_STATUS 0x0E 982 #define PCIR_VC_RESOURCE_CAP(n) (0x10 + (n) * 0x0C) 983 #define PCIR_VC_RESOURCE_CTL(n) (0x14 + (n) * 0x0C) 984 #define PCIR_VC_RESOURCE_STA(n) (0x18 + (n) * 0x0C) 985 986 /* Serial Number definitions */ 987 #define PCIR_SERIAL_LOW 0x04 988 #define PCIR_SERIAL_HIGH 0x08 989