1 /* 2 * Copyright 2020, Jérôme Duval, jerome.duval@gmail.com. 3 * 4 * Distributed under the terms of the MIT License. 5 */ 6 #ifndef _PCH_THERMAL_H 7 #define _PCH_THERMAL_H 8 9 10 enum { /* ioctl op-codes */ 11 drvOpGetThermalType = B_DEVICE_OP_CODES_END + 10001, 12 }; 13 14 15 struct pch_thermal_type { 16 /* Required fields for thermal devices */ 17 uint32 critical_temp; 18 uint32 current_temp; 19 20 /* Optional HOT temp, S4 sleep threshold */ 21 uint32 hot_temp; 22 }; 23 24 // Registers 25 #define PCH_THERMAL_TEMP 0x00 26 #define PCH_THERMAL_TEMP_TSR_SHIFT 0 27 #define PCH_THERMAL_TEMP_TSR_MASK 0xff 28 #define PCH_THERMAL_TSC 0x04 29 #define PCH_THERMAL_TSC_CPDE (1 << 0) 30 #define PCH_THERMAL_TSC_PLDB (1 << 7) 31 #define PCH_THERMAL_TSS 0x06 32 #define PCH_THERMAL_TSS_SMIS (1 << 2) 33 #define PCH_THERMAL_TSS_GPES (1 << 3) 34 #define PCH_THERMAL_TSS_TSDSS (1 << 4) 35 #define PCH_THERMAL_TSEL 0x08 36 #define PCH_THERMAL_TSEL_ETS (1 << 0) 37 #define PCH_THERMAL_TSEL_PLDB (1 << 7) 38 #define PCH_THERMAL_TSREL 0x0a 39 #define PCH_THERMAL_TSREL_ESTR (1 << 0) 40 #define PCH_THERMAL_TSREL_PLDB (1 << 7) 41 #define PCH_THERMAL_TSMIC 0x0c 42 #define PCH_THERMAL_TSMIC_ATST (1 << 0) 43 #define PCH_THERMAL_TSMIC_PLDB (1 << 7) 44 #define PCH_THERMAL_CTT 0x10 45 #define PCH_THERMAL_CTT_CTRIP_SHIFT 0 46 #define PCH_THERMAL_CTT_CTRIP_MASK 0x1ff 47 #define PCH_THERMAL_TAHV 0x14 48 #define PCH_THERMAL_TAHV_AH_SHIFT 0 49 #define PCH_THERMAL_TAHV_AH_MASK 0x1ff 50 #define PCH_THERMAL_TALV 0x18 51 #define PCH_THERMAL_TALV_AL_SHIFT 0 52 #define PCH_THERMAL_TALV_AL_MASK 0x1ff 53 #define PCH_THERMAL_TSPM 0x1c 54 #define PCH_THERMAL_TSPM_LTT_SHIFT 0 55 #define PCH_THERMAL_TSPM_LTT_MASK 0x1ff 56 #define PCH_THERMAL_TSPM_MAXTSST_SHIFT 9 57 #define PCH_THERMAL_TSPM_MAXTSST_MASK 0xf 58 #define PCH_THERMAL_TSPM_DTSSIC0 (1 << 13) 59 #define PCH_THERMAL_TSPM_DTSSS0EN (1 << 14) 60 #define PCH_THERMAL_TSPM_TSPMLOCK (1 << 15) 61 #define PCH_THERMAL_TL 0x40 62 #define PCH_THERMAL_TL_T0L_SHIFT 0 63 #define PCH_THERMAL_TL_T0L_MASK 0x1ff 64 #define PCH_THERMAL_TL_T1L_SHIFT 10 65 #define PCH_THERMAL_TL_T1L_MASK 0x1ff 66 #define PCH_THERMAL_TL_T2L_SHIFT 20 67 #define PCH_THERMAL_TL_T2L_MASK 0x1ff 68 #define PCH_THERMAL_TL_TTEN (1 << 29) 69 #define PCH_THERMAL_TL_TT13EN (1 << 30) 70 #define PCH_THERMAL_TL_TTL (1 << 31) 71 #define PCH_THERMAL_TL2 0x50 72 #define PCH_THERMAL_TL2_TL2LOCK_SHIFT 15 73 #define PCH_THERMAL_TL2_PCMTEN_SHIFT 16 74 #define PCH_THERMAL_PHL 0x60 75 #define PCH_THERMAL_PHL_PHLL_SHIFT 0 76 #define PCH_THERMAL_PHL_PHLL_MASK 0x1ff 77 #define PCH_THERMAL_PHL_PHLE (1 << 15) 78 #define PCH_THERMAL_PHLC 0x62 79 #define PCH_THERMAL_PHLC_PHLL (1 << 0) 80 #define PCH_THERMAL_TAS 0x80 81 #define PCH_THERMAL_TAS_ALHE (1 << 0) 82 #define PCH_THERMAL_TAS_AHLE (1 << 1) 83 #define PCH_THERMAL_TSPIEN 0x82 84 #define PCH_THERMAL_TSPIEN_ALHEN (1 << 0) 85 #define PCH_THERMAL_TSPIEN_AHLEN (1 << 1) 86 #define PCH_THERMAL_TSGPEN 0x84 87 #define PCH_THERMAL_TSGPEN_ALHEN (1 << 0) 88 #define PCH_THERMAL_TSGPEN_AHLEN (1 << 1) 89 #define PCH_THERMAL_TCFD 0xf0 90 #define PCH_THERMAL_TCFD_TCD (1 << 0) 91 92 93 #endif // _PCH_THERMAL_H 94 95