Home
last modified time | relevance | path

Searched refs:OUTREGP (Results 1 – 14 of 14) sorted by relevance

/haiku/src/add-ons/accelerants/radeon/
H A Ddpms.c68 OUTREGP( regs, RADEON_LVDS_GEN_CNTL, RADEON_LVDS_BLON, ~RADEON_LVDS_BLON ); in Radeon_SetDPMS_LVDS()
70 OUTREGP( regs, RADEON_LVDS_GEN_CNTL, RADEON_LVDS_ON, ~RADEON_LVDS_ON ); in Radeon_SetDPMS_LVDS()
84 OUTREGP( regs, RADEON_LVDS_GEN_CNTL, 0, ~(RADEON_LVDS_BLON | RADEON_LVDS_ON) ); in Radeon_SetDPMS_LVDS()
104 OUTREGP( regs, RADEON_FP_GEN_CNTL, RADEON_FP_FPON | RADEON_FP_TMDS_EN, in Radeon_SetDPMS_DVI()
110 OUTREGP( regs, RADEON_FP_GEN_CNTL, 0, ~RADEON_FP_FPON | RADEON_FP_TMDS_EN ); in Radeon_SetDPMS_DVI()
126 OUTREGP( regs, RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_BLANK_EN); in Radeon_SetDPMS_FP2()
127 OUTREGP( regs, RADEON_FP2_GEN_CNTL, RADEON_FP2_FPON, ~RADEON_FP2_FPON); in Radeon_SetDPMS_FP2()
129 OUTREGP( regs, RADEON_FP2_GEN_CNTL, RADEON_FP2_DV0_EN, ~RADEON_FP2_DV0_EN); in Radeon_SetDPMS_FP2()
135 OUTREGP( regs, RADEON_FP2_GEN_CNTL, RADEON_FP2_BLANK_EN, ~RADEON_FP2_BLANK_EN ); in Radeon_SetDPMS_FP2()
136 OUTREGP( regs, RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_FPON); in Radeon_SetDPMS_FP2()
[all …]
H A Dmonitor_routing.c426 OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, values->crtc2_gen_cntl, in Radeon_ProgramMonitorRouting()
450 OUTREGP( regs, RADEON_GPIOPAD_A, values->gpiopad_a, ~1 ); in Radeon_ProgramMonitorRouting()
468 OUTREGP( regs, RADEON_FP_GEN_CNTL, values->fp_gen_cntl, ~( in Radeon_ProgramMonitorRouting()
481 OUTREGP( regs, RADEON_FP2_GEN_CNTL, values->fp2_gen_cntl, in Radeon_ProgramMonitorRouting()
513 OUTREGP( regs, RADEON_CRTC_GEN_CNTL, crtc_gen_cntl, in Radeon_ProgramMonitorRouting()
530 OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl, in Radeon_ProgramMonitorRouting()
535 OUTREGP( regs, RADEON_CRTC_EXT_CNTL, values->crtc_ext_cntl, in Radeon_ProgramMonitorRouting()
H A Dcrtc.c27 OUTREGP( regs, RADEON_CRTC_GEN_CNTL, values->crtc_gen_cntl, in Radeon_ProgramCRTCRegisters()
38 OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, values->crtc_gen_cntl, in Radeon_ProgramCRTCRegisters()
H A Dflat_panel.c258 OUTREGP( regs, RADEON_FP_GEN_CNTL, values->fp_gen_cntl, RADEON_FP_SEL_CRTC2 ); in Radeon_ProgramFPRegisters()
262 OUTREGP( regs, RADEON_FP2_GEN_CNTL, values->fp2_gen_cntl, in Radeon_ProgramFPRegisters()
264 OUTREGP( regs, RADEON_FP2_GEN_CNTL, values->fp2_gen_cntl, in Radeon_ProgramFPRegisters()
H A Dmonitor_detection.c239 OUTREGP(regs, RADEON_GPIOPAD_EN, 1, ~1); in Radeon_DetectTVCRT_R300()
240 OUTREGP(regs, RADEON_GPIOPAD_MASK, 1, ~1); in Radeon_DetectTVCRT_R300()
241 OUTREGP(regs, RADEON_GPIOPAD_A, 1, ~1); in Radeon_DetectTVCRT_R300()
283 OUTREGP(regs, RADEON_GPIOPAD_A, old_radeon_gpiopad_a, ~1); in Radeon_DetectTVCRT_R300()
427 OUTREGP(regs, RADEON_GPIOPAD_EN, 1, ~1); in Radeon_DetectTV_R300()
428 OUTREGP(regs, RADEON_GPIOPAD_MASK, 1, ~1); in Radeon_DetectTV_R300()
429 OUTREGP(regs, RADEON_GPIOPAD_A, 0, ~1); in Radeon_DetectTV_R300()
493 OUTREGP(regs, RADEON_GPIOPAD_A, old_radeon_gpiopad_a, ~1); in Radeon_DetectTV_R300()
H A DSetDisplayMode.c93 OUTREGP( regs, RADEON_CRTC_GEN_CNTL, in Radeon_InitCommonRegs()
523 OUTREGP( ai->regs, RADEON_CRTC_EXT_CNTL, 0, ~RADEON_CRTC_DISPLAY_DIS ); in SET_DISPLAY_MODE()
H A Dpll.c477 OUTREGP( regs, RADEON_CLOCK_CNTL_INDEX, in Radeon_ProgramPLL()
/haiku/headers/private/graphics/radeon/
H A Dmmio.h22 #define OUTREGP( regs, addr, val, mask ) \ macro
/haiku/src/add-ons/kernel/drivers/graphics/radeon/
H A Dvip.c43 OUTREGP( regs, RADEON_VIPH_TIMEOUT_STAT, 0, in do_VIPRead()
57 OUTREGP( regs, RADEON_VIPH_TIMEOUT_STAT, RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS, in do_VIPRead()
72 OUTREGP( regs, RADEON_VIPH_TIMEOUT_STAT, RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS, in do_VIPRead()
H A DPCI_GART.c300 OUTREGP( regs, RADEON_BUS_CNTL, RADEON_BUS_MASTER_DIS, ~RADEON_BUS_MASTER_DIS ); in Radeon_CleanupPCIGART()
302 OUTREGP( regs, RADEON_AIC_CNTL, 0, ~RADEON_PCIGART_TRANSLATE_EN ); in Radeon_CleanupPCIGART()
H A DDMA.c39 OUTREGP( di->regs, RADEON_GEN_INT_CNTL, RADEON_VIDDMA_MASK, ~RADEON_VIDDMA_MASK ); in Radeon_InitDMA()
H A Dmem_controller.c159 OUTREGP( regs, RADEON_AIC_CNTL, RADEON_PCIGART_TRANSLATE_EN, in Radeon_InitMemController()
H A DCP_setup.c186 OUTREGP( di->regs, RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL, in Radeon_FlushPixelCache()
548 OUTREGP( di->regs, RADEON_BUS_CNTL, 0, ~RADEON_BUS_MASTER_DIS ); in Radeon_InitCP()
H A Dbios.c898 OUTREGP( regs, RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, in RADEON_GetAccessibleVRAM()