Searched refs:NV_IMAGE_BLIT (Results 1 – 3 of 3) sorted by relevance
210 ACCW(HT_HANDL_01, (0x80000000 | NV_IMAGE_BLIT)); /* 32bit handle */ in nv_acc_init()232 ACCW(HT_HANDL_01, (0x80000000 | NV_IMAGE_BLIT)); /* 32bit handle */ in nv_acc_init()1013 si->engine.fifo.handle[4] = NV_IMAGE_BLIT; in nv_acc_init()1319 !si->engine.fifo.ch_ptr[NV_IMAGE_BLIT] || in nv_acc_assert_fifo()1338 si->engine.fifo.handle[4] = NV_IMAGE_BLIT; in nv_acc_assert_fifo()1367 &(regs[(si->engine.fifo.ch_ptr[NV_IMAGE_BLIT]) >> 2]); in nv_acc_assert_fifo()
225 ACCW(HT_HANDL_01, (0x80000000 | NV_IMAGE_BLIT)); /* 32bit handle */ in nv_acc_init_dma()250 ACCW(HT_HANDL_01, (0x80000000 | NV_IMAGE_BLIT)); /* 32bit handle */ in nv_acc_init_dma()1031 si->engine.fifo.handle[4] = NV_IMAGE_BLIT; in nv_acc_init_dma()1603 !si->engine.fifo.ch_ptr[NV_IMAGE_BLIT] || in nv_acc_assert_fifo_dma()1623 si->engine.fifo.handle[4] = NV_IMAGE_BLIT; in nv_acc_assert_fifo_dma()1707 nv_acc_cmd_dma(NV_IMAGE_BLIT, NV_IMAGE_BLIT_SOURCEORG, 3); in SCREEN_TO_SCREEN_BLIT_DMA()
170 #define NV_IMAGE_BLIT 0x00000011 /* 2D */ macro