1 /*
2 * Copyright 2006-2016, Haiku, Inc. All Rights Reserved.
3 * Distributed under the terms of the MIT License.
4 *
5 * Authors:
6 * Axel Dörfler, axeld@pinc-software.de
7 * Alexander von Gluck, kallisti5@unixzen.com
8 */
9 #ifndef INTEL_EXTREME_H
10 #define INTEL_EXTREME_H
11
12
13 #include "lock.h"
14
15 #include <Accelerant.h>
16 #include <Drivers.h>
17 #include <PCI.h>
18
19 #include <edid.h>
20
21
22 #define VENDOR_ID_INTEL 0x8086
23
24 #define INTEL_FAMILY_MASK 0x00ff0000
25 #define INTEL_GROUP_MASK 0x00fffff0
26 #define INTEL_MODEL_MASK 0x00ffffff
27 #define INTEL_TYPE_MASK 0x0000000f
28
29 // families
30 #define INTEL_FAMILY_8xx 0x00020000 // Second Gen
31 #define INTEL_FAMILY_9xx 0x00040000 // Third Gen +
32 #define INTEL_FAMILY_SER5 0x00080000 // Intel5 Series
33 #define INTEL_FAMILY_SOC0 0x00200000 // Atom SOC
34 #define INTEL_FAMILY_LAKE 0x00400000 // Intel Lakes
35
36 // groups
37 #define INTEL_GROUP_83x (INTEL_FAMILY_8xx | 0x0010)
38 #define INTEL_GROUP_85x (INTEL_FAMILY_8xx | 0x0020)
39 #define INTEL_GROUP_91x (INTEL_FAMILY_9xx | 0x0010)
40 #define INTEL_GROUP_94x (INTEL_FAMILY_9xx | 0x0020)
41 #define INTEL_GROUP_96x (INTEL_FAMILY_9xx | 0x0040)
42 #define INTEL_GROUP_Gxx (INTEL_FAMILY_9xx | 0x0080)
43 #define INTEL_GROUP_G4x (INTEL_FAMILY_9xx | 0x0100)
44 #define INTEL_GROUP_PIN (INTEL_FAMILY_9xx | 0x0200) // PineView
45 #define INTEL_GROUP_ILK (INTEL_FAMILY_SER5 | 0x0010) // IronLake
46 #define INTEL_GROUP_SNB (INTEL_FAMILY_SER5 | 0x0020) // SandyBridge
47 #define INTEL_GROUP_IVB (INTEL_FAMILY_SER5 | 0x0040) // IvyBridge
48 #define INTEL_GROUP_HAS (INTEL_FAMILY_SER5 | 0x0080) // Haswell
49 #define INTEL_GROUP_VLV (INTEL_FAMILY_SOC0 | 0x0010) // ValleyView
50 #define INTEL_GROUP_CHV (INTEL_FAMILY_SOC0 | 0x0020) // CherryView
51 #define INTEL_GROUP_BDW (INTEL_FAMILY_SOC0 | 0x0040) // Broadwell
52 #define INTEL_GROUP_SKY (INTEL_FAMILY_LAKE | 0x0010) // SkyLake
53 #define INTEL_GROUP_KBY (INTEL_FAMILY_LAKE | 0x0020) // KabyLake
54 #define INTEL_GROUP_CFL (INTEL_FAMILY_LAKE | 0x0040) // CoffeeLake
55 #define INTEL_GROUP_CML (INTEL_FAMILY_LAKE | 0x0080) // CometLake
56 #define INTEL_GROUP_JSL (INTEL_FAMILY_LAKE | 0x0100) // JasperLake
57 #define INTEL_GROUP_TGL (INTEL_FAMILY_LAKE | 0x0200) // TigerLake
58 // models
59 #define INTEL_TYPE_SERVER 0x0004
60 #define INTEL_TYPE_MOBILE 0x0008
61 #define INTEL_MODEL_915 (INTEL_GROUP_91x)
62 #define INTEL_MODEL_915M (INTEL_GROUP_91x | INTEL_TYPE_MOBILE)
63 #define INTEL_MODEL_945 (INTEL_GROUP_94x)
64 #define INTEL_MODEL_945M (INTEL_GROUP_94x | INTEL_TYPE_MOBILE)
65 #define INTEL_MODEL_965 (INTEL_GROUP_96x)
66 #define INTEL_MODEL_965M (INTEL_GROUP_96x | INTEL_TYPE_MOBILE)
67 #define INTEL_MODEL_G33 (INTEL_GROUP_Gxx)
68 #define INTEL_MODEL_G45 (INTEL_GROUP_G4x)
69 #define INTEL_MODEL_GM45 (INTEL_GROUP_G4x | INTEL_TYPE_MOBILE)
70 #define INTEL_MODEL_PINE (INTEL_GROUP_PIN)
71 #define INTEL_MODEL_PINEM (INTEL_GROUP_PIN | INTEL_TYPE_MOBILE)
72 #define INTEL_MODEL_ILKG (INTEL_GROUP_ILK)
73 #define INTEL_MODEL_ILKGM (INTEL_GROUP_ILK | INTEL_TYPE_MOBILE)
74 #define INTEL_MODEL_SNBG (INTEL_GROUP_SNB)
75 #define INTEL_MODEL_SNBGM (INTEL_GROUP_SNB | INTEL_TYPE_MOBILE)
76 #define INTEL_MODEL_SNBGS (INTEL_GROUP_SNB | INTEL_TYPE_SERVER)
77 #define INTEL_MODEL_IVBG (INTEL_GROUP_IVB)
78 #define INTEL_MODEL_IVBGM (INTEL_GROUP_IVB | INTEL_TYPE_MOBILE)
79 #define INTEL_MODEL_IVBGS (INTEL_GROUP_IVB | INTEL_TYPE_SERVER)
80 #define INTEL_MODEL_HAS (INTEL_GROUP_HAS)
81 #define INTEL_MODEL_HASM (INTEL_GROUP_HAS | INTEL_TYPE_MOBILE)
82 #define INTEL_MODEL_VLV (INTEL_GROUP_VLV)
83 #define INTEL_MODEL_VLVM (INTEL_GROUP_VLV | INTEL_TYPE_MOBILE)
84 #define INTEL_MODEL_BDW (INTEL_GROUP_BDW)
85 #define INTEL_MODEL_BDWM (INTEL_GROUP_BDW | INTEL_TYPE_MOBILE)
86 #define INTEL_MODEL_BDWS (INTEL_GROUP_BDW | INTEL_TYPE_SERVER)
87 #define INTEL_MODEL_SKY (INTEL_GROUP_SKY)
88 #define INTEL_MODEL_SKYM (INTEL_GROUP_SKY | INTEL_TYPE_MOBILE)
89 #define INTEL_MODEL_SKYS (INTEL_GROUP_SKY | INTEL_TYPE_SERVER)
90 #define INTEL_MODEL_KBY (INTEL_GROUP_KBY)
91 #define INTEL_MODEL_KBYM (INTEL_GROUP_KBY | INTEL_TYPE_MOBILE)
92 #define INTEL_MODEL_CFL (INTEL_GROUP_CFL)
93 #define INTEL_MODEL_CFLM (INTEL_GROUP_CFL | INTEL_TYPE_MOBILE)
94 #define INTEL_MODEL_CML (INTEL_GROUP_CML)
95 #define INTEL_MODEL_CMLM (INTEL_GROUP_CML | INTEL_TYPE_MOBILE)
96 #define INTEL_MODEL_JSL (INTEL_GROUP_JSL)
97 #define INTEL_MODEL_JSLM (INTEL_GROUP_JSL | INTEL_TYPE_MOBILE)
98 #define INTEL_MODEL_TGLM (INTEL_GROUP_TGL | INTEL_TYPE_MOBILE)
99
100 #define INTEL_PCH_DEVICE_ID_MASK 0xff80
101 #define INTEL_PCH_IBX_DEVICE_ID 0x3b00
102 #define INTEL_PCH_CPT_DEVICE_ID 0x1c00
103 #define INTEL_PCH_PPT_DEVICE_ID 0x1e00
104 #define INTEL_PCH_LPT_DEVICE_ID 0x8c00
105 #define INTEL_PCH_LPT_LP_DEVICE_ID 0x9c00
106 #define INTEL_PCH_WPT_DEVICE_ID 0x8c80
107 #define INTEL_PCH_WPT_LP_DEVICE_ID 0x9c80
108 #define INTEL_PCH_SPT_DEVICE_ID 0xa100
109 #define INTEL_PCH_SPT_LP_DEVICE_ID 0x9d00
110 #define INTEL_PCH_KBP_DEVICE_ID 0xa280
111 #define INTEL_PCH_GMP_DEVICE_ID 0x3180
112 #define INTEL_PCH_CNP_DEVICE_ID 0xa300
113 #define INTEL_PCH_CNP_LP_DEVICE_ID 0x9d80
114 #define INTEL_PCH_CMP_DEVICE_ID 0x0280
115 #define INTEL_PCH_CMP2_DEVICE_ID 0x0680
116 #define INTEL_PCH_CMP_V_DEVICE_ID 0xa380
117 #define INTEL_PCH_ICP_DEVICE_ID 0x3480
118 #define INTEL_PCH_ICP2_DEVICE_ID 0x3880
119 #define INTEL_PCH_MCC_DEVICE_ID 0x4b00
120 #define INTEL_PCH_TGP_DEVICE_ID 0xa080
121 #define INTEL_PCH_TGP2_DEVICE_ID 0x4380
122 #define INTEL_PCH_JSP_DEVICE_ID 0x4d80
123 #define INTEL_PCH_ADP_DEVICE_ID 0x7a80
124 #define INTEL_PCH_ADP2_DEVICE_ID 0x5180
125 #define INTEL_PCH_ADP3_DEVICE_ID 0x7a00
126 #define INTEL_PCH_ADP4_DEVICE_ID 0x5480
127 #define INTEL_PCH_P2X_DEVICE_ID 0x7100
128 #define INTEL_PCH_P3X_DEVICE_ID 0x7000
129
130 // ValleyView MMIO offset
131 #define VLV_DISPLAY_BASE 0x180000
132
133 #define DEVICE_NAME "intel_extreme"
134 #define INTEL_ACCELERANT_NAME "intel_extreme.accelerant"
135
136 // We encode the register block into the value and extract/translate it when
137 // actually accessing.
138 #define REGISTER_BLOCK_COUNT 6
139 #define REGISTER_BLOCK_SHIFT 24
140 #define REGISTER_BLOCK_MASK 0xff000000
141 #define REGISTER_REGISTER_MASK 0x00ffffff
142 #define REGISTER_BLOCK(x) ((x & REGISTER_BLOCK_MASK) >> REGISTER_BLOCK_SHIFT)
143 #define REGISTER_REGISTER(x) (x & REGISTER_REGISTER_MASK)
144
145 #define REGS_FLAT (0 << REGISTER_BLOCK_SHIFT)
146 #define REGS_NORTH_SHARED (1 << REGISTER_BLOCK_SHIFT)
147 #define REGS_NORTH_PIPE_AND_PORT (2 << REGISTER_BLOCK_SHIFT)
148 #define REGS_NORTH_PLANE_CONTROL (3 << REGISTER_BLOCK_SHIFT)
149 #define REGS_SOUTH_SHARED (4 << REGISTER_BLOCK_SHIFT)
150 #define REGS_SOUTH_TRANSCODER_PORT (5 << REGISTER_BLOCK_SHIFT)
151
152 // register blocks for (G)MCH/ICH based platforms
153 #define MCH_SHARED_REGISTER_BASE 0x00000
154 #define MCH_PIPE_AND_PORT_REGISTER_BASE 0x60000
155 #define MCH_PLANE_CONTROL_REGISTER_BASE 0x70000
156
157 #define ICH_SHARED_REGISTER_BASE 0x00000
158 #define ICH_PORT_REGISTER_BASE 0x60000
159
160 // PCH - Platform Control Hub - Some hardware moves from a MCH/ICH based
161 // setup to a PCH based one, that means anything that used to communicate via
162 // (G)MCH registers needs to use different ones on PCH based platforms
163 // (Ironlake, SandyBridge, IvyBridge, Some Haswell).
164 #define PCH_NORTH_SHARED_REGISTER_BASE 0x40000
165 #define PCH_NORTH_PIPE_AND_PORT_REGISTER_BASE 0x60000
166 #define PCH_NORTH_PLANE_CONTROL_REGISTER_BASE 0x70000
167 #define PCH_SOUTH_SHARED_REGISTER_BASE 0xc0000
168 #define PCH_SOUTH_TRANSCODER_AND_PORT_REGISTER_BASE 0xe0000
169
170
171 struct DeviceType {
172 uint32 type;
173
DeviceTypeDeviceType174 DeviceType(int t)
175 {
176 type = t;
177 }
178
179 DeviceType& operator=(int t)
180 {
181 type = t;
182 return *this;
183 }
184
InFamilyDeviceType185 bool InFamily(uint32 family) const
186 {
187 return (type & INTEL_FAMILY_MASK) == family;
188 }
189
InGroupDeviceType190 bool InGroup(uint32 group) const
191 {
192 return (type & INTEL_GROUP_MASK) == group;
193 }
194
IsModelDeviceType195 bool IsModel(uint32 model) const
196 {
197 return (type & INTEL_MODEL_MASK) == model;
198 }
199
IsMobileDeviceType200 bool IsMobile() const
201 {
202 return (type & INTEL_TYPE_MASK) == INTEL_TYPE_MOBILE;
203 }
204
SupportsHDMIDeviceType205 bool SupportsHDMI() const
206 {
207 return InGroup(INTEL_GROUP_G4x) || InFamily(INTEL_FAMILY_SER5)
208 || InFamily(INTEL_FAMILY_SOC0);
209 }
210
HasDDIDeviceType211 bool HasDDI() const
212 {
213 // Intel Digital Display Interface
214 return InGroup(INTEL_GROUP_HAS) || (Generation() >= 8);
215 }
216
GenerationDeviceType217 int Generation() const
218 {
219 if (InFamily(INTEL_FAMILY_8xx))
220 return 2;
221 if (InGroup(INTEL_GROUP_91x) || InGroup(INTEL_GROUP_94x)
222 || IsModel(INTEL_MODEL_G33) || InGroup(INTEL_GROUP_PIN))
223 return 3;
224 if (InFamily(INTEL_FAMILY_9xx))
225 return 4;
226 if (InGroup(INTEL_GROUP_ILK))
227 return 5;
228 if (InGroup(INTEL_GROUP_SNB))
229 return 6;
230 if (InFamily(INTEL_FAMILY_SER5) || InGroup(INTEL_GROUP_VLV))
231 return 7;
232 if (InGroup(INTEL_GROUP_CHV) || InGroup(INTEL_GROUP_BDW))
233 return 8;
234 if (InGroup(INTEL_GROUP_JSL))
235 return 11;
236 if (InGroup(INTEL_GROUP_TGL))
237 return 12;
238 if (InFamily(INTEL_FAMILY_LAKE))
239 return 9;
240
241 // Generation 0 means something is wrong :-)
242 return 0;
243 }
244 };
245
246 enum port_index {
247 INTEL_PORT_ANY, // wildcard for lookup functions
248 INTEL_PORT_A,
249 INTEL_PORT_B,
250 INTEL_PORT_C,
251 INTEL_PORT_D,
252 INTEL_PORT_E,
253 INTEL_PORT_F,
254 INTEL_PORT_G
255 };
256
257 enum pch_info {
258 INTEL_PCH_NONE = 0, // No PCH present
259 INTEL_PCH_IBX, // Ibexpeak
260 INTEL_PCH_CPT, // Cougarpoint
261 INTEL_PCH_LPT, // Lynxpoint
262 INTEL_PCH_SPT, // SunrisePoint
263 INTEL_PCH_CNP, // CannonLake
264 INTEL_PCH_ICP, // IceLake
265 INTEL_PCH_JSP, // JasperLake
266 INTEL_PCH_MCC, // Mule Creek Canyon
267 INTEL_PCH_TGP, // TigerLake
268 INTEL_PCH_ADP, // AlderLake
269 INTEL_PCH_NOP
270 };
271
272 // info about PLL on graphics card
273 struct pll_info {
274 uint32 reference_frequency;
275 uint32 max_frequency;
276 uint32 min_frequency;
277 uint32 divisor_register;
278 };
279
280 struct ring_buffer {
281 struct lock lock;
282 uint32 register_base;
283 uint32 offset;
284 uint32 size;
285 uint32 position;
286 uint32 space_left;
287 uint8* base;
288 };
289
290
291 struct child_device_config {
292 uint16 handle;
293 uint16 device_type;
294 #define DEVICE_TYPE_ANALOG_OUTPUT (1 << 0)
295 #define DEVICE_TYPE_DIGITAL_OUTPUT (1 << 1)
296 #define DEVICE_TYPE_DISPLAYPORT_OUTPUT (1 << 2)
297 #define DEVICE_TYPE_VIDEO_SIGNALING (1 << 3)
298 #define DEVICE_TYPE_TMDS_DVI_SIGNALING (1 << 4)
299 #define DEVICE_TYPE_LVDS_SIGNALING (1 << 5)
300 #define DEVICE_TYPE_HIGH_SPEED_LINK (1 << 6)
301 #define DEVICE_TYPE_DUAL_CHANNEL (1 << 8)
302 #define DEVICE_TYPE_COMPOSITE_OUTPUT (1 << 9)
303 #define DEVICE_TYPE_MIPI_OUTPUT (1 << 10)
304 #define DEVICE_TYPE_NOT_HDMI_OUTPUT (1 << 11)
305 #define DEVICE_TYPE_INTERNAL_CONNECTOR (1 << 12)
306 #define DEVICE_TYPE_HOTPLUG_SIGNALING (1 << 13)
307 #define DEVICE_TYPE_POWER_MANAGEMENT (1 << 14)
308 #define DEVICE_TYPE_CLASS_EXTENSION (1 << 15)
309
310 uint8 device_id[10];
311 uint16 addin_offset;
312 uint8 dvo_port;
313 uint8 i2c_pin;
314 uint8 slave_addr;
315 uint8 ddc_pin;
316 uint16 edid_ptr;
317 uint8 dvo_cfg;
318
319 struct {
320 bool efp_routed:1;
321 bool lane_reversal:1;
322 bool lspcon:1;
323 bool iboost:1;
324 bool hpd_invert:1;
325 bool use_vbt_vswing:1;
326 uint8 reserved:2;
327 bool hdmi_support:1;
328 bool dp_support:1;
329 bool tmds_support:1;
330 uint8 reserved2:5;
331 uint8 aux_channel;
332 uint8 dongle_detect;
333 } __attribute__((packed));
334
335 uint8 caps;
336 uint8 dvo_wiring;
337 uint8 dvo2_wiring;
338 uint16 extended_type;
339 uint8 dvo_function;
340
341 bool dp_usb_type_c:1;
342 bool tbt:1;
343 uint8 reserved3:2;
344 uint8 dp_port_trace_length:4;
345 uint8 dp_gpio_index;
346 uint8 dp_gpio_pin_num;
347 uint8 dp_iboost_level:4;
348 uint8 hdmi_iboost_level:4;
349 uint8 dp_max_link_rate:3;
350 uint8 dp_max_link_rate_reserved:5;
351 } __attribute__((packed));
352
353
354 enum dvo_port {
355 DVO_PORT_HDMIA,
356 DVO_PORT_HDMIB,
357 DVO_PORT_HDMIC,
358 DVO_PORT_HDMID,
359 DVO_PORT_LVDS,
360 DVO_PORT_TV,
361 DVO_PORT_CRT,
362 DVO_PORT_DPB,
363 DVO_PORT_DPC,
364 DVO_PORT_DPD,
365 DVO_PORT_DPA,
366 DVO_PORT_DPE,
367 DVO_PORT_HDMIE,
368 DVO_PORT_DPF,
369 DVO_PORT_HDMIF,
370 DVO_PORT_DPG,
371 DVO_PORT_HDMIG,
372 DVO_PORT_DPH,
373 DVO_PORT_HDMIH,
374 DVO_PORT_DPI,
375 DVO_PORT_HDMII,
376 };
377
378
379 enum dp_aux_channel {
380 DP_AUX_A = 0x40,
381 DP_AUX_B = 0x10,
382 DP_AUX_C = 0x20,
383 DP_AUX_D = 0x30,
384 DP_AUX_E = 0x50,
385 DP_AUX_F = 0x60,
386 DP_AUX_G = 0x70,
387 DP_AUX_H = 0x80,
388 DP_AUX_I = 0x90
389 };
390
391
392 enum aux_channel {
393 AUX_CH_A,
394 AUX_CH_B,
395 AUX_CH_C,
396 AUX_CH_D,
397 AUX_CH_E,
398 AUX_CH_F,
399 AUX_CH_G,
400 AUX_CH_H,
401 AUX_CH_I,
402 };
403
404
405 enum hpd_pin {
406 HPD_PORT_A,
407 HPD_PORT_B,
408 HPD_PORT_C,
409 HPD_PORT_D,
410 HPD_PORT_E,
411 HPD_PORT_TC1,
412 HPD_PORT_TC2,
413 HPD_PORT_TC3,
414 HPD_PORT_TC4,
415 HPD_PORT_TC5,
416 HPD_PORT_TC6,
417 };
418
419
420 struct intel_shared_info {
421 area_id mode_list_area; // area containing display mode list
422 uint32 mode_count;
423
424 display_mode current_mode; // pretty much a hack until per-display modes
425 display_timing panel_timing; // Hardware timings of the LVDS panel, extracted from BIOS
426 uint32 bytes_per_row;
427 uint32 bits_per_pixel;
428 uint32 dpms_mode;
429 uint16 min_brightness;
430
431 area_id registers_area; // area of memory mapped registers
432 uint32 register_blocks[REGISTER_BLOCK_COUNT];
433
434 uint8* status_page;
435 phys_addr_t physical_status_page;
436 uint8* graphics_memory;
437 phys_addr_t physical_graphics_memory;
438 uint32 graphics_memory_size;
439
440 addr_t frame_buffer;
441 uint32 frame_buffer_offset;
442
443 uint32 fdi_link_frequency; // In Mhz
444 uint32 hraw_clock;
445 uint32 hw_cdclk;
446
447 bool got_vbt;
448 bool single_head_locked;
449
450 struct lock accelerant_lock;
451 struct lock engine_lock;
452
453 ring_buffer primary_ring_buffer;
454
455 int32 overlay_channel_used;
456 bool overlay_active;
457 uintptr_t overlay_token;
458 phys_addr_t physical_overlay_registers;
459 uint32 overlay_offset;
460
461 bool hardware_cursor_enabled;
462 sem_id vblank_sem;
463
464 uint8* cursor_memory;
465 phys_addr_t physical_cursor_memory;
466 uint32 cursor_buffer_offset;
467 uint32 cursor_format;
468 bool cursor_visible;
469 uint16 cursor_hot_x;
470 uint16 cursor_hot_y;
471
472 DeviceType device_type;
473 char device_identifier[32];
474 struct pll_info pll_info;
475
476 enum pch_info pch_info;
477
478 edid1_info vesa_edid_info;
479 bool has_vesa_edid_info;
480
481 bool internal_crt_support;
482 uint32 device_config_count;
483 child_device_config device_configs[10];
484 };
485
486 enum pipe_index {
487 INTEL_PIPE_ANY,
488 INTEL_PIPE_A,
489 INTEL_PIPE_B,
490 INTEL_PIPE_C,
491 INTEL_PIPE_D
492 };
493
494 class pipes {
495 public:
pipes()496 pipes() : bitmask(0) {}
497
HasPipe(pipe_index pipe)498 bool HasPipe(pipe_index pipe)
499 {
500 if (pipe == INTEL_PIPE_ANY)
501 return bitmask != 0;
502
503 return (bitmask & (1 << pipe)) != 0;
504 }
505
SetPipe(pipe_index pipe)506 void SetPipe(pipe_index pipe)
507 {
508 if (pipe == INTEL_PIPE_ANY) {
509 bitmask = ~1;
510 // first bit corresponds to INTEL_PIPE_ANY but it's never used,
511 // so it should be 0
512 }
513 bitmask |= (1 << pipe);
514 }
515
ClearPipe(pipe_index pipe)516 void ClearPipe(pipe_index pipe)
517 {
518 if (pipe == INTEL_PIPE_ANY)
519 bitmask = 0;
520
521 bitmask &= ~(1 << pipe);
522 }
523
524 private:
525 uint8 bitmask;
526 };
527
528 //----------------- ioctl() interface ----------------
529
530 // magic code for ioctls
531 #define INTEL_PRIVATE_DATA_MAGIC 'itic'
532
533 // list ioctls
534 enum {
535 INTEL_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1,
536
537 INTEL_GET_DEVICE_NAME,
538 INTEL_ALLOCATE_GRAPHICS_MEMORY,
539 INTEL_FREE_GRAPHICS_MEMORY,
540 INTEL_GET_BRIGHTNESS_LEGACY,
541 INTEL_SET_BRIGHTNESS_LEGACY
542 };
543
544 // retrieve the area_id of the kernel/accelerant shared info
545 struct intel_get_private_data {
546 uint32 magic; // magic number
547 area_id shared_info_area;
548 };
549
550 // allocate graphics memory
551 struct intel_allocate_graphics_memory {
552 uint32 magic;
553 uint32 size;
554 uint32 alignment;
555 uint32 flags;
556 addr_t buffer_base;
557 };
558
559 // free graphics memory
560 struct intel_free_graphics_memory {
561 uint32 magic;
562 addr_t buffer_base;
563 };
564
565 // brightness legacy
566 struct intel_brightness_legacy {
567 uint32 magic;
568 uint8 lpc;
569 };
570
571 //----------------------------------------------------------
572 // Register definitions, taken from X driver
573
574 // PCI bridge memory management
575 #define INTEL_GRAPHICS_MEMORY_CONTROL 0x52 // i830+
576
577 // GGC - (G)MCH Graphics Control Register
578 #define MEMORY_CONTROL_ENABLED 0x0004
579 #define MEMORY_MASK 0x0001
580 #define STOLEN_MEMORY_MASK 0x00f0
581 #define i965_GTT_MASK 0x000e
582 #define G33_GTT_MASK 0x0300
583 #define G4X_GTT_MASK 0x0f00 // GGMS (GSM Memory Size) mask
584
585 // models i830 and up
586 #define i830_LOCAL_MEMORY_ONLY 0x10
587 #define i830_STOLEN_512K 0x20
588 #define i830_STOLEN_1M 0x30
589 #define i830_STOLEN_8M 0x40
590 #define i830_FRAME_BUFFER_64M 0x01
591 #define i830_FRAME_BUFFER_128M 0x00
592
593 // models i855 and up
594 #define i855_STOLEN_MEMORY_1M 0x10
595 #define i855_STOLEN_MEMORY_4M 0x20
596 #define i855_STOLEN_MEMORY_8M 0x30
597 #define i855_STOLEN_MEMORY_16M 0x40
598 #define i855_STOLEN_MEMORY_32M 0x50
599 #define i855_STOLEN_MEMORY_48M 0x60
600 #define i855_STOLEN_MEMORY_64M 0x70
601 #define i855_STOLEN_MEMORY_128M 0x80
602 #define i855_STOLEN_MEMORY_256M 0x90
603
604 #define G4X_STOLEN_MEMORY_96MB 0xa0 // GMS - Graphics Mode Select
605 #define G4X_STOLEN_MEMORY_160MB 0xb0
606 #define G4X_STOLEN_MEMORY_224MB 0xc0
607 #define G4X_STOLEN_MEMORY_352MB 0xd0
608
609 // SandyBridge (SNB)
610
611 #define SNB_GRAPHICS_MEMORY_CONTROL 0x50
612
613 #define SNB_STOLEN_MEMORY_MASK 0xf8
614 #define SNB_STOLEN_MEMORY_32MB (1 << 3)
615 #define SNB_STOLEN_MEMORY_64MB (2 << 3)
616 #define SNB_STOLEN_MEMORY_96MB (3 << 3)
617 #define SNB_STOLEN_MEMORY_128MB (4 << 3)
618 #define SNB_STOLEN_MEMORY_160MB (5 << 3)
619 #define SNB_STOLEN_MEMORY_192MB (6 << 3)
620 #define SNB_STOLEN_MEMORY_224MB (7 << 3)
621 #define SNB_STOLEN_MEMORY_256MB (8 << 3)
622 #define SNB_STOLEN_MEMORY_288MB (9 << 3)
623 #define SNB_STOLEN_MEMORY_320MB (10 << 3)
624 #define SNB_STOLEN_MEMORY_352MB (11 << 3)
625 #define SNB_STOLEN_MEMORY_384MB (12 << 3)
626 #define SNB_STOLEN_MEMORY_416MB (13 << 3)
627 #define SNB_STOLEN_MEMORY_448MB (14 << 3)
628 #define SNB_STOLEN_MEMORY_480MB (15 << 3)
629 #define SNB_STOLEN_MEMORY_512MB (16 << 3)
630
631 #define SNB_GTT_SIZE_MASK (3 << 8)
632 #define SNB_GTT_SIZE_NONE (0 << 8)
633 #define SNB_GTT_SIZE_1MB (1 << 8)
634 #define SNB_GTT_SIZE_2MB (2 << 8)
635
636 // BDW+ (GGC_0_0_0_PCI)
637
638 #define BDW_GRAPHICS_MEMORY_CONTROL 0x50
639
640 #define BDW_STOLEN_MEMORY_MASK 0xff00
641 #define BDW_STOLEN_MEMORY_32MB (1 << 8)
642 #define BDW_STOLEN_MEMORY_64MB (2 << 8)
643 #define BDW_STOLEN_MEMORY_96MB (3 << 8)
644 #define BDW_STOLEN_MEMORY_128MB (4 << 8)
645 #define BDW_STOLEN_MEMORY_160MB (5 << 8)
646 #define BDW_STOLEN_MEMORY_192MB (6 << 8)
647 #define BDW_STOLEN_MEMORY_224MB (7 << 8)
648 #define BDW_STOLEN_MEMORY_256MB (8 << 8)
649 #define BDW_STOLEN_MEMORY_288MB (9 << 8)
650 #define BDW_STOLEN_MEMORY_320MB (10 << 8)
651 #define BDW_STOLEN_MEMORY_352MB (11 << 8)
652 #define BDW_STOLEN_MEMORY_384MB (12 << 8)
653 #define BDW_STOLEN_MEMORY_416MB (13 << 8)
654 #define BDW_STOLEN_MEMORY_448MB (14 << 8)
655 #define BDW_STOLEN_MEMORY_480MB (15 << 8)
656 #define BDW_STOLEN_MEMORY_512MB (16 << 8)
657 #define BDW_STOLEN_MEMORY_1024MB (32 << 8)
658 #define BDW_STOLEN_MEMORY_1536MB (48 << 8)
659 #define BDW_STOLEN_MEMORY_2016MB (63 << 8)
660 #define SKL_STOLEN_MEMORY_2048MB (64 << 8)
661 #define SKL_STOLEN_MEMORY_4MB (240 << 8)
662 #define SKL_STOLEN_MEMORY_8MB (241 << 8)
663 #define SKL_STOLEN_MEMORY_12MB (242 << 8)
664 #define SKL_STOLEN_MEMORY_16MB (243 << 8)
665 #define SKL_STOLEN_MEMORY_20MB (244 << 8)
666 #define SKL_STOLEN_MEMORY_24MB (245 << 8)
667 #define SKL_STOLEN_MEMORY_28MB (246 << 8)
668 #define SKL_STOLEN_MEMORY_32MB (247 << 8)
669 #define SKL_STOLEN_MEMORY_36MB (248 << 8)
670 #define SKL_STOLEN_MEMORY_40MB (249 << 8)
671 #define SKL_STOLEN_MEMORY_44MB (250 << 8)
672 #define SKL_STOLEN_MEMORY_48MB (251 << 8)
673 #define SKL_STOLEN_MEMORY_52MB (252 << 8)
674 #define SKL_STOLEN_MEMORY_56MB (253 << 8)
675 #define SKL_STOLEN_MEMORY_60MB (254 << 8)
676
677
678 #define BDW_GTT_SIZE_MASK (3 << 6)
679 #define BDW_GTT_SIZE_NONE (0 << 6)
680 #define BDW_GTT_SIZE_2MB (1 << 6)
681 #define BDW_GTT_SIZE_4MB (2 << 6)
682 #define BDW_GTT_SIZE_8MB (3 << 6)
683
684 // Gen2, i915GM, i945GM
685 #define LEGACY_BACKLIGHT_BRIGHTNESS 0xf4
686
687 // graphics page translation table
688 #define INTEL_PAGE_TABLE_CONTROL 0x02020
689 #define PAGE_TABLE_ENABLED 0x00000001
690 #define INTEL_PAGE_TABLE_ERROR 0x02024
691 #define INTEL_HARDWARE_STATUS_PAGE 0x02080
692 #define i915_GTT_BASE 0x1c
693 #define i830_GTT_BASE 0x10000 // (- 0x2ffff)
694 #define i830_GTT_SIZE 0x20000
695 #define i965_GTT_BASE 0x80000 // (- 0xfffff)
696 #define i965_GTT_SIZE 0x80000
697 #define i965_GTT_128K (2 << 1)
698 #define i965_GTT_256K (1 << 1)
699 #define i965_GTT_512K (0 << 1)
700 #define G33_GTT_1M (1 << 8)
701 #define G33_GTT_2M (2 << 8)
702 #define G4X_GTT_NONE 0x000 // GGMS - GSM Memory Size
703 #define G4X_GTT_1M_NO_IVT 0x100 // no Intel Virtualization Tech.
704 #define G4X_GTT_2M_NO_IVT 0x300
705 #define G4X_GTT_2M_IVT 0x900 // with Intel Virt. Tech.
706 #define G4X_GTT_3M_IVT 0xa00
707 #define G4X_GTT_4M_IVT 0xb00
708
709
710 #define GTT_ENTRY_VALID 0x01
711 #define GTT_ENTRY_LOCAL_MEMORY 0x02
712 #define GTT_PAGE_SHIFT 12
713
714
715 // ring buffer
716 #define INTEL_PRIMARY_RING_BUFFER 0x02030
717 #define INTEL_SECONDARY_RING_BUFFER_0 0x02100
718 #define INTEL_SECONDARY_RING_BUFFER_1 0x02110
719 // offsets for the ring buffer base registers above
720 #define RING_BUFFER_TAIL 0x0
721 #define RING_BUFFER_HEAD 0x4
722 #define RING_BUFFER_START 0x8
723 #define RING_BUFFER_CONTROL 0xc
724 #define INTEL_RING_BUFFER_SIZE_MASK 0x001ff000
725 #define INTEL_RING_BUFFER_HEAD_MASK 0x001ffffc
726 #define INTEL_RING_BUFFER_ENABLED 1
727
728 // interrupts
729 #define INTEL_INTERRUPT_ENABLED 0x020a0
730 #define INTEL_INTERRUPT_IDENTITY 0x020a4
731 #define INTEL_INTERRUPT_MASK 0x020a8
732 #define INTEL_INTERRUPT_STATUS 0x020ac
733 #define INTERRUPT_VBLANK_PIPEA (1 << 7)
734 #define INTERRUPT_VBLANK_PIPEB (1 << 5)
735
736 // PCH interrupts
737 #define PCH_INTERRUPT_STATUS 0x44000
738 #define PCH_INTERRUPT_MASK 0x44004
739 #define PCH_INTERRUPT_IDENTITY 0x44008
740 #define PCH_INTERRUPT_ENABLED 0x4400c
741
742 #define PCH_INTERRUPT_VBLANK_PIPEA (1 << 0)
743 #define PCH_INTERRUPT_VBLANK_PIPEB (1 << 5)
744 #define PCH_INTERRUPT_VBLANK_PIPEC (1 << 10)
745
746 // SandyBridge had only two pipes, and things were shuffled aroud again with
747 // the introduction of pipe C.
748 #define PCH_INTERRUPT_VBLANK_PIPEA_SNB (1 << 7)
749 #define PCH_INTERRUPT_VBLANK_PIPEB_SNB (1 << 15)
750 #define PCH_INTERRUPT_GLOBAL_SNB (1 << 31)
751
752 #define PCH_MASTER_INT_CTL_BDW 0x44200
753
754 #define PCH_MASTER_INT_CTL_PIPE_PENDING_BDW(pipe) (1 << (15 + pipe))
755 #define GEN8_DE_PCH_IRQ (1 << 23)
756 #define GEN8_DE_PORT_IRQ (1 << 20)
757 #define PCH_MASTER_INT_CTL_GLOBAL_BDW (1 << 31)
758
759 #define PCH_INTERRUPT_PIPE_STATUS_BDW(pipe) (0x44400 + (pipe - 1) * 0x10) // GEN8_DE_PIPE_ISR
760 #define PCH_INTERRUPT_PIPE_MASK_BDW(pipe) (0x44404 + (pipe - 1) * 0x10) // GEN8_DE_PIPE_IMR
761 #define PCH_INTERRUPT_PIPE_IDENTITY_BDW(pipe) (0x44408 + (pipe - 1) * 0x10) // GEN8_DE_PIPE_IIR
762 #define PCH_INTERRUPT_PIPE_ENABLED_BDW(pipe) (0x4440c + (pipe - 1) * 0x10) // GEN8_DE_PIPE_IER
763
764 #define GEN8_DE_PORT_ISR 0x44440
765 #define GEN8_DE_PORT_IMR 0x44444
766 #define GEN8_DE_PORT_IIR 0x44448
767 #define GEN8_DE_PORT_IER 0x4444c
768 #define GEN8_AUX_CHANNEL_A (1 << 0)
769 #define GEN9_AUX_CHANNEL_B (1 << 25)
770 #define GEN9_AUX_CHANNEL_C (1 << 26)
771 #define GEN9_AUX_CHANNEL_D (1 << 27)
772 #define CNL_AUX_CHANNEL_F (1 << 28)
773 #define ICL_AUX_CHANNEL_E (1 << 29)
774
775 #define GEN8_DE_MISC_ISR 0x44460
776 #define GEN8_DE_MISC_IMR 0x44464
777 #define GEN8_DE_MISC_IIR 0x44468
778 #define GEN8_DE_MISC_IER 0x4446c
779 #define GEN8_DE_EDP_PSR (1 << 19)
780
781 #define GEN11_DE_HPD_ISR 0x44470
782 #define GEN11_DE_HPD_IMR 0x44474
783 #define GEN11_DE_HPD_IIR 0x44478
784 #define GEN11_DE_HPD_IER 0x4447c
785 #define GEN11_DE_TC_HOTPLUG_MASK (0x3f << 16)
786 #define GEN11_DE_TBT_HOTPLUG_MASK (0x3f)
787
788 #define GEN11_TBT_HOTPLUG_CTL 0x44030
789 #define GEN11_TC_HOTPLUG_CTL 0x44038
790
791 #define SHPD_FILTER_CNT 0xc4038
792 #define SHPD_FILTER_CNT_500_ADJ 0x1d9
793
794 #define SDEISR 0xc4000
795 #define SDEIMR 0xc4004
796 #define SDEIIR 0xc4008
797 #define SDEIER 0xc400c
798 #define SDE_GMBUS_ICP (1 << 23)
799
800 #define SHOTPLUG_CTL_DDI 0xc4030
801 #define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8 << (4 * ((hpd_pin) - HPD_PORT_A)))
802 #define SHOTPLUG_CTL_TC 0xc4034
803 #define SHOTPLUG_CTL_TC_HPD_ENABLE(hpd_pin) (0x8 << (4 * ((hpd_pin) - HPD_PORT_TC1)))
804
805 #define PCH_PORT_HOTPLUG SHOTPLUG_CTL_DDI
806 #define PCH_PORT_HOTPLUG2 0xc403c
807
808 #define PCH_INTERRUPT_VBLANK_BDW (1 << 0) // GEN8_PIPE_VBLANK
809 #define GEN8_PIPE_VSYNC (1 << 1)
810 #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2)
811
812 #define GEN11_GFX_MSTR_IRQ 0x190010
813 #define GEN11_MASTER_IRQ (1 << 31)
814 #define GEN11_DISPLAY_IRQ (1 << 16)
815 #define GEN11_GT_DW1_IRQ (1 << 1)
816 #define GEN11_GT_DW0_IRQ (1 << 0)
817
818 #define GEN11_DISPLAY_INT_CTL 0x44200 // same as PCH_MASTER_INT_CTL_BDW
819 #define GEN11_DE_HPD_IRQ (1 << 21)
820
821 #define GEN11_GT_INTR_DW0 0x190018
822 #define GEN11_GT_INTR_DW1 0x19001c
823
824 #define GEN11_GU_MISC_IMR 0x444f4
825 #define GEN11_GU_MISC_IIR 0x444f8
826 #define GEN11_GU_MISC_IER 0x444fc
827 #define GEN11_GU_MISC_GSE (1 << 27)
828
829
830 // graphics port control (i.e. G45)
831 #define DISPLAY_MONITOR_PORT_ENABLED (1UL << 31)
832 #define DISPLAY_MONITOR_PIPE_B (1UL << 30)
833 #define DISPLAY_MONITOR_VGA_POLARITY (1UL << 15)
834 #define DISPLAY_MONITOR_MODE_MASK (3UL << 10)
835 #define DISPLAY_MONITOR_ON 0
836 #define DISPLAY_MONITOR_SUSPEND (1UL << 10)
837 #define DISPLAY_MONITOR_STAND_BY (2UL << 10)
838 #define DISPLAY_MONITOR_OFF (3UL << 10)
839 #define DISPLAY_MONITOR_POLARITY_MASK (3UL << 3)
840 #define DISPLAY_MONITOR_POSITIVE_HSYNC (1UL << 3)
841 #define DISPLAY_MONITOR_POSITIVE_VSYNC (2UL << 3)
842 #define DISPLAY_MONITOR_PORT_DETECTED (1UL << 2) // TMDS/DisplayPort only
843
844 // Cougar Point transcoder pipe selection
845 // (replaces DISPLAY_MONITOR_PIPE_B)
846 #define PORT_TRANS_A_SEL_CPT 0
847 #define PORT_TRANS_B_SEL_CPT (1<<29)
848 #define PORT_TRANS_C_SEL_CPT (2<<29)
849 #define PORT_TRANS_SEL_MASK (3<<29)
850
851 #define LVDS_POST2_RATE_SLOW 14 // PLL Divisors
852 #define LVDS_POST2_RATE_FAST 7
853 #define LVDS_B0B3_POWER_MASK (3UL << 2)
854 #define LVDS_B0B3_POWER_UP (3UL << 2)
855 #define LVDS_CLKB_POWER_MASK (3UL << 4)
856 #define LVDS_CLKB_POWER_UP (3UL << 4)
857 #define LVDS_A3_POWER_MASK (3UL << 6)
858 #define LVDS_A3_POWER_UP (3UL << 6)
859 #define LVDS_A0A2_CLKA_POWER_UP (3UL << 8)
860 #define LVDS_BORDER_ENABLE (1UL << 15)
861 #define LVDS_HSYNC_POLARITY (1UL << 20)
862 #define LVDS_VSYNC_POLARITY (1UL << 21)
863 #define LVDS_18BIT_DITHER (1UL << 25)
864 #define LVDS_PORT_EN (1UL << 31)
865
866 // PLL flags (pre-DDI)
867 #define DISPLAY_PLL_ENABLED (1UL << 31)
868 #define DISPLAY_PLL_2X_CLOCK (1UL << 30)
869 #define DISPLAY_PLL_SYNC_LOCK_ENABLED (1UL << 29)
870 #define DISPLAY_PLL_NO_VGA_CONTROL (1UL << 28)
871 #define DISPLAY_PLL_MODE_NORMAL (1UL << 26)
872 #define DISPLAY_PLL_MODE_LVDS (2UL << 26)
873 #define DISPLAY_PLL_DIVIDE_HIGH (1UL << 24)
874 #define DISPLAY_PLL_DIVIDE_4X (1UL << 23)
875 #define DISPLAY_PLL_POST1_DIVIDE_2 (1UL << 21)
876 #define DISPLAY_PLL_POST1_DIVISOR_MASK 0x001f0000
877 #define DISPLAY_PLL_9xx_POST1_DIVISOR_MASK 0x00ff0000
878 #define DISPLAY_PLL_SNB_FP0_POST1_DIVISOR_MASK 0x000000ff
879 #define DISPLAY_PLL_IGD_POST1_DIVISOR_MASK 0x00ff8000
880 #define DISPLAY_PLL_POST1_DIVISOR_SHIFT 16
881 #define DISPLAY_PLL_SNB_FP0_POST1_DIVISOR_SHIFT 0
882 #define DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT 15
883 #define DISPLAY_PLL_DIVISOR_1 (1UL << 8)
884 #define DISPLAY_PLL_N_DIVISOR_MASK 0x001f0000
885 #define DISPLAY_PLL_IGD_N_DIVISOR_MASK 0x00ff0000
886 #define DISPLAY_PLL_M1_DIVISOR_MASK 0x00001f00
887 #define DISPLAY_PLL_M2_DIVISOR_MASK 0x0000001f
888 #define DISPLAY_PLL_IGD_M2_DIVISOR_MASK 0x000000ff
889 #define DISPLAY_PLL_N_DIVISOR_SHIFT 16
890 #define DISPLAY_PLL_M1_DIVISOR_SHIFT 8
891 #define DISPLAY_PLL_M2_DIVISOR_SHIFT 0
892 #define DISPLAY_PLL_PULSE_PHASE_SHIFT 9
893
894 // Skylake PLLs
895 #define SKL_DPLL1_CFGCR1 (0xc040 | REGS_NORTH_PIPE_AND_PORT)
896 #define SKL_DPLL1_CFGCR2 (0xc044 | REGS_NORTH_PIPE_AND_PORT)
897 #define SKL_DPLL2_CFGCR1 (0xc048 | REGS_NORTH_PIPE_AND_PORT)
898 #define SKL_DPLL2_CFGCR2 (0xc04c | REGS_NORTH_PIPE_AND_PORT)
899 #define SKL_DPLL3_CFGCR1 (0xc050 | REGS_NORTH_PIPE_AND_PORT)
900 #define SKL_DPLL3_CFGCR2 (0xc054 | REGS_NORTH_PIPE_AND_PORT)
901 // These exist also still in CoffeeLake (confirmed):
902 #define SKL_DPLL_CTRL1 (0xc058 | REGS_NORTH_PIPE_AND_PORT)
903 #define SKL_DPLL_CTRL2 (0xc05c | REGS_NORTH_PIPE_AND_PORT)
904 #define SKL_DPLL_STATUS (0xc060 | REGS_NORTH_PIPE_AND_PORT)
905 #define SKL_DPLL0_DP_LINKRATE_SHIFT 1
906 #define SKL_DPLL1_DP_LINKRATE_SHIFT 7
907 #define SKL_DPLL2_DP_LINKRATE_SHIFT 13
908 #define SKL_DPLL3_DP_LINKRATE_SHIFT 19
909 #define SKL_DPLL_DP_LINKRATE_MASK 7
910 #define SKL_DPLL_CTRL1_2700 0
911 #define SKL_DPLL_CTRL1_1350 1
912 #define SKL_DPLL_CTRL1_810 2
913 #define SKL_DPLL_CTRL1_1620 3
914 #define SKL_DPLL_CTRL1_1080 4
915 #define SKL_DPLL_CTRL1_2160 5
916
917 // Icelake PLLs
918 #define ICL_DSSM 0x51004
919 #define ICL_DSSM_REF_FREQ_SHIFT 29
920 #define ICL_DSSM_REF_FREQ_MASK (7 << ICL_DSSM_REF_FREQ_SHIFT)
921 #define ICL_DSSM_24000 0
922 #define ICL_DSSM_19200 1
923 #define ICL_DSSM_38400 2
924
925 #define LCPLL_CTL 0x130040
926 #define LCPLL_CLK_FREQ_MASK (3 << 26)
927 #define LCPLL_CLK_FREQ_450 (0 << 26)
928 #define LCPLL_CLK_FREQ_54O_BDW (1 << 26)
929 #define LCPLL_CLK_FREQ_337_5_BDW (2 << 26)
930 #define LCPLL_CD_SOURCE_FCLK (1 << 21)
931
932 // Tigerlake PLLs
933 #define TGL_DPCLKA_CFGCR0 0x164280
934 #define TGL_DPCLKA_DDIC_CLOCK_OFF (1 << 24)
935 #define TGL_DPCLKA_TC6_CLOCK_OFF (1 << 23)
936 #define TGL_DPCLKA_TC5_CLOCK_OFF (1 << 22)
937 #define TGL_DPCLKA_TC4_CLOCK_OFF (1 << 21)
938 #define TGL_DPCLKA_TC3_CLOCK_OFF (1 << 14)
939 #define TGL_DPCLKA_TC2_CLOCK_OFF (1 << 13)
940 #define TGL_DPCLKA_TC1_CLOCK_OFF (1 << 12)
941 #define TGL_DPCLKA_DDIB_CLOCK_OFF (1 << 11)
942 #define TGL_DPCLKA_DDIA_CLOCK_OFF (1 << 10)
943 #define TGL_DPCLKA_DDIC_CLOCK_SELECT (3 << 4)
944 #define TGL_DPCLKA_DDIB_CLOCK_SELECT (3 << 2)
945 #define TGL_DPCLKA_DDIB_CLOCK_SELECT_SHIFT 2
946 #define TGL_DPCLKA_DDIA_CLOCK_SELECT (3 << 0)
947
948 #define TGL_DPLL0_CFGCR0 0x164284
949 #define TGL_DPLL1_CFGCR0 0x16428C
950 #define TGL_TBTPLL_CFGCR0 0x16429C
951 #define TGL_DPLL4_CFGCR0 0x164294
952 #define TGL_DPLL_DCO_FRACTION (0x7FFF << 10)
953 #define TGL_DPLL_DCO_FRACTION_SHIFT 10
954 #define TGL_DPLL_DCO_INTEGER (0x3FF << 0)
955
956 #define TGL_DPLL0_CFGCR1 0x164288
957 #define TGL_DPLL1_CFGCR1 0x164290
958 #define TGL_TBTPLL_CFGCR1 0x1642A0
959 #define TGL_DPLL4_CFGCR1 0x164298
960 #define TGL_DPLL_QDIV_RATIO (0xFF << 10)
961 #define TGL_DPLL_QDIV_RATIO_SHIFT 10
962 #define TGL_DPLL_QDIV_ENABLE (1 << 9)
963 #define TGL_DPLL_KDIV (7 << 6)
964 #define TGL_DPLL_KDIV_1 (1 << 6)
965 #define TGL_DPLL_KDIV_2 (2 << 6)
966 #define TGL_DPLL_KDIV_3 (4 << 6)
967 #define TGL_DPLL_PDIV (0xF << 2)
968 #define TGL_DPLL_PDIV_2 (1 << 2)
969 #define TGL_DPLL_PDIV_3 (2 << 2)
970 #define TGL_DPLL_PDIV_5 (4 << 2)
971 #define TGL_DPLL_PDIV_7 (8 << 2)
972 #define TGL_DPLL_CFSELOVRD (3 << 0)
973
974 #define TGL_DPLL0_DIV0 0x164B00
975 #define TGL_DPLL1_DIV0 0x164C00
976 #define TGL_DPLL4_DIV0 0x164E00
977 #define TGL_DPLL_I_TRUELOCK_CRITERIA (3 << 30)
978 #define TGL_DPLL_I_EARLYLOCK_CRITERIA (3 << 28)
979 #define TGL_DPLL_I_AFC_STARTUP (7 << 25)
980 #define TGL_DPLL_I_DIV_RETIMER_EN (1 << 24)
981 #define TGL_DPLL_I_GAIN_CTRL (7 << 21)
982 #define TGL_DPLL_I_INTEGRAL_COEFF (0xF << 16)
983 #define TGL_DPLL_I_PROPORTIONAL_COEFF (0xF << 12)
984 #define TGL_DPLL_I_FB_PREDIVIDER (0xF << 8)
985 #define TGL_DPLL_I_FB_DIVIDER_M2 (0xFF << 0)
986
987 #define TGL_DPLL0_ENABLE 0x46010
988 #define TGL_DPLL1_ENABLE 0x46014
989 #define TGL_DPLL4_ENABLE 0x46018
990 #define TGL_DPLL_ENABLE (1 << 31)
991 #define TGL_DPLL_LOCK (1 << 30)
992 #define TGL_DPLL_POWER_ENABLE (1 << 27)
993 #define TGL_DPLL_POWER_STATE (1 << 26)
994
995 #define TGL_DPLL0_SPREAD_SPECTRUM 0x164B10
996 #define TGL_DPLL1_SPREAD_SPECTRUM 0x164C10
997 #define TGL_DPLL4_SPREAD_SPECTRUM 0x164E10
998 #define TGL_DPLL_IREF_NDIVRATIO (3 << 29)
999 #define TGL_DPLL_SSC_STEP_NUMBER_OFFSET (3 << 26)
1000 #define TGL_DPLL_SSC_INJECTION_ADAPTIVE_GAIN_CHANGE_ENABLE (1 << 25)
1001 #define TGL_DPLL_SSC_INJECTION_ENABLE (1 << 24)
1002 #define TGL_DPLL_SSC_STEP_LENGTH (0xFF << 16)
1003 #define TGL_DPLL_SSC_FLL_UPDATE (3 << 14)
1004 #define TGL_DPLL_SSC_STEP_NUMBER (7 << 11)
1005 #define TGL_DPLL_SSC_OPENLOOP (1 << 10)
1006 #define TGL_DPLL_SSC_ENABLE (1 << 9)
1007 #define TGL_DPLL_SSC_FLL_ENABLE (1 << 8)
1008 #define TGL_DPLL_SSC_BIAS_GUARD_BAND (3 << 6)
1009 #define TGL_DPLL_SSC_INIT_DCO_AMP (0x3F << 0)
1010
1011 #define FUSE_STRAP 0x42014
1012 #define HSW_CDCLK_LIMIT (1 << 24)
1013
1014 // display
1015
1016 #define INTEL_DISPLAY_OFFSET 0x1000
1017
1018 // Note: on Skylake below registers are part of the transcoder
1019 #define INTEL_DISPLAY_A_HTOTAL (0x0000 | REGS_NORTH_PIPE_AND_PORT)
1020 #define INTEL_DISPLAY_A_HBLANK (0x0004 | REGS_NORTH_PIPE_AND_PORT)
1021 #define INTEL_DISPLAY_A_HSYNC (0x0008 | REGS_NORTH_PIPE_AND_PORT)
1022 #define INTEL_DISPLAY_A_VTOTAL (0x000c | REGS_NORTH_PIPE_AND_PORT)
1023 #define INTEL_DISPLAY_A_VBLANK (0x0010 | REGS_NORTH_PIPE_AND_PORT)
1024 #define INTEL_DISPLAY_A_VSYNC (0x0014 | REGS_NORTH_PIPE_AND_PORT)
1025 #define INTEL_DISPLAY_B_HTOTAL (0x1000 | REGS_NORTH_PIPE_AND_PORT)
1026 #define INTEL_DISPLAY_B_HBLANK (0x1004 | REGS_NORTH_PIPE_AND_PORT)
1027 #define INTEL_DISPLAY_B_HSYNC (0x1008 | REGS_NORTH_PIPE_AND_PORT)
1028 #define INTEL_DISPLAY_B_VTOTAL (0x100c | REGS_NORTH_PIPE_AND_PORT)
1029 #define INTEL_DISPLAY_B_VBLANK (0x1010 | REGS_NORTH_PIPE_AND_PORT)
1030 #define INTEL_DISPLAY_B_VSYNC (0x1014 | REGS_NORTH_PIPE_AND_PORT)
1031
1032 #define INTEL_DISPLAY_A_PIPE_SIZE (0x001c | REGS_NORTH_PIPE_AND_PORT)
1033 #define INTEL_DISPLAY_B_PIPE_SIZE (0x101c | REGS_NORTH_PIPE_AND_PORT)
1034
1035 //G45 displayport link
1036 #define INTEL_PIPE_A_DATA_M (0x0050 | REGS_NORTH_PLANE_CONTROL)
1037 #define INTEL_PIPE_B_DATA_M (0x1050 | REGS_NORTH_PLANE_CONTROL)
1038 #define INTEL_PIPE_A_DATA_N (0x0054 | REGS_NORTH_PLANE_CONTROL)
1039 #define INTEL_PIPE_B_DATA_N (0x1054 | REGS_NORTH_PLANE_CONTROL)
1040 #define INTEL_PIPE_A_LINK_M (0x0060 | REGS_NORTH_PLANE_CONTROL)
1041 #define INTEL_PIPE_B_LINK_M (0x1060 | REGS_NORTH_PLANE_CONTROL)
1042 #define INTEL_PIPE_A_LINK_N (0x0064 | REGS_NORTH_PLANE_CONTROL)
1043 #define INTEL_PIPE_B_LINK_N (0x1064 | REGS_NORTH_PLANE_CONTROL)
1044
1045 //DDI port link
1046 #define INTEL_DDI_PIPE_A_DATA_M (0x0030 | REGS_NORTH_PIPE_AND_PORT)
1047 #define INTEL_DDI_PIPE_B_DATA_M (0x1030 | REGS_NORTH_PIPE_AND_PORT)
1048 #define INTEL_DDI_PIPE_A_DATA_N (0x0034 | REGS_NORTH_PIPE_AND_PORT)
1049 #define INTEL_DDI_PIPE_B_DATA_N (0x1034 | REGS_NORTH_PIPE_AND_PORT)
1050 #define INTEL_DDI_PIPE_A_LINK_M (0x0040 | REGS_NORTH_PIPE_AND_PORT)
1051 #define INTEL_DDI_PIPE_B_LINK_M (0x1040 | REGS_NORTH_PIPE_AND_PORT)
1052 #define INTEL_DDI_PIPE_A_LINK_N (0x0044 | REGS_NORTH_PIPE_AND_PORT)
1053 #define INTEL_DDI_PIPE_B_LINK_N (0x1044 | REGS_NORTH_PIPE_AND_PORT)
1054
1055 // on PCH we also have to set the transcoder
1056 #define INTEL_TRANSCODER_A_HTOTAL (0x0000 | REGS_SOUTH_TRANSCODER_PORT)
1057 #define INTEL_TRANSCODER_A_HBLANK (0x0004 | REGS_SOUTH_TRANSCODER_PORT)
1058 #define INTEL_TRANSCODER_A_HSYNC (0x0008 | REGS_SOUTH_TRANSCODER_PORT)
1059 #define INTEL_TRANSCODER_A_VTOTAL (0x000c | REGS_SOUTH_TRANSCODER_PORT)
1060 #define INTEL_TRANSCODER_A_VBLANK (0x0010 | REGS_SOUTH_TRANSCODER_PORT)
1061 #define INTEL_TRANSCODER_A_VSYNC (0x0014 | REGS_SOUTH_TRANSCODER_PORT)
1062 #define INTEL_TRANSCODER_B_HTOTAL (0x1000 | REGS_SOUTH_TRANSCODER_PORT)
1063 #define INTEL_TRANSCODER_B_HBLANK (0x1004 | REGS_SOUTH_TRANSCODER_PORT)
1064 #define INTEL_TRANSCODER_B_HSYNC (0x1008 | REGS_SOUTH_TRANSCODER_PORT)
1065 #define INTEL_TRANSCODER_B_VTOTAL (0x100c | REGS_SOUTH_TRANSCODER_PORT)
1066 #define INTEL_TRANSCODER_B_VBLANK (0x1010 | REGS_SOUTH_TRANSCODER_PORT)
1067 #define INTEL_TRANSCODER_B_VSYNC (0x1014 | REGS_SOUTH_TRANSCODER_PORT)
1068
1069 // transcoder M/N DATA AND LINK VALUES (refreshrate)
1070 #define INTEL_TRANSCODER_A_DATA_M1 (0x0030 | REGS_SOUTH_TRANSCODER_PORT)
1071 #define INTEL_TRANSCODER_A_DATA_M2 (0x0038 | REGS_SOUTH_TRANSCODER_PORT)
1072 #define INTEL_TRANSCODER_B_DATA_M1 (0x1030 | REGS_SOUTH_TRANSCODER_PORT)
1073 #define INTEL_TRANSCODER_B_DATA_M2 (0x1038 | REGS_SOUTH_TRANSCODER_PORT)
1074 #define INTEL_TRANSCODER_C_DATA_M1 (0x2030 | REGS_SOUTH_TRANSCODER_PORT)
1075 #define INTEL_TRANSCODER_C_DATA_M2 (0x2038 | REGS_SOUTH_TRANSCODER_PORT)
1076 #define INTEL_TRANSCODER_A_DATA_N1 (0x0034 | REGS_SOUTH_TRANSCODER_PORT)
1077 #define INTEL_TRANSCODER_A_DATA_N2 (0x003c | REGS_SOUTH_TRANSCODER_PORT)
1078 #define INTEL_TRANSCODER_B_DATA_N1 (0x1034 | REGS_SOUTH_TRANSCODER_PORT)
1079 #define INTEL_TRANSCODER_B_DATA_N2 (0x103c | REGS_SOUTH_TRANSCODER_PORT)
1080 #define INTEL_TRANSCODER_C_DATA_N1 (0x2034 | REGS_SOUTH_TRANSCODER_PORT)
1081 #define INTEL_TRANSCODER_C_DATA_N2 (0x203c | REGS_SOUTH_TRANSCODER_PORT)
1082 #define INTEL_TRANSCODER_A_LINK_M1 (0x0040 | REGS_SOUTH_TRANSCODER_PORT)
1083 #define INTEL_TRANSCODER_A_LINK_M2 (0x0048 | REGS_SOUTH_TRANSCODER_PORT)
1084 #define INTEL_TRANSCODER_B_LINK_M1 (0x1040 | REGS_SOUTH_TRANSCODER_PORT)
1085 #define INTEL_TRANSCODER_B_LINK_M2 (0x1048 | REGS_SOUTH_TRANSCODER_PORT)
1086 #define INTEL_TRANSCODER_C_LINK_M1 (0x2040 | REGS_SOUTH_TRANSCODER_PORT)
1087 #define INTEL_TRANSCODER_C_LINK_M2 (0x2048 | REGS_SOUTH_TRANSCODER_PORT)
1088 #define INTEL_TRANSCODER_A_LINK_N1 (0x0044 | REGS_SOUTH_TRANSCODER_PORT)
1089 #define INTEL_TRANSCODER_A_LINK_N2 (0x004c | REGS_SOUTH_TRANSCODER_PORT)
1090 #define INTEL_TRANSCODER_B_LINK_N1 (0x1044 | REGS_SOUTH_TRANSCODER_PORT)
1091 #define INTEL_TRANSCODER_B_LINK_N2 (0x104c | REGS_SOUTH_TRANSCODER_PORT)
1092 #define INTEL_TRANSCODER_C_LINK_N1 (0x2044 | REGS_SOUTH_TRANSCODER_PORT)
1093 #define INTEL_TRANSCODER_C_LINK_N2 (0x204c | REGS_SOUTH_TRANSCODER_PORT)
1094 #define INTEL_TRANSCODER_MN_TU_SIZE_MASK (0x3f << 25)
1095 #define INTEL_TRANSCODER_MN_VALUE_MASK (0xffffff << 0)
1096
1097 #define INTEL_TRANSCODER_A_IMAGE_SIZE (0x001c | REGS_SOUTH_TRANSCODER_PORT)
1098 #define INTEL_TRANSCODER_B_IMAGE_SIZE (0x101c | REGS_SOUTH_TRANSCODER_PORT)
1099
1100 // TODO: Is there consolidation that could happen here with digital ports?
1101
1102 #define INTEL_ANALOG_PORT (0x1100 | REGS_SOUTH_TRANSCODER_PORT)
1103 #define INTEL_DIGITAL_PORT_A (0x1120 | REGS_SOUTH_TRANSCODER_PORT)
1104 #define INTEL_DIGITAL_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT)
1105 #define INTEL_DIGITAL_PORT_C (0x1160 | REGS_SOUTH_TRANSCODER_PORT)
1106 #define INTEL_DIGITAL_LVDS_PORT (0x1180 | REGS_SOUTH_TRANSCODER_PORT)
1107
1108 #define INTEL_HDMI_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT)
1109 #define INTEL_HDMI_PORT_C (0x1160 | REGS_SOUTH_TRANSCODER_PORT)
1110
1111 #define PCH_HDMI_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT)
1112 #define PCH_HDMI_PORT_C (0x1150 | REGS_SOUTH_TRANSCODER_PORT)
1113 #define PCH_HDMI_PORT_D (0x1160 | REGS_SOUTH_TRANSCODER_PORT)
1114
1115 #define GEN4_HDMI_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT)
1116 #define GEN4_HDMI_PORT_C (0x1160 | REGS_SOUTH_TRANSCODER_PORT)
1117 #define CHV_HDMI_PORT_D (0x116C | REGS_SOUTH_TRANSCODER_PORT)
1118
1119 // DDI Buffer Control (This replaces DP on Haswell+)
1120 #define DDI_BUF_CTL_A (0x4000 | REGS_NORTH_PIPE_AND_PORT)
1121 #define DDI_BUF_CTL_B (0x4100 | REGS_NORTH_PIPE_AND_PORT)
1122 #define DDI_BUF_CTL_C (0x4200 | REGS_NORTH_PIPE_AND_PORT)
1123 #define DDI_BUF_CTL_D (0x4300 | REGS_NORTH_PIPE_AND_PORT)
1124 #define DDI_BUF_CTL_E (0x4400 | REGS_NORTH_PIPE_AND_PORT)
1125 #define DDI_BUF_CTL_F (0x4500 | REGS_NORTH_PIPE_AND_PORT)
1126 #define DDI_BUF_CTL_G (0x4600 | REGS_NORTH_PIPE_AND_PORT)
1127 #define DDI_BUF_CTL_ENABLE (1 << 31)
1128 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
1129 #define DDI_BUF_EMP_MASK (0xf << 24)
1130 #define DDI_BUF_PORT_REVERSAL (1 << 16)
1131 #define DDI_BUF_IS_IDLE (1 << 7)
1132 #define DDI_A_4_LANES (1 << 4)
1133 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
1134 #define DDI_INIT_DISPLAY_DETECTED (1 << 0)
1135
1136 #define PIPE_DDI_FUNC_CTL_A (0x0400 | REGS_NORTH_PIPE_AND_PORT)
1137 #define PIPE_DDI_FUNC_CTL_B (0x1400 | REGS_NORTH_PIPE_AND_PORT)
1138 #define PIPE_DDI_FUNC_CTL_C (0x2400 | REGS_NORTH_PIPE_AND_PORT)
1139 #define PIPE_DDI_FUNC_CTL_EDP (0xF400 | REGS_NORTH_PIPE_AND_PORT)
1140 #define PIPE_DDI_FUNC_CTL_DSI0 (0xB400 | REGS_NORTH_PIPE_AND_PORT)
1141 #define PIPE_DDI_FUNC_CTL_DSI1 (0xBC00 | REGS_NORTH_PIPE_AND_PORT)
1142 #define PIPE_DDI_FUNC_CTL_ENABLE (1 << 31)
1143 #define PIPE_DDI_SELECT_SHIFT 28
1144 #define TGL_PIPE_DDI_SELECT_SHIFT 27
1145 #define PIPE_DDI_SELECT_PORT(x) ((x) << PIPE_DDI_SELECT_SHIFT)
1146 #define TGL_PIPE_DDI_SELECT_PORT(x) ((x) << TGL_PIPE_DDI_SELECT_SHIFT)
1147 #define PIPE_DDI_SELECT_MASK (7 << PIPE_DDI_SELECT_SHIFT)
1148 #define TGL_PIPE_DDI_SELECT_MASK (7 << TGL_PIPE_DDI_SELECT_SHIFT)
1149 #define PIPE_DDI_PORT_NONE 0
1150 #define PIPE_DDI_PORT_B 1
1151 #define PIPE_DDI_PORT_C 2
1152 #define PIPE_DDI_PORT_D 3
1153 #define PIPE_DDI_PORT_E 4
1154 #define PIPE_DDI_PORT_F 5
1155 #define PIPE_DDI_PORT_G 6
1156 #define PIPE_DDI_MODESEL_SHIFT 24
1157 #define PIPE_DDI_MODESEL_MODE(x) ((x) << PIPE_DDI_MODESEL_SHIFT)
1158 #define PIPE_DDI_MODESEL_MASK (7 << PIPE_DDI_MODESEL_SHIFT)
1159 #define PIPE_DDI_MODE_HDMI 0
1160 #define PIPE_DDI_MODE_DVI 1
1161 #define PIPE_DDI_MODE_DP_SST 2
1162 #define PIPE_DDI_MODE_DP_MST 3
1163 #define PIPE_DDI_COLOR_SHIFT 20
1164 #define PIPE_DDI_BPC(x) ((x) << PIPE_DDI_COLOR_SHIFT)
1165 #define PIPE_DDI_BPC_MASK (7 << PIPE_DDI_COLOR_SHIFT)
1166 #define PIPE_DDI_8BPC 0
1167 #define PIPE_DDI_10BPC 1
1168 #define PIPE_DDI_6BPC 2
1169 #define PIPE_DDI_12BPC 3
1170 #define PIPE_DDI_DP_WIDTH_SHIFT 1
1171 #define PIPE_DDI_DP_WIDTH_SEL(x) ((x) << PIPE_DDI_DP_WIDTH_SHIFT)
1172 #define PIPE_DDI_DP_WIDTH_MASK (7 << PIPE_DDI_DP_WIDTH_SHIFT)
1173 #define PIPE_DDI_DP_WIDTH_1 0
1174 #define PIPE_DDI_DP_WIDTH_2 1
1175 #define PIPE_DDI_DP_WIDTH_4 2
1176
1177 // DP_A always @ 6xxxx, DP_B-DP_D move with PCH
1178 #define INTEL_DISPLAY_PORT_A (0x4000 | REGS_NORTH_PIPE_AND_PORT)
1179 #define INTEL_DISPLAY_PORT_B (0x4100 | REGS_SOUTH_TRANSCODER_PORT)
1180 #define INTEL_DISPLAY_PORT_C (0x4200 | REGS_SOUTH_TRANSCODER_PORT)
1181 #define INTEL_DISPLAY_PORT_D (0x4300 | REGS_SOUTH_TRANSCODER_PORT)
1182
1183 #define INTEL_DISP_PORTA_SNB_PIPE_SHIFT 30
1184 #define INTEL_DISP_PORTA_SNB_PIPE_MASK (1 << INTEL_DISP_PORTA_SNB_PIPE_SHIFT)
1185 #define INTEL_DISP_PORTA_SNB_PIPE_A 0
1186 #define INTEL_DISP_PORTA_SNB_PIPE_B 1
1187 #define INTEL_DISP_PORTA_IVB_PIPE_SHIFT 29
1188 #define INTEL_DISP_PORTA_IVB_PIPE_MASK (3 << INTEL_DISP_PORTA_IVB_PIPE_SHIFT)
1189 #define INTEL_DISP_PORTA_IVB_PIPE_A 0
1190 #define INTEL_DISP_PORTA_IVB_PIPE_B 1
1191 #define INTEL_DISP_PORTA_IVB_PIPE_C 2
1192
1193 #define INTEL_DISP_PORT_WIDTH_SHIFT 19
1194 #define INTEL_DISP_PORT_WIDTH_MASK (7 << INTEL_DISP_PORT_WIDTH_SHIFT)
1195 #define INTEL_DISP_PORT_WIDTH_1 0
1196 #define INTEL_DISP_PORT_WIDTH_2 1
1197 #define INTEL_DISP_PORT_WIDTH_4 3
1198 #define INTEL_DISP_EDP_PLL_FREQ_SHIFT 16
1199 #define INTEL_DISP_EDP_PLL_FREQ_MASK (3 << INTEL_DISP_EDP_PLL_FREQ_SHIFT)
1200 #define INTEL_DISP_EDP_PLL_FREQ_270 0
1201 #define INTEL_DISP_EDP_PLL_FREQ_162 1
1202
1203 #define INTEL_TRANSCODER_A_DP_CTL (0x0300 | REGS_SOUTH_TRANSCODER_PORT)
1204 #define INTEL_TRANSCODER_B_DP_CTL (0x1300 | REGS_SOUTH_TRANSCODER_PORT)
1205 #define INTEL_TRANSCODER_C_DP_CTL (0x2300 | REGS_SOUTH_TRANSCODER_PORT)
1206
1207 #define INTEL_TRANS_DP_COLOR_SHIFT 9
1208 #define INTEL_TRANS_DP_BPC(x) ((x) << INTEL_TRANS_DP_COLOR_SHIFT)
1209 #define INTEL_TRANS_DP_BPC_MASK (7 << INTEL_TRANS_DP_COLOR_SHIFT)
1210 #define INTEL_TRANS_DP_PORT_SHIFT 29
1211 #define INTEL_TRANS_DP_PORT(x) ((x) << INTEL_TRANS_DP_PORT_SHIFT)
1212 #define INTEL_TRANS_DP_PORT_MASK (3 << INTEL_TRANS_DP_PORT_SHIFT)
1213 #define INTEL_TRANS_DP_PORT_B 0
1214 #define INTEL_TRANS_DP_PORT_C 1
1215 #define INTEL_TRANS_DP_PORT_D 2
1216 #define INTEL_TRANS_DP_PORT_NONE 3
1217
1218 // Unless you're a damn Valley/CherryView unicorn :-(
1219 #define VLV_DISPLAY_PORT_B (VLV_DISPLAY_BASE + 0x64100)
1220 #define VLV_DISPLAY_PORT_C (VLV_DISPLAY_BASE + 0x64200)
1221 #define CHV_DISPLAY_PORT_D (VLV_DISPLAY_BASE + 0x64300)
1222
1223 // DP AUX channels
1224 #define _DPA_AUX_CH_CTL (0x4010 | REGS_NORTH_PIPE_AND_PORT)
1225 #define _DPA_AUX_CH_DATA1 (0x4014 | REGS_NORTH_PIPE_AND_PORT)
1226 #define _DPB_AUX_CH_CTL (0x4110 | REGS_NORTH_PIPE_AND_PORT)
1227 #define _DPB_AUX_CH_DATA1 (0x4114 | REGS_NORTH_PIPE_AND_PORT)
1228 #define DP_AUX_CH_CTL(aux) \
1229 (_DPA_AUX_CH_CTL + (_DPB_AUX_CH_CTL - _DPA_AUX_CH_CTL) * aux)
1230 #define DP_AUX_CH_DATA(aux, i) \
1231 (_DPA_AUX_CH_DATA1 + (_DPB_AUX_CH_DATA1 - _DPA_AUX_CH_DATA1) * aux + i * 4)
1232 #define _PCH_DPB_AUX_CH_CTL (0x4110 | REGS_SOUTH_TRANSCODER_PORT)
1233 #define _PCH_DPB_AUX_CH_DATA1 (0x4114 | REGS_SOUTH_TRANSCODER_PORT)
1234 #define _PCH_DPC_AUX_CH_CTL (0x4210 | REGS_SOUTH_TRANSCODER_PORT)
1235 #define _PCH_DPC_AUX_CH_DATA1 (0x4214 | REGS_SOUTH_TRANSCODER_PORT)
1236 #define PCH_DP_AUX_CH_CTL(aux) \
1237 (_PCH_DPB_AUX_CH_CTL + (_PCH_DPC_AUX_CH_CTL - _PCH_DPB_AUX_CH_CTL) * (aux - AUX_CH_B))
1238 #define PCH_DP_AUX_CH_DATA(aux, i) \
1239 (_PCH_DPB_AUX_CH_DATA1 + (_PCH_DPC_AUX_CH_DATA1 - _PCH_DPB_AUX_CH_DATA1) * (aux - AUX_CH_B) \
1240 + i * 4)
1241
1242 #define INTEL_DP_AUX_CTL_BUSY (1 << 31)
1243 #define INTEL_DP_AUX_CTL_DONE (1 << 30)
1244 #define INTEL_DP_AUX_CTL_INTERRUPT (1 << 29)
1245 #define INTEL_DP_AUX_CTL_TIMEOUT_ERROR (1 << 28)
1246 #define INTEL_DP_AUX_CTL_TIMEOUT_400us (0 << 26)
1247 #define INTEL_DP_AUX_CTL_TIMEOUT_600us (1 << 26)
1248 #define INTEL_DP_AUX_CTL_TIMEOUT_800us (2 << 26)
1249 #define INTEL_DP_AUX_CTL_TIMEOUT_1600us (3 << 26)
1250 #define INTEL_DP_AUX_CTL_TIMEOUT_MASK (3 << 26)
1251 #define INTEL_DP_AUX_CTL_RECEIVE_ERROR (1 << 25)
1252 #define INTEL_DP_AUX_CTL_MSG_SIZE_MASK (0x1f << 20)
1253 #define INTEL_DP_AUX_CTL_MSG_SIZE_SHIFT 20
1254 #define INTEL_DP_AUX_CTL_PRECHARGE_2US_MASK (0xf << 16)
1255 #define INTEL_DP_AUX_CTL_PRECHARGE_2US_SHIFT 16
1256 #define INTEL_DP_AUX_CTL_BIT_CLOCK_2X_MASK (0x7ff)
1257 #define INTEL_DP_AUX_CTL_BIT_CLOCK_2X_SHIFT 0
1258 #define INTEL_DP_AUX_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
1259 #define INTEL_DP_AUX_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
1260
1261 // planes
1262 #define INTEL_PIPE_ENABLED (1UL << 31)
1263 #define INTEL_PIPE_STATE (1UL << 30)
1264
1265 #define INTEL_PLANE_OFFSET 0x1000
1266
1267 #define INTEL_DISPLAY_A_PIPE_CONTROL (0x0008 | REGS_NORTH_PLANE_CONTROL)
1268 #define INTEL_DISPLAY_B_PIPE_CONTROL (0x1008 | REGS_NORTH_PLANE_CONTROL)
1269 #define INTEL_DISPLAY_C_PIPE_CONTROL (0x2008 | REGS_NORTH_PLANE_CONTROL)
1270 #define INTEL_DISPLAY_A_PIPE_STATUS (0x0024 | REGS_NORTH_PLANE_CONTROL)
1271 #define INTEL_DISPLAY_B_PIPE_STATUS (0x1024 | REGS_NORTH_PLANE_CONTROL)
1272
1273 #define INTEL_DISPLAY_A_PIPE_WATERMARK (0x5100 | REGS_NORTH_PLANE_CONTROL)
1274 #define INTEL_DISPLAY_B_PIPE_WATERMARK (0x5104 | REGS_NORTH_PLANE_CONTROL)
1275 #define INTEL_DISPLAY_C_PIPE_WATERMARK (0x5200 | REGS_NORTH_PLANE_CONTROL)
1276
1277 #define DISPLAY_PIPE_VBLANK_ENABLED (1UL << 17)
1278 #define DISPLAY_PIPE_VBLANK_STATUS (1UL << 1)
1279
1280 #define INTEL_DISPLAY_A_CONTROL (0x0180 | REGS_NORTH_PLANE_CONTROL)
1281 #define INTEL_DISPLAY_A_BASE (0x0184 | REGS_NORTH_PLANE_CONTROL)
1282 #define INTEL_DISPLAY_A_BYTES_PER_ROW (0x0188 | REGS_NORTH_PLANE_CONTROL)
1283 #define INTEL_DISPLAY_A_POS (0x018c | REGS_NORTH_PLANE_CONTROL)
1284 // reserved on A
1285 #define INTEL_DISPLAY_A_IMAGE_SIZE (0x0190 | REGS_NORTH_PLANE_CONTROL)
1286 #define INTEL_DISPLAY_A_SURFACE (0x019c | REGS_NORTH_PLANE_CONTROL)
1287 #define INTEL_DISPLAY_A_OFFSET_HAS (0x01a4 | REGS_NORTH_PLANE_CONTROL)
1288 // i965 and up only
1289
1290 #define INTEL_DISPLAY_B_CONTROL (0x1180 | REGS_NORTH_PLANE_CONTROL)
1291 #define INTEL_DISPLAY_B_BASE (0x1184 | REGS_NORTH_PLANE_CONTROL)
1292 #define INTEL_DISPLAY_B_BYTES_PER_ROW (0x1188 | REGS_NORTH_PLANE_CONTROL)
1293 #define INTEL_DISPLAY_B_POS (0x118c | REGS_NORTH_PLANE_CONTROL)
1294 #define INTEL_DISPLAY_B_IMAGE_SIZE (0x1190 | REGS_NORTH_PLANE_CONTROL)
1295 #define INTEL_DISPLAY_B_SURFACE (0x119c | REGS_NORTH_PLANE_CONTROL)
1296 #define INTEL_DISPLAY_B_OFFSET_HAS (0x11a4 | REGS_NORTH_PLANE_CONTROL)
1297 // i965 and up only
1298
1299 // INTEL_DISPLAY_A_CONTROL source pixel format
1300 #define DISPLAY_CONTROL_ENABLED (1UL << 31)
1301 #define DISPLAY_CONTROL_GAMMA (1UL << 30)
1302 #define DISPLAY_CONTROL_COLOR_MASK (0x0fUL << 26)
1303 #define DISPLAY_CONTROL_CMAP8 (2UL << 26)
1304 #define DISPLAY_CONTROL_RGB15 (4UL << 26)
1305 #define DISPLAY_CONTROL_RGB16 (5UL << 26)
1306 #define DISPLAY_CONTROL_RGB32 (6UL << 26)
1307 #define DISPLAY_CONTROL_RGB64 (0x0cUL << 26)
1308 // Skylake
1309 #define DISPLAY_CONTROL_COLOR_MASK_SKY (0x0fUL << 24)
1310 #define DISPLAY_CONTROL_CMAP8_SKY (0x0cUL << 24)
1311 #define DISPLAY_CONTROL_RGB15_SKY (0x0eUL << 24)
1312 #define DISPLAY_CONTROL_RGB16_SKY (0x0eUL << 24)
1313 #define DISPLAY_CONTROL_RGB32_SKY (0x04UL << 24)
1314 #define DISPLAY_CONTROL_RGB64_SKY (0x06UL << 24)
1315
1316 // INTEL_DISPLAY_A_PIPE_CONTROL ILK+
1317 #define INTEL_PIPE_DITHER_TYPE_MASK (0x0000000c)
1318 #define INTEL_PIPE_DITHER_TYPE_SP (0 << 2)
1319 #define INTEL_PIPE_DITHER_TYPE_ST1 (1 << 2)
1320 #define INTEL_PIPE_DITHER_TYPE_ST2 (2 << 2)
1321 #define INTEL_PIPE_DITHER_TYPE_TEMP (3 << 2)
1322 #define INTEL_PIPE_DITHER_EN (1 << 4)
1323 #define INTEL_PIPE_COLOR_SHIFT 5
1324 #define INTEL_PIPE_BPC(x) ((x) << INTEL_PIPE_COLOR_SHIFT)
1325 #define INTEL_PIPE_BPC_MASK (7 << INTEL_PIPE_COLOR_SHIFT)
1326 #define INTEL_PIPE_8BPC 0
1327 #define INTEL_PIPE_10BPC 1
1328 #define INTEL_PIPE_6BPC 2
1329 #define INTEL_PIPE_12BPC 3
1330 #define INTEL_PIPE_PROGRESSIVE (0 << 21)
1331
1332 // cursors
1333 #define INTEL_CURSOR_CONTROL (0x0080 | REGS_NORTH_PLANE_CONTROL)
1334 #define INTEL_CURSOR_BASE (0x0084 | REGS_NORTH_PLANE_CONTROL)
1335 #define INTEL_CURSOR_POSITION (0x0088 | REGS_NORTH_PLANE_CONTROL)
1336 #define INTEL_CURSOR_PALETTE (0x0090 | REGS_NORTH_PLANE_CONTROL)
1337 // (- 0x009f)
1338 #define INTEL_CURSOR_SIZE (0x00a0 | REGS_NORTH_PLANE_CONTROL)
1339 #define CURSOR_ENABLED (1UL << 31)
1340 #define CURSOR_FORMAT_2_COLORS (0UL << 24)
1341 #define CURSOR_FORMAT_3_COLORS (1UL << 24)
1342 #define CURSOR_FORMAT_4_COLORS (2UL << 24)
1343 #define CURSOR_FORMAT_ARGB (4UL << 24)
1344 #define CURSOR_FORMAT_XRGB (5UL << 24)
1345 #define CURSOR_POSITION_NEGATIVE 0x8000
1346 #define CURSOR_POSITION_MASK 0x3fff
1347
1348 // palette registers
1349 #define INTEL_DISPLAY_A_PALETTE (0xa000 | REGS_NORTH_SHARED)
1350 #define INTEL_DISPLAY_B_PALETTE (0xa800 | REGS_NORTH_SHARED)
1351
1352 // Ironlake PCH reference clk control
1353 #define PCH_DREF_CONTROL (0x6200 | REGS_SOUTH_SHARED)
1354 #define DREF_CONTROL_MASK 0x7fc3
1355 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13)
1356 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13)
1357 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13)
1358 #define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13)
1359 #define DREF_SSC_SOURCE_DISABLE (0 << 11)
1360 #define DREF_SSC_SOURCE_ENABLE (2 << 11)
1361 #define DREF_SSC_SOURCE_MASK (3 << 11)
1362 #define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9)
1363 #define DREF_NONSPREAD_CK505_ENABLE (1 << 9)
1364 #define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9)
1365 #define DREF_NONSPREAD_SOURCE_MASK (3 << 9)
1366 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7)
1367 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7)
1368 #define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7)
1369 #define DREF_SSC4_DOWNSPREAD (0 << 6)
1370 #define DREF_SSC4_CENTERSPREAD (1 << 6)
1371 #define DREF_SSC1_DISABLE (0 << 1)
1372 #define DREF_SSC1_ENABLE (1 << 1)
1373 #define DREF_SSC4_DISABLE (0 << 0)
1374 #define DREF_SSC4_ENABLE (1 << 0)
1375
1376 #define PCH_RAWCLK_FREQ (0x6204 | REGS_SOUTH_SHARED)
1377 #define RAWCLK_FREQ_MASK 0x3ff
1378
1379 // PLL registers
1380 // Multiplier Divisor
1381 #define INTEL_DISPLAY_A_PLL (0x6014 | REGS_SOUTH_SHARED)
1382 #define INTEL_DISPLAY_B_PLL (0x6018 | REGS_SOUTH_SHARED)
1383 #define INTEL_DISPLAY_A_PLL_MD (0x601C | REGS_SOUTH_SHARED)
1384 #define INTEL_DISPLAY_B_PLL_MD (0x6020 | REGS_SOUTH_SHARED)
1385 #define CHV_DISPLAY_C_PLL (0x6030 | REGS_SOUTH_SHARED)
1386 #define CHV_DISPLAY_B_PLL_MD (0x603C | REGS_SOUTH_SHARED)
1387
1388 #define INTEL_DISPLAY_A_PLL_DIVISOR_0 (0x6040 | REGS_SOUTH_SHARED)
1389 #define INTEL_DISPLAY_A_PLL_DIVISOR_1 (0x6044 | REGS_SOUTH_SHARED)
1390 #define INTEL_DISPLAY_B_PLL_DIVISOR_0 (0x6048 | REGS_SOUTH_SHARED)
1391 #define INTEL_DISPLAY_B_PLL_DIVISOR_1 (0x604c | REGS_SOUTH_SHARED)
1392
1393 #define SNB_DPLL_SEL (0x7000 | REGS_SOUTH_SHARED)
1394
1395 // i2c bit banging interface
1396 #define INTEL_I2C_IO_A (0x5010 | REGS_SOUTH_SHARED)
1397 #define INTEL_I2C_IO_B (0x5014 | REGS_SOUTH_SHARED)
1398 #define INTEL_I2C_IO_C (0x5018 | REGS_SOUTH_SHARED)
1399 #define INTEL_I2C_IO_D (0x501c | REGS_SOUTH_SHARED)
1400 #define INTEL_I2C_IO_E (0x5020 | REGS_SOUTH_SHARED)
1401 #define INTEL_I2C_IO_F (0x5024 | REGS_SOUTH_SHARED)
1402 #define INTEL_I2C_IO_G (0x5028 | REGS_SOUTH_SHARED)
1403 #define INTEL_I2C_IO_H (0x502c | REGS_SOUTH_SHARED)
1404 #define INTEL_I2C_IO_I (0x5030 | REGS_SOUTH_SHARED)
1405 #define INTEL_I2C_IO_J (0x5034 | REGS_SOUTH_SHARED)
1406 #define INTEL_I2C_IO_K (0x5038 | REGS_SOUTH_SHARED)
1407 #define INTEL_I2C_IO_L (0x503c | REGS_SOUTH_SHARED)
1408 #define INTEL_I2C_IO_M (0x5040 | REGS_SOUTH_SHARED)
1409 #define INTEL_I2C_IO_N (0x5044 | REGS_SOUTH_SHARED)
1410 // i2c hardware controller
1411 #define INTEL_GMBUS0 (0x5100 | REGS_SOUTH_SHARED)
1412 #define INTEL_GMBUS4 (0x5110 | REGS_SOUTH_SHARED)
1413
1414 #define I2C_CLOCK_DIRECTION_MASK (1 << 0)
1415 #define I2C_CLOCK_DIRECTION_OUT (1 << 1)
1416 #define I2C_CLOCK_VALUE_MASK (1 << 2)
1417 #define I2C_CLOCK_VALUE_OUT (1 << 3)
1418 #define I2C_CLOCK_VALUE_IN (1 << 4)
1419 #define I2C_DATA_DIRECTION_MASK (1 << 8)
1420 #define I2C_DATA_DIRECTION_OUT (1 << 9)
1421 #define I2C_DATA_VALUE_MASK (1 << 10)
1422 #define I2C_DATA_VALUE_OUT (1 << 11)
1423 #define I2C_DATA_VALUE_IN (1 << 12)
1424 #define I2C_RESERVED ((1 << 13) | (1 << 5))
1425
1426 // gpu block clock gating disable bits
1427 #define INTEL_DSPCLK_GATE_D (0x2020 | REGS_SOUTH_SHARED)
1428 #define PCH_GMBUSUNIT_CLK_GATE_DIS (1UL << 31)
1429 #define INTEL_GEN9_CLKGATE_DIS_4 (0x653c | REGS_NORTH_SHARED)
1430 #define BXT_GMBUSUNIT_CLK_GATE_DIS (1 << 14)
1431
1432 // gpu power wells (confirmed skylake)
1433 #define INTEL_PWR_WELL_CTL_1_BIOS (0x5400 | REGS_NORTH_SHARED)
1434 #define INTEL_PWR_WELL_CTL_2_DRIVER (0x5404 | REGS_NORTH_SHARED)
1435
1436 #define HSW_PWR_WELL_CTL_REQ(i) (0x2 << ((2 * i)))
1437 #define HSW_PWR_WELL_CTL_STATE(i) (0x1 << ((2 * i)))
1438
1439 #define HSW_PWR_WELL_CTL1 INTEL_PWR_WELL_CTL_1_BIOS
1440 #define HSW_PWR_WELL_CTL2 INTEL_PWR_WELL_CTL_2_DRIVER
1441 #define HSW_PWR_WELL_CTL3 (0x5408 | REGS_NORTH_SHARED)
1442 #define HSW_PWR_WELL_CTL4 (0x540c | REGS_NORTH_SHARED)
1443
1444 #define ICL_PWR_WELL_CTL_AUX1 (0x5440 | REGS_NORTH_SHARED)
1445 #define ICL_PWR_WELL_CTL_AUX2 (0x5444 | REGS_NORTH_SHARED)
1446 #define ICL_PWR_WELL_CTL_AUX4 (0x544c | REGS_NORTH_SHARED)
1447
1448 #define ICL_PWR_WELL_CTL_DDI1 (0x5450 | REGS_NORTH_SHARED)
1449 #define ICL_PWR_WELL_CTL_DDI2 (0x5454 | REGS_NORTH_SHARED)
1450 #define ICL_PWR_WELL_CTL_DDI4 (0x545c | REGS_NORTH_SHARED)
1451
1452 // gpu pll enable registers (confirmed skylake)
1453 #define INTEL_WRPLL_CTL_1_DPLL2 (0x6040 | REGS_NORTH_SHARED)
1454 #define INTEL_WRPLL_CTL_2_DPLL3 (0x6060 | REGS_NORTH_SHARED)
1455 #define WRPLL_PLL_ENABLE (1 << 31)
1456
1457 // TODO: on IronLake this is in the north shared block at 0x41000
1458 #define INTEL_VGA_DISPLAY_CONTROL (0x1400 | REGS_NORTH_PLANE_CONTROL)
1459 #define VGA_DISPLAY_DISABLED (1UL << 31)
1460
1461 // LVDS panel
1462 #define INTEL_PANEL_STATUS (0x1200 | REGS_NORTH_PIPE_AND_PORT)
1463 #define INTEL_PANEL_CONTROL (0x1204 | REGS_NORTH_PIPE_AND_PORT)
1464 #define INTEL_PANEL_FIT_CONTROL (0x1230 | REGS_NORTH_PIPE_AND_PORT)
1465 #define INTEL_PANEL_FIT_RATIOS (0x1234 | REGS_NORTH_PIPE_AND_PORT)
1466
1467 // LVDS on IronLake and up
1468 #define PCH_PANEL_STATUS (0x7200 | REGS_SOUTH_SHARED)
1469 #define PCH_PANEL_CONTROL (0x7204 | REGS_SOUTH_SHARED)
1470 #define PCH_PANEL_ON_DELAYS (0x7208 | REGS_SOUTH_SHARED)
1471 #define PCH_PANEL_OFF_DELAYS (0x720c | REGS_SOUTH_SHARED)
1472 #define PCH_PANEL_DIVISOR (0x7210 | REGS_SOUTH_SHARED)
1473 #define PCH_LVDS_DETECTED (1 << 1)
1474
1475 #define PANEL_STATUS_POWER_ON (1UL << 31)
1476 #define PANEL_CONTROL_POWER_TARGET_OFF (0UL << 0)
1477 #define PANEL_CONTROL_POWER_TARGET_ON (1UL << 0)
1478 #define PANEL_CONTROL_POWER_TARGET_RST (1UL << 1)
1479 #define PANEL_REGISTER_UNLOCK (0xabcd << 16)
1480
1481 // PCH_PANEL_ON_DELAYS
1482 #define PANEL_DELAY_PORT_SELECT_MASK (3 << 30)
1483 #define PANEL_DELAY_PORT_SELECT_LVDS (0 << 30)
1484 #define PANEL_DELAY_PORT_SELECT_DPA (1 << 30)
1485 #define PANEL_DELAY_PORT_SELECT_DPC (2 << 30)
1486 #define PANEL_DELAY_PORT_SELECT_DPD (3 << 30)
1487
1488 // PCH_PANEL_DIVISOR
1489 #define PANEL_DIVISOR_REFERENCE_DIV_MASK 0xffffff00
1490 #define PANEL_DIVISOR_REFERENCE_DIV_SHIFT 8
1491 #define PANEL_DIVISOR_POW_CYCLE_DLY_MASK 0x1f
1492 #define PANEL_DIVISOR_POW_CYCLE_DLY_SHIFT 0x1f
1493
1494 // Backlight control registers
1495 // These have moved around, initially they were per pipe, then they were moved in the "north" part
1496 // of the PCH with a single backlight control (independant of pipes), and then moved again to the
1497 // "south" part of the PCH, with a simplified register layout.
1498 #define PCH_BLC_PWM_CTL2 (0x8250 | REGS_NORTH_SHARED) // Linux BLC_PWM_CPU_CTL2
1499 #define PCH_BLC_PWM_CTL (0x8254 | REGS_NORTH_SHARED) // Linux BLC_PWM_CPU_CTL
1500
1501 // Kaby Lake/Sunrisepoint
1502 #define BLC_PWM_PCH_CTL1 (0x8250 | REGS_SOUTH_SHARED) // Enable with bit 31
1503 #define BLC_PWM_PCH_CTL2 (0x8254 | REGS_SOUTH_SHARED) // Duty Cycle and Period
1504
1505 // Devices after Cannonlake have a new register layout, with separate registers for the period
1506 // and duty cycle instead of having two 16bit values in a 32bit register
1507 #define PCH_SOUTH_BLC_PWM_CONTROL (0x8250 | REGS_SOUTH_SHARED) // Linux _BXT_BLC_PWM_CTL1
1508 #define PCH_SOUTH_BLC_PWM_PERIOD (0x8254 | REGS_SOUTH_SHARED) // Linux _BXT_BLC_PWM_FREQ1
1509 #define PCH_SOUTH_BLC_PWM_DUTY_CYCLE (0x8258 | REGS_SOUTH_SHARED) // Linux _BXT_BLC_PWM_DUTY1
1510
1511 #define MCH_BLC_PWM_CTL (0x1254 | REGS_NORTH_PIPE_AND_PORT)
1512 // Linux VLV_BLC_PWM_CTL (one register per pipe) or BLC_PWM_CTL (a single register that can be
1513 // programmed for use on either pipe)
1514 #define BLM_LEGACY_MODE (1 << 16)
1515
1516 // ring buffer commands
1517
1518 #define COMMAND_NOOP 0x00
1519 #define COMMAND_WAIT_FOR_EVENT (0x03 << 23)
1520 #define COMMAND_WAIT_FOR_OVERLAY_FLIP (1 << 16)
1521
1522 #define COMMAND_FLUSH (0x04 << 23)
1523
1524 // overlay flip
1525 #define COMMAND_OVERLAY_FLIP (0x11 << 23)
1526 #define COMMAND_OVERLAY_CONTINUE (0 << 21)
1527 #define COMMAND_OVERLAY_ON (1 << 21)
1528 #define COMMAND_OVERLAY_OFF (2 << 21)
1529 #define OVERLAY_UPDATE_COEFFICIENTS 0x1
1530
1531 // 2D acceleration
1532 #define XY_COMMAND_SOURCE_BLIT 0x54c00006
1533 #define XY_COMMAND_COLOR_BLIT 0x54000004
1534 #define XY_COMMAND_SETUP_MONO_PATTERN 0x44400007
1535 #define XY_COMMAND_SCANLINE_BLIT 0x49400001
1536 #define COMMAND_COLOR_BLIT 0x50000003
1537 #define COMMAND_BLIT_RGBA 0x00300000
1538
1539 #define COMMAND_MODE_SOLID_PATTERN 0x80
1540 #define COMMAND_MODE_CMAP8 0x00
1541 #define COMMAND_MODE_RGB15 0x02
1542 #define COMMAND_MODE_RGB16 0x01
1543 #define COMMAND_MODE_RGB32 0x03
1544
1545 // overlay
1546 #define INTEL_OVERLAY_UPDATE 0x30000
1547 #define INTEL_OVERLAY_TEST 0x30004
1548 #define INTEL_OVERLAY_STATUS 0x30008
1549 #define INTEL_OVERLAY_EXTENDED_STATUS 0x3000c
1550 #define INTEL_OVERLAY_GAMMA_5 0x30010
1551 #define INTEL_OVERLAY_GAMMA_4 0x30014
1552 #define INTEL_OVERLAY_GAMMA_3 0x30018
1553 #define INTEL_OVERLAY_GAMMA_2 0x3001c
1554 #define INTEL_OVERLAY_GAMMA_1 0x30020
1555 #define INTEL_OVERLAY_GAMMA_0 0x30024
1556
1557 // FDI - Flexible Display Interface, the interface between the (CPU-internal)
1558 // GPU and the PCH display outputs. Proprietary interface, based on DisplayPort
1559 // though, so similar link training and all...
1560 // There's an FDI transmitter (TX) on the CPU and an FDI receiver (RX) on the
1561 // PCH for each display pipe.
1562 // FDI receiver A is hooked up to transcoder A, FDI receiver B is hooked up to
1563 // transcoder B, so we have the same mapping as with the display pipes.
1564 #define _FDI_RXA_CTL 0xf000c
1565 #define _FDI_RXB_CTL 0xf100c
1566 #define FDI_RX_CTL(pipe) (_FDI_RXA_CTL + (_FDI_RXB_CTL - _FDI_RXA_CTL) * (pipe - INTEL_PIPE_A))
1567 #define _FDI_RXA_MISC 0xf0010
1568 #define _FDI_RXB_MISC 0xf1010
1569 #define FDI_RX_MISC(pipe) (_FDI_RXA_MISC + (_FDI_RXB_MISC - _FDI_RXA_MISC) * (pipe - INTEL_PIPE_A))
1570 #define _FDI_RXA_IIR 0xf0014
1571 #define _FDI_RXB_IIR 0xf1014
1572 #define FDI_RX_IIR(pipe) (_FDI_RXA_IIR + (_FDI_RXB_IIR - _FDI_RXA_IIR) * (pipe - INTEL_PIPE_A))
1573 #define _FDI_RXA_IMR 0xf0018
1574 #define _FDI_RXB_IMR 0xf1018
1575 #define FDI_RX_IMR(pipe) (_FDI_RXA_IMR + (_FDI_RXB_IMR - _FDI_RXA_IMR) * (pipe - INTEL_PIPE_A))
1576
1577 #define FDI_RX_ENABLE (1 << 31)
1578 #define FDI_RX_PLL_ENABLED (1 << 13)
1579
1580 #define FDI_RX_LINK_COLOR_SHIFT 16
1581 #define FDI_RX_LINK_BPC(x) ((x) << FDI_RX_LINK_COLOR_SHIFT)
1582 #define FDI_RX_LINK_BPC_MASK (7 << FDI_RX_LINK_COLOR_SHIFT)
1583
1584 // Transcoder - same base as FDI_RX
1585 #define PCH_TRANS_CONF_A 0x0008
1586 #define PCH_TRANS_CONF_B 0x1008
1587 #define PCH_TRANS_CONF_C 0x2008
1588
1589 // Transcoder - skylake DDI
1590 #define DDI_SKL_TRANS_CONF_A (0x0008 | REGS_NORTH_PLANE_CONTROL)
1591 #define DDI_SKL_TRANS_CONF_B (0x1008 | REGS_NORTH_PLANE_CONTROL)
1592 #define DDI_SKL_TRANS_CONF_C (0x2008 | REGS_NORTH_PLANE_CONTROL)
1593 #define DDI_SKL_TRANS_CONF_EDP (0xf008 | REGS_NORTH_PLANE_CONTROL)
1594
1595 #define TRANS_ENABLE (1 << 31)
1596 #define TRANS_ENABLED (1 << 30)
1597
1598 // FDI_tX interrupt register
1599 #define FDI_RX_INTER_LANE_ALIGN (1 << 10)
1600 #define FDI_RX_SYMBOL_LOCK (1 << 9)
1601 #define FDI_RX_BIT_LOCK (1 << 8)
1602 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1 << 7)
1603 #define FDI_RX_FS_CODE_ERR (1 << 6)
1604 #define FDI_RX_FE_CODE_ERR (1 << 5)
1605 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1 << 4)
1606 #define FDI_RX_HDCP_LINK_FAIL (1 << 3)
1607 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1 << 2)
1608 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1 << 1)
1609 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1 << 0)
1610
1611 #define FDI_FS_ERRC_ENABLE (1 << 27)
1612 #define FDI_FE_ERRC_ENABLE (1 << 26)
1613
1614 #define _FDI_RXA_TUSIZE1 0xf0030
1615 #define _FDI_RXA_TUSIZE2 0xf0038
1616 #define _FDI_RXB_TUSIZE1 0xf1030
1617 #define _FDI_RXB_TUSIZE2 0xf1038
1618 #define FDI_RX_TUSIZE1(pipe) (_FDI_RXA_TUSIZE1 + (_FDI_RXB_TUSIZE1 - _FDI_RXA_TUSIZE1) * (pipe - INTEL_PIPE_A))
1619 #define FDI_RX_TUSIZE2(pipe) (_FDI_RXA_TUSIZE2 + (_FDI_RXB_TUSIZE2 - _FDI_RXA_TUSIZE2) * (pipe - INTEL_PIPE_A))
1620 #define FDI_RX_TRANS_UNIT_SIZE(x) ((x - 1) << 25)
1621 #define FDI_RX_TRANS_UNIT_MASK 0x7e000000
1622
1623 #define FDI_RX_ENHANCE_FRAME_ENABLE (1 << 6)
1624 #define FDI_RX_CLOCK_MASK (1 << 4)
1625 #define FDI_RX_CLOCK_RAW (0 << 4)
1626 #define FDI_RX_CLOCK_PCD (1 << 4)
1627
1628 // FDI RX MISC
1629 #define FDI_RX_PWRDN_LANE1_MASK (3 << 26)
1630 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x) << 26)
1631 #define FDI_RX_PWRDN_LANE0_MASK (3 << 24)
1632 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x) << 24)
1633 #define FDI_RX_TP1_TO_TP2_48 (2 << 20)
1634 #define FDI_RX_TP1_TO_TP2_64 (3 << 20)
1635 #define FDI_RX_FDI_DELAY_90 (0x90 << 0)
1636
1637 #define _FDI_TXA_CTL (0x0100 | REGS_NORTH_PIPE_AND_PORT)
1638 #define _FDI_TXB_CTL (0x1100 | REGS_NORTH_PIPE_AND_PORT)
1639 #define FDI_TX_CTL(pipe) (_FDI_TXA_CTL + (_FDI_TXB_CTL - _FDI_TXA_CTL) * (pipe - INTEL_PIPE_A))
1640 #define FDI_TX_ENABLE (1 << 31)
1641 #define FDI_LINK_TRAIN_PATTERN_1 (0 << 28)
1642 #define FDI_LINK_TRAIN_PATTERN_2 (1 << 28)
1643 #define FDI_LINK_TRAIN_PATTERN_IDLE (2 << 28)
1644 #define FDI_LINK_TRAIN_NONE (3 << 28)
1645 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0 << 25)
1646 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1 << 25)
1647 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2 << 25)
1648 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3 << 25)
1649 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22)
1650 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22)
1651 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22)
1652 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22)
1653
1654 // FDI/PIPE M/N DATA AND LINK VALUES (refreshrate)
1655 #define PCH_FDI_PIPE_A_DATA_M1 (0x0030 | REGS_NORTH_PIPE_AND_PORT)
1656 #define PCH_FDI_PIPE_A_DATA_M2 (0x0038 | REGS_NORTH_PIPE_AND_PORT)
1657 #define PCH_FDI_PIPE_B_DATA_M1 (0x1030 | REGS_NORTH_PIPE_AND_PORT)
1658 #define PCH_FDI_PIPE_B_DATA_M2 (0x1038 | REGS_NORTH_PIPE_AND_PORT)
1659 #define PCH_FDI_PIPE_C_DATA_M1 (0x2030 | REGS_NORTH_PIPE_AND_PORT)
1660 #define PCH_FDI_PIPE_C_DATA_M2 (0x2038 | REGS_NORTH_PIPE_AND_PORT)
1661 #define PCH_FDI_PIPE_A_DATA_N1 (0x0034 | REGS_NORTH_PIPE_AND_PORT)
1662 #define PCH_FDI_PIPE_A_DATA_N2 (0x003c | REGS_NORTH_PIPE_AND_PORT)
1663 #define PCH_FDI_PIPE_B_DATA_N1 (0x1034 | REGS_NORTH_PIPE_AND_PORT)
1664 #define PCH_FDI_PIPE_B_DATA_N2 (0x103c | REGS_NORTH_PIPE_AND_PORT)
1665 #define PCH_FDI_PIPE_C_DATA_N1 (0x2034 | REGS_NORTH_PIPE_AND_PORT)
1666 #define PCH_FDI_PIPE_C_DATA_N2 (0x203c | REGS_NORTH_PIPE_AND_PORT)
1667 #define PCH_FDI_PIPE_A_LINK_M1 (0x0040 | REGS_NORTH_PIPE_AND_PORT)
1668 #define PCH_FDI_PIPE_A_LINK_M2 (0x0048 | REGS_NORTH_PIPE_AND_PORT)
1669 #define PCH_FDI_PIPE_B_LINK_M1 (0x1040 | REGS_NORTH_PIPE_AND_PORT)
1670 #define PCH_FDI_PIPE_B_LINK_M2 (0x1048 | REGS_NORTH_PIPE_AND_PORT)
1671 #define PCH_FDI_PIPE_C_LINK_M1 (0x2040 | REGS_NORTH_PIPE_AND_PORT)
1672 #define PCH_FDI_PIPE_C_LINK_M2 (0x2048 | REGS_NORTH_PIPE_AND_PORT)
1673 #define PCH_FDI_PIPE_A_LINK_N1 (0x0044 | REGS_NORTH_PIPE_AND_PORT)
1674 #define PCH_FDI_PIPE_A_LINK_N2 (0x004c | REGS_NORTH_PIPE_AND_PORT)
1675 #define PCH_FDI_PIPE_B_LINK_N1 (0x1044 | REGS_NORTH_PIPE_AND_PORT)
1676 #define PCH_FDI_PIPE_B_LINK_N2 (0x104c | REGS_NORTH_PIPE_AND_PORT)
1677 #define PCH_FDI_PIPE_C_LINK_N1 (0x2044 | REGS_NORTH_PIPE_AND_PORT)
1678 #define PCH_FDI_PIPE_C_LINK_N2 (0x204c | REGS_NORTH_PIPE_AND_PORT)
1679 #define FDI_PIPE_MN_TU_SIZE_MASK (0x3f << 25)
1680 #define FDI_PIPE_MN_VALUE_MASK (0xffffff << 0)
1681
1682 // SNB A stepping
1683 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
1684 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)
1685 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)
1686 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x00 << 22)
1687
1688 // SNB B stepping
1689 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x00 << 22)
1690 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a << 22)
1691 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39 << 22)
1692 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38 << 22)
1693 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f << 22)
1694 #define FDI_TX_ENHANCE_FRAME_ENABLE (1 << 18)
1695 #define FDI_TX_PLL_ENABLED (1 << 14)
1696
1697 #define FDI_DP_PORT_WIDTH_SHIFT 19
1698 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT)
1699 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
1700
1701 #define FDI_PLL_BIOS_0 0x46000
1702 #define FDI_PLL_FB_CLOCK_MASK 0xff
1703 #define FDI_PLL_BIOS_1 0x46004
1704 #define FDI_PLL_BIOS_2 0x46008
1705
1706 #define FDI_AUTO_TRAINING (1 << 10)
1707 #define FDI_AUTO_TRAIN_DONE (1 << 1)
1708
1709 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0 << 8)
1710 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1 << 8)
1711 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2 << 8)
1712 #define FDI_LINK_TRAIN_NORMAL_CPT (3 << 8)
1713 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3 << 8)
1714
1715 // IvyBridge changes it up because... they hate developers?
1716 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0 << 8)
1717 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1 << 8)
1718 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2 << 8)
1719 #define FDI_LINK_TRAIN_NONE_IVB (3 << 8)
1720
1721 #define PCH_FDI_RXA_CHICKEN (0x200c | REGS_SOUTH_SHARED)
1722 #define PCH_FDI_RXB_CHICKEN (0x2010 | REGS_SOUTH_SHARED)
1723 #define FDI_RX_PHASE_SYNC_POINTER_EN (1 << 0)
1724 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1 << 1)
1725
1726 #define SFUSE_STRAP (0x2014 | REGS_SOUTH_SHARED)
1727 #define SFUSE_STRAP_RAW_FREQUENCY (1 << 8)
1728
1729 // CPU Panel Fitters - These are for IronLake and up and are the CPU internal
1730 // panel fitters.
1731 #define PCH_PANEL_FITTER_BASE_REGISTER 0x68000
1732 #define PCH_PANEL_FITTER_PIPE_OFFSET 0x00800
1733
1734 #define PCH_PANEL_FITTER_WINDOW_POS 0x70
1735 #define PCH_PANEL_FITTER_WINDOW_SIZE 0x74
1736 #define PCH_PANEL_FITTER_CONTROL 0x80
1737 //not on IvyBridge:
1738 #define PCH_PANEL_FITTER_V_SCALE 0x84
1739 #define PCH_PANEL_FITTER_H_SCALE 0x90
1740
1741 #define PANEL_FITTER_ENABLED (1 << 31)
1742 //pipes are hardcoded according to offset on SkyLake and later
1743 #define PANEL_FITTER_PIPE_MASK (3 << 29)
1744 #define PANEL_FITTER_PIPE_A (0 << 29)
1745 #define PANEL_FITTER_PIPE_B (1 << 29)
1746 #define PANEL_FITTER_PIPE_C (2 << 29)
1747 #define PANEL_FITTER_SCALING_MODE_MASK (7 << 26)
1748 #define PANEL_FITTER_FILTER_MASK (3 << 24)
1749
1750 struct overlay_scale {
1751 uint32 _reserved0 : 3;
1752 uint32 horizontal_scale_fraction : 12;
1753 uint32 _reserved1 : 1;
1754 uint32 horizontal_downscale_factor : 3;
1755 uint32 _reserved2 : 1;
1756 uint32 vertical_scale_fraction : 12;
1757 };
1758
1759 #define OVERLAY_FORMAT_RGB15 0x2
1760 #define OVERLAY_FORMAT_RGB16 0x3
1761 #define OVERLAY_FORMAT_RGB32 0x1
1762 #define OVERLAY_FORMAT_YCbCr422 0x8
1763 #define OVERLAY_FORMAT_YCbCr411 0x9
1764 #define OVERLAY_FORMAT_YCbCr420 0xc
1765
1766 #define OVERLAY_MIRROR_NORMAL 0x0
1767 #define OVERLAY_MIRROR_HORIZONTAL 0x1
1768 #define OVERLAY_MIRROR_VERTICAL 0x2
1769
1770 // The real overlay registers are written to using an update buffer
1771
1772 struct overlay_registers {
1773 uint32 buffer_rgb0;
1774 uint32 buffer_rgb1;
1775 uint32 buffer_u0;
1776 uint32 buffer_v0;
1777 uint32 buffer_u1;
1778 uint32 buffer_v1;
1779 // (0x18) OSTRIDE - overlay stride
1780 uint16 stride_rgb;
1781 uint16 stride_uv;
1782 // (0x1c) YRGB_VPH - Y/RGB vertical phase
1783 uint16 vertical_phase0_rgb;
1784 uint16 vertical_phase1_rgb;
1785 // (0x20) UV_VPH - UV vertical phase
1786 uint16 vertical_phase0_uv;
1787 uint16 vertical_phase1_uv;
1788 // (0x24) HORZ_PH - horizontal phase
1789 uint16 horizontal_phase_rgb;
1790 uint16 horizontal_phase_uv;
1791 // (0x28) INIT_PHS - initial phase shift
1792 uint32 initial_vertical_phase0_shift_rgb0 : 4;
1793 uint32 initial_vertical_phase1_shift_rgb0 : 4;
1794 uint32 initial_horizontal_phase_shift_rgb0 : 4;
1795 uint32 initial_vertical_phase0_shift_uv : 4;
1796 uint32 initial_vertical_phase1_shift_uv : 4;
1797 uint32 initial_horizontal_phase_shift_uv : 4;
1798 uint32 _reserved0 : 8;
1799 // (0x2c) DWINPOS - destination window position
1800 uint16 window_left;
1801 uint16 window_top;
1802 // (0x30) DWINSZ - destination window size
1803 uint16 window_width;
1804 uint16 window_height;
1805 // (0x34) SWIDTH - source width
1806 uint16 source_width_rgb;
1807 uint16 source_width_uv;
1808 // (0x38) SWITDHSW - source width in 8 byte steps
1809 uint16 source_bytes_per_row_rgb;
1810 uint16 source_bytes_per_row_uv;
1811 uint16 source_height_rgb;
1812 uint16 source_height_uv;
1813 overlay_scale scale_rgb;
1814 overlay_scale scale_uv;
1815 // (0x48) OCLRC0 - overlay color correction 0
1816 uint32 brightness_correction : 8; // signed, -128 to 127
1817 uint32 _reserved1 : 10;
1818 uint32 contrast_correction : 9; // fixed point: 3.6 bits
1819 uint32 _reserved2 : 5;
1820 // (0x4c) OCLRC1 - overlay color correction 1
1821 uint32 saturation_cos_correction : 10; // fixed point: 3.7 bits
1822 uint32 _reserved3 : 6;
1823 uint32 saturation_sin_correction : 11; // signed fixed point: 3.7 bits
1824 uint32 _reserved4 : 5;
1825 // (0x50) DCLRKV - destination color key value
1826 uint32 color_key_blue : 8;
1827 uint32 color_key_green : 8;
1828 uint32 color_key_red : 8;
1829 uint32 _reserved5 : 8;
1830 // (0x54) DCLRKM - destination color key mask
1831 uint32 color_key_mask_blue : 8;
1832 uint32 color_key_mask_green : 8;
1833 uint32 color_key_mask_red : 8;
1834 uint32 _reserved6 : 7;
1835 uint32 color_key_enabled : 1;
1836 // (0x58) SCHRKVH - source chroma key high value
1837 uint32 source_chroma_key_high_red : 8;
1838 uint32 source_chroma_key_high_blue : 8;
1839 uint32 source_chroma_key_high_green : 8;
1840 uint32 _reserved7 : 8;
1841 // (0x5c) SCHRKVL - source chroma key low value
1842 uint32 source_chroma_key_low_red : 8;
1843 uint32 source_chroma_key_low_blue : 8;
1844 uint32 source_chroma_key_low_green : 8;
1845 uint32 _reserved8 : 8;
1846 // (0x60) SCHRKEN - source chroma key enable
1847 uint32 _reserved9 : 24;
1848 uint32 source_chroma_key_red_enabled : 1;
1849 uint32 source_chroma_key_blue_enabled : 1;
1850 uint32 source_chroma_key_green_enabled : 1;
1851 uint32 _reserved10 : 5;
1852 // (0x64) OCONFIG - overlay configuration
1853 uint32 _reserved11 : 3;
1854 uint32 color_control_output_mode : 1;
1855 uint32 yuv_to_rgb_bypass : 1;
1856 uint32 _reserved12 : 11;
1857 uint32 gamma2_enabled : 1;
1858 uint32 _reserved13 : 1;
1859 uint32 select_pipe : 1;
1860 uint32 slot_time : 8;
1861 uint32 _reserved14 : 5;
1862 // (0x68) OCOMD - overlay command
1863 uint32 overlay_enabled : 1;
1864 uint32 active_field : 1;
1865 uint32 active_buffer : 2;
1866 uint32 test_mode : 1;
1867 uint32 buffer_field_mode : 1;
1868 uint32 _reserved15 : 1;
1869 uint32 tv_flip_field_enabled : 1;
1870 uint32 _reserved16 : 1;
1871 uint32 tv_flip_field_parity : 1;
1872 uint32 source_format : 4;
1873 uint32 ycbcr422_order : 2;
1874 uint32 _reserved18 : 1;
1875 uint32 mirroring_mode : 2;
1876 uint32 _reserved19 : 13;
1877
1878 uint32 _reserved20;
1879
1880 uint32 start_0y;
1881 uint32 start_1y;
1882 uint32 start_0u;
1883 uint32 start_0v;
1884 uint32 start_1u;
1885 uint32 start_1v;
1886 uint32 _reserved21[6];
1887 #if 0
1888 // (0x70) AWINPOS - alpha blend window position
1889 uint32 awinpos;
1890 // (0x74) AWINSZ - alpha blend window size
1891 uint32 awinsz;
1892
1893 uint32 _reserved21[10];
1894 #endif
1895
1896 // (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough,
1897 // the next two registers switch the usual Y/RGB vs. UV order)
1898 uint16 horizontal_scale_uv;
1899 uint16 horizontal_scale_rgb;
1900 // (0xa4) UVSCALEV - vertical downscale
1901 uint16 vertical_scale_uv;
1902 uint16 vertical_scale_rgb;
1903
1904 uint32 _reserved22[86];
1905
1906 // (0x200) polyphase filter coefficients
1907 uint16 vertical_coefficients_rgb[128];
1908 uint16 horizontal_coefficients_rgb[128];
1909
1910 uint32 _reserved23[64];
1911
1912 // (0x500)
1913 uint16 vertical_coefficients_uv[128];
1914 uint16 horizontal_coefficients_uv[128];
1915 };
1916
1917 // i965 overlay support is currently realized using its 3D hardware
1918 #define INTEL_i965_OVERLAY_STATE_SIZE 36864
1919 #define INTEL_i965_3D_CONTEXT_SIZE 32768
1920
1921 inline bool
intel_uses_physical_overlay(intel_shared_info & info)1922 intel_uses_physical_overlay(intel_shared_info &info)
1923 {
1924 return !info.device_type.InGroup(INTEL_GROUP_Gxx);
1925 }
1926
1927
1928 struct hardware_status {
1929 uint32 interrupt_status_register;
1930 uint32 _reserved0[3];
1931 void* primary_ring_head_storage;
1932 uint32 _reserved1[3];
1933 void* secondary_ring_0_head_storage;
1934 void* secondary_ring_1_head_storage;
1935 uint32 _reserved2[2];
1936 void* binning_head_storage;
1937 uint32 _reserved3[3];
1938 uint32 store[1008];
1939 };
1940
1941
1942 #endif /* INTEL_EXTREME_H */
1943