Searched refs:HAL_NUM_TX_QUEUES (Results 1 – 19 of 19) sorted by relevance
40 if (q >= HAL_NUM_TX_QUEUES) { in ar5210SetTxQueueProps()56 if (q >= HAL_NUM_TX_QUEUES) { in ar5210GetTxQueueProps()128 if (q >= HAL_NUM_TX_QUEUES) { in ar5210ReleaseTxQueue()161 if (q >= HAL_NUM_TX_QUEUES) { in ar5210ResetTxQueue()262 HALASSERT(q < HAL_NUM_TX_QUEUES); in ar5210GetTxDP()287 HALASSERT(q < HAL_NUM_TX_QUEUES); in ar5210SetTxDP()372 HALASSERT(q < HAL_NUM_TX_QUEUES); in ar5210StartTxDma()406 HALASSERT(q < HAL_NUM_TX_QUEUES); in ar5210NumTxPending()433 HALASSERT(q < HAL_NUM_TX_QUEUES); in ar5210StopTxDma()
95 #undef HAL_NUM_TX_QUEUES /* from ah.h */96 #define HAL_NUM_TX_QUEUES 3 macro112 HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES]; /* beacon+cab+data */
371 pCap->halTotalQueues = HAL_NUM_TX_QUEUES; in ar5210FillCapabilityInfo()
267 for (q = 0; q < HAL_NUM_TX_QUEUES; q++) in ar5210Reset()
84 if (q >= HAL_NUM_TX_QUEUES) { in ar5211SetTxQueueProps()100 if (q >= HAL_NUM_TX_QUEUES) { in ar5211GetTxQueueProps()203 if (q >= HAL_NUM_TX_QUEUES) { in ar5211ReleaseTxQueue()239 if (q >= HAL_NUM_TX_QUEUES) { in ar5211ResetTxQueue()404 HALASSERT(q < HAL_NUM_TX_QUEUES); in ar5211GetTxDP()414 HALASSERT(q < HAL_NUM_TX_QUEUES); in ar5211SetTxDP()434 HALASSERT(q < HAL_NUM_TX_QUEUES); in ar5211StartTxDma()457 HALASSERT(q < HAL_NUM_TX_QUEUES); in ar5211NumTxPending()479 HALASSERT(q < HAL_NUM_TX_QUEUES); in ar5211StopTxDma()
121 HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES];
506 pCap->halTotalQueues = HAL_NUM_TX_QUEUES; in ar5211FillCapabilityInfo()
487 for (q = 0; q < HAL_NUM_TX_QUEUES; q++) in ar5211Reset()
685 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { in ath_edma_dma_txsetup()697 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { in ath_edma_dma_txteardown()726 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { in ath_edma_tx_drain()743 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { in ath_edma_tx_drain()1031 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { in ath_edma_tx_processq()
351 #define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */578 struct ath_tx_edma_fifo sc_txedma[HAL_NUM_TX_QUEUES];764 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES];
3106 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { in ath_reset()4206 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) in ath_tx_cleanup()4722 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) in ath_tx_proc()4772 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { in ath_txq_sched_tasklet()4868 if (bf->bf_state.bfs_tx_queue > HAL_NUM_TX_QUEUES) { in ath_txq_addholdingbuf()5140 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { in ath_stoptxdma()5191 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { in ath_legacy_tx_drain()
495 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { in ath_sysctl_txagg()
469 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { in ar9300__cont_tx_mode()550 for (i = 0; i < HAL_NUM_TX_QUEUES + 2; i++) { /* disconnect QCUs */ in ar9300__cont_tx_mode()
432 HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES];
2805 p_cap->halTotalQueues = HAL_NUM_TX_QUEUES; in ar9300_fill_capability_info()
271 HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES];
867 pCap->halTotalQueues = HAL_NUM_TX_QUEUES; in ar5212FillCapabilityInfo()
958 pCap->halTotalQueues = HAL_NUM_TX_QUEUES; in ar5416FillCapabilityInfo()
249 #define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */ macro