1 /* 2 * Copyright 2012-2016 Haiku, Inc. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Alexander von Gluck, kallisti5@unixzen.com 7 */ 8 #ifndef _DP_RAW_H 9 #define _DP_RAW_H 10 11 12 /* ****************************************************** */ 13 /* *** AUX Channel Communications *** */ 14 // Native AUX Communications 15 #define DP_AUX_NATIVE_WRITE 0x8 16 #define DP_AUX_NATIVE_READ 0x9 17 #define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0) 18 #define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0) 19 #define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0) 20 #define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0) 21 // AUX i2c Communications 22 #define DP_AUX_I2C_WRITE 0x0 23 #define DP_AUX_I2C_READ 0x1 24 #define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2 25 #define DP_AUX_I2C_MOT 0x4 26 #define DP_AUX_I2C_REPLY_ACK (0x0 << 2) 27 #define DP_AUX_I2C_REPLY_NACK (0x1 << 2) 28 #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2) 29 #define DP_AUX_I2C_REPLY_MASK (0x3 << 2) 30 31 32 /* ****************************************************** */ 33 /* *** DPCD (DisplayPort Configuration Data) *** */ 34 /* *** Read / Written over DisplayPort AUX link *** */ 35 36 /* *** DPCD Receiver Compatibility Field (0x0000) *** */ 37 /* *** VESA DisplayPort Standard, rev 1.1, p112 *** */ 38 // DPCD Version (0x0) 39 #define DP_DPCD_REV 0x0000 // Reg 40 #define DP_DPCD_REV_MINOR_MASK (15 << 0) // Int 41 #define DP_DPCD_REV_MAJOR_MASK (15 << 4) // Int 42 #define DP_DPCD_REV_10 0x0010 // Value 43 #define DP_DPCD_REV_11 0x0011 // Value 44 #define DP_DPCD_REV_12 0x0012 // Value 45 // DP Maximum Link Rate (0x1) 46 #define DP_MAX_LINK_RATE 0x0001 // Reg 47 // Use DP_LINK_RATE_* for speed. 48 // DP Maximum Lane Count (0x2) 49 #define DP_MAX_LANE_COUNT 0x0002 // Reg 50 #define DP_MAX_LANE_COUNT_MASK 0x1f // Count 51 #define DP_ENHANCED_FRAME_CAP (1 << 7) // Bool, Rev 1.1 52 // DP Maximum Downspread (0x3) 53 #define DP_MAX_DOWNSPREAD 0x0003 // Reg 54 #define DP_MAX_DOWNSPREAD_0_5 (1 << 0) // Bool 55 #define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) // Bool 56 // DP Number of Receiver Ports (0x4) 57 #define DP_NORP 0x0004 // Reg 58 #define DP_NORP_MASK 0x1 // Count 59 // DP Downstream Port Present (0x5) 60 #define DP_DOWNSTREAMPORT_PRESENT 0x0005 // Reg 61 #define DP_DWN_STRM_PORT_PRESENT (1 << 0) // Bool 62 #define DP_DWN_STRM_PORT_TYPE_MASK (3 << 1) // Mask 63 #define DP_DWN_STRM_PORT_TYPE_DP (0 << 1) // Value 64 #define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1) // Value 65 #define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1) // Value 66 #define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1) // Value 67 #define DP_FORMAT_CONVERSION (1 << 3) // Bool 68 #define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) // Bool 69 // DP Main Link Channel Coding (0x6) 70 #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x0006 // Reg 71 #define DP_CAP_ANSI_8B10B (1 << 0) // Bool 72 // DP Downstream Port Count (0x7) (Only 1.1+) 73 #define DP_DOWN_STREAM_PORT_COUNT 0x0007 // Reg 74 #define DP_PORT_COUNT_MASK 0xf // Count 75 #define DP_OUI_SUPPORT (1 << 7) // Bool 76 // DP Port Capability 0 77 #define DP_RECEIVE_PORT_0_CAP_0 0x0008 // Reg 78 #define DP_RECEIVE_PORT_1_CAP_0 0x000a // Reg 79 #define DP_LOCAL_EDID_PRESENT (1 << 1) // Bool 80 #define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2) // Bool 81 // DP Port Buffer Size 82 #define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x0009 // Reg 83 #define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x000b // Reg 84 // (value + 1) * 32 bytes per lane 85 86 /* *** DPCD Link Configuration Field (0x0100) *** */ 87 /* *** VESA DisplayPort Standard, rev 1.1, p117 *** */ 88 89 // DP Set Link Rate Per Lane (0x0100) 90 #define DP_LINK_RATE 0x0100 // Reg 91 #define DP_LINK_RATE_162 0x0006 // 1.62Ghz 92 #define DP_LINK_RATE_270 0x000A // 2.70Ghz 93 #define DP_LINK_RATE_540 0x0014 // 5.40Ghz 94 // DP Set Lane Count (0x0101) 95 #define DP_LANE_COUNT 0x0101 // Reg 96 #define DP_LANE_COUNT_MASK (31 << 0) // Count 97 #define DP_ENHANCED_FRAME_EN (1 << 7) // Bool, Rev 1.1 98 // DP Training Pattern (0x0102) 99 #define DP_TRAINING_PATTERN_SET 0x0102 // Reg 100 #define DP_TRAINING_PATTERN_MASK (3 << 0) // Mask 101 #define DP_TRAINING_PATTERN_DISABLE (0 << 0) // Value 102 #define DP_TRAINING_PATTERN_1 (1 << 0) // Value 103 #define DP_TRAINING_PATTERN_2 (2 << 0) // Value 104 #define DP_TRAINING_PATTERN_3 (3 << 0) // Value 105 106 #define DP_TRAIN_QUAL_MASK (3 << 2) // Mask 107 #define DP_TRAIN_QUAL_NONE (0 << 2) // Value 108 #define DP_TRAIN_QUAL_D102 (1 << 2) // Value 109 #define DP_TRAIN_QUAL_SYMB_ERR (2 << 2) // Value 110 #define DP_TRAIN_QUAL_PRBS7 (3 << 2) // Value 111 112 #define DP_TRAIN_CLOCK_RECOVER_EN (1 << 4) // Bool 113 #define DP_TRAIN_SCRAMBLE_DI (1 << 5) // Bool (rev) 114 #define DP_TRAIN_SYMBL_ERR_SEL_MASK (3 << 6) // Mask 115 #define DP_TRAIN_SYMBL_ERR_SEL_BOTH (0 << 6) // Value 116 #define DP_TRAIN_SYMBL_ERR_SEL_DISPARITY (1 << 6) // Value 117 #define DP_TRAIN_SYMBL_ERR_SEL_SYMBOL (2 << 6) // Value 118 // DP Training Lane n (0x0103 - 0x0106) 119 #define DP_TRAINING_LANE0_SET 0x0103 // Reg 120 #define DP_TRAINING_LANE1_SET 0x0104 // Reg 121 #define DP_TRAINING_LANE2_SET 0x0105 // Reg 122 #define DP_TRAINING_LANE3_SET 0x0106 // Reg 123 124 #define DP_TRAIN_VCC_SWING_SHIFT (0 << 0) // Shift 125 #define DP_TRAIN_VCC_SWING_MASK (3 << 0) // Mask 126 #define DP_TRAIN_VCC_SWING_400 (0 << 0) // Value 127 #define DP_TRAIN_VCC_SWING_600 (1 << 0) // Value 128 #define DP_TRAIN_VCC_SWING_800 (2 << 0) // Value 129 #define DP_TRAIN_VCC_SWING_1200 (3 << 0) // Value 130 #define DP_TRAIN_MAX_SWING_EN (1 << 2) // Bool 131 132 #define DP_TRAIN_PRE_EMPHASIS_SHIFT (3 << 0) // Shift 133 #define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) // Mask 134 #define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3) // Value 135 #define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3) // Value 136 #define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3) // Value 137 #define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3) // Value 138 #define DP_TRAIN_MAX_EMPHASIS_EN (1 << 5) // Bool 139 // DP Down-spread Control (0x0107) 140 #define DP_DOWNSPREAD_CTRL 0x0107 // Reg 141 #define DP_DOWNSPREAD_CTRL_FREQ_MASK (1 << 0) // Int 142 #define DP_DOWNSPREAD_CTRL_AMP_EN (1 << 4) // Int 143 // DP Main Link Channel Coding (0x0108) 144 #define DP_MAIN_CHAN_CODE 0x0108 // Reg 145 #define DP_MAIN_CHAN_CODE_ANSIX3_EN (1 << 0) // Bool 146 147 /* *** DPCD Link / Sink Status Field (0x0200) *** */ 148 /* *** VESA DisplayPort Standard, rev 1.1, p120 *** */ 149 150 // DP Sink Count (0x0200) 151 #define DP_SINK_COUNT 0x0200 // Reg 152 #define DP_SINK_COUNT_MASK (63 << 0) // Mask 153 #define DP_SINK_COUNT_CP_READY (1 << 6) // Bool 154 // DP Service IRQ Vector (0x0201) 155 #define DP_SINK_IRQ_VECTOR 0x0201 // Reg 156 #define DP_SINK_IRQ_TEST_REQ (1 << 1) // Bool 157 #define DP_SINK_IRQ_CP_IRQ (1 << 2) // Bool 158 #define DP_SINK_IRQ_VENDOR (1 << 6) // Bool 159 // DP Lane Status A B 160 #define DP_LANE_STATUS_0_1 0x0202 // Reg 161 #define DP_LANE_STATUS_2_3 0x0203 // Reg 162 #define DP_LINK_STATUS_SIZE 6 // Size 163 #define DP_LANE_STATUS_CR_DONE_A (1 << 0) // Bool 164 #define DP_LANE_STATUS_CHEQ_DONE_A (1 << 1) // Bool 165 #define DP_LANE_STATUS_SYMB_LOCK_A (1 << 2) // Bool 166 #define DP_LANE_STATUS_CR_DONE_B (1 << 4) // Bool 167 #define DP_LANE_STATUS_CHEQ_DONE_B (1 << 5) // Bool 168 #define DP_LANE_STATUS_SYMB_LOCK_B (1 << 6) // Bool 169 #define DP_LANE_STATUS_EQUALIZED_A (DP_LANE_STATUS_CR_DONE_A \ 170 | DP_LANE_STATUS_CHEQ_DONE_A \ 171 | DP_LANE_STATUS_SYMB_LOCK_A) 172 #define DP_LANE_STATUS_EQUALIZED_B (DP_LANE_STATUS_CR_DONE_B \ 173 | DP_LANE_STATUS_CHEQ_DONE_B \ 174 | DP_LANE_STATUS_SYMB_LOCK_B) 175 // DP Lane Align Status (0x0204) 176 #define DP_LANE_ALIGN_STATUS_UPDATED 0x0204 // Reg 177 #define DP_INTERLANE_ALIGN_DONE (1 << 0) // Bool 178 #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) // Bool 179 #define DP_LINK_STATUS_UPDATED (1 << 7) // Bool 180 // DP Sink Status (0x0205) 181 #define DP_SINK_STATUS 0x0205 // Reg 182 #define DP_SINK_STATUS_IN_SYNC_0 (1 << 0) // Bool 183 #define DP_SINK_STATUS_IN_SYNC_1 (1 << 1) // Bool 184 // DP Adjust Request A B 185 #define DP_ADJ_REQUEST_0_1 0x0206 // Reg 186 #define DP_ADJ_REQUEST_2_3 0x0207 // Reg 187 #define DP_ADJ_VCC_SWING_LANEA_SHIFT 0 // Shift 188 #define DP_ADJ_VCC_SWING_LANEA_MASK (3 << 0) // Mask 189 #define DP_ADJ_PRE_EMPHASIS_LANEA_SHIFT 2 // Shift 190 #define DP_ADJ_PRE_EMPHASIS_LANEA_MASK (3 << 2) // Mask 191 #define DP_ADJ_VCC_SWING_LANEB_SHIFT 4 // Shift 192 #define DP_ADJ_VCC_SRING_LANEB_MASK (3 << 4) // Mask 193 #define DP_ADJ_PRE_EMPHASIS_LANEB_SHIFT 6 // Shift 194 #define DP_ADJ_PRE_EMPHASIS_LANEB_MASK (3 << 6) // Mask 195 196 // TODO: 0x0210 - 0x0217 197 198 /* *** DPCD Automated Self-testing Field (0x0218) *** */ 199 /* *** VESA DisplayPort Standard, rev 1.1, p123 *** */ 200 201 // TODO: Optional Field 202 203 /* *** DPCD Source Device Specific Field (0x0300) *** */ 204 /* *** VESA DisplayPort Standard, rev 1.1, p127 *** */ 205 206 // TODO 207 208 /* *** DPCD Sink Device Specific Field (0x0400) *** */ 209 /* *** VESA DisplayPort Standard, rev 1.1, p127 *** */ 210 211 // TODO 212 213 /* *** DPCD Branch Device Specific Field (0x0500) *** */ 214 /* *** VESA DisplayPort Standard, rev 1.1, p127 *** */ 215 216 // TODO 217 218 /* *** DPCD Sink Control Field (0x0600) *** */ 219 /* *** VESA DisplayPort Standard, rev 1.1, p128 *** */ 220 221 #define DP_SET_POWER 0x0600 // Reg 222 #define DP_SET_POWER_D0 (1 << 0) // Value 223 #define DP_SET_POWER_D3 (1 << 1) // Value 224 225 /* *** DPCD Reserved (0x0700+) *** */ 226 /* ****************************************************** */ 227 228 229 #endif /* _DP_RAW_H */ 230