xref: /haiku/src/add-ons/media/media-add-ons/radeon/Radeon.h (revision 97f865f72a5e3084e47caa02d8749b10f0c201b9)
1 /******************************************************************************
2 /
3 /	File:			Radeon.h
4 /
5 /	Description:	ATI Radeon Graphics Chip interface.
6 /
7 /	Copyright 2001, Carlos Hasan
8 /
9 *******************************************************************************/
10 
11 #ifndef __RADEON_H__
12 #define __RADEON_H__
13 
14 #include "radeon_interface.h"
15 
16 #define BITS(a) int((0xffffffffU>>(31-(1?a)))&(0xffffffffU<<(0?a)))
17 
18 enum radeon_video_tuner {
19 	C_RADEON_NO_TUNER							= 0,
20 	C_RADEON_FI1236_MK1_NTSC					= 1,
21 	C_RADEON_FI1236_MK2_NTSC_JAPAN				= 2,
22 	C_RADEON_FI1216_MK2_PAL_BG					= 3,
23 	C_RADEON_FI1246_MK2_PAL_I					= 4,
24 	C_RADEON_FI1216_MF_MK2_PAL_BG_SECAM_L		= 5,
25 	C_RADEON_FI1236_MK2_NTSC					= 6,
26 	C_RADEON_FI1256_MK2_SECAM_DK				= 7,
27 	C_RADEON_FI1216_MK2_PAL_BG_SECAM_L			= 8,
28 	C_RADEON_TEMIC_FN5AL_PAL_IBGDK_SECAM_DK		= 9
29 };
30 
31 enum radeon_video_clock {
32 	C_RADEON_NO_VIDEO_CLOCK						= 0,
33 	C_RADEON_VIDEO_CLOCK_28_63636_MHZ			= 1,
34 	C_RADEON_VIDEO_CLOCK_29_49892_MHZ			= 2,
35 	C_RADEON_VIDEO_CLOCK_27_00000_MHZ			= 3,
36 	C_RADEON_VIDEO_CLOCK_14_31818_MHZ			= 4
37 };
38 
39 enum radeon_video_decoder {
40 	C_RADEON_NO_VIDEO							= 0,
41 	C_RADEON_BT819								= 1,
42 	C_RADEON_BT829								= 2,
43 	C_RADEON_BT829A								= 3,
44 	C_RADEON_SA7111								= 4,
45 	C_RADEON_SA7112								= 5,
46 	C_RADEON_RAGE_THEATER						= 6
47 };
48 
49 enum radeon_register {
50 	C_RADEON_VIDEOMUX_CNTL						= 0x0190,
51 		C_RADEON_VIPH_INT_SEL					= BITS(0:0),
52 		C_RADEON_ROM_CLK_DIVIDE					= BITS(20:16),
53 		C_RADEON_STR_ROMCLK						= BITS(21:21),
54 		C_RADEON_VIP_INTERNAL_DEBUG_SEL			= BITS(24:22),
55 
56 	// I2C
57     C_RADEON_I2C_CNTL_0                        	= 0x0090,
58     C_RADEON_I2C_CNTL_0_PLUS1					= 0x0091,
59         C_RADEON_I2C_DONE                      	= BITS(0:0),
60         C_RADEON_I2C_NACK                      	= BITS(1:1),
61         C_RADEON_I2C_HALT                      	= BITS(2:2),
62         C_RADEON_I2C_SOFT_RST                  	= BITS(5:5),
63         C_RADEON_I2C_DRIVE_EN                  	= BITS(6:6),
64         C_RADEON_I2C_DRIVE_SEL                 	= BITS(7:7),
65             C_RADEON_I2C_DRIVE_SEL_10_MCLKS    	= 0 << 7,
66             C_RADEON_I2C_DRIVE_SEL_20_MCLKS    	= 1 << 7,
67         C_RADEON_I2C_START                     	= BITS(8:8),
68         C_RADEON_I2C_STOP                      	= BITS(9:9),
69         C_RADEON_I2C_RECEIVE                   	= BITS(10:10),
70         C_RADEON_I2C_ABORT                     	= BITS(11:11),
71         C_RADEON_I2C_GO                        	= BITS(12:12),
72 		C_RADEON_I2C_PRESCALE					= BITS(31:16),
73 
74     C_RADEON_I2C_CNTL_1                        	= 0x0094,
75         C_RADEON_I2C_DATA_COUNT                	= BITS(3:0),
76         C_RADEON_I2C_ADDR_COUNT                	= BITS(10:8),
77         C_RADEON_I2C_SEL                       	= BITS(16:16),
78         C_RADEON_I2C_EN                        	= BITS(17:17),
79 		C_RADEON_I2C_TIME_LIMIT					= BITS(31:24),
80 
81     C_RADEON_I2C_DATA                          	= 0x0098,
82         C_RADEON_I2C_DATA_MASK                 	= BITS(7:0),
83 
84 	// Capture
85 	C_RADEON_CAP_INT_CNTL						= 0x0908,
86 		C_RADEON_CAP0_BUF0_INT_EN				= BITS(0:0),
87 		C_RADEON_CAP0_BUF0_EVEN_INT_EN			= BITS(1:1),
88 		C_RADEON_CAP0_BUF1_INT_EN				= BITS(2:2),
89 		C_RADEON_CAP0_BUF1_EVEN_INT_EN			= BITS(3:3),
90 		C_RADEON_CAP0_VBI0_INT_EN				= BITS(4:4),
91 		C_RADEON_CAP0_VBI1_INT_EN				= BITS(5:5),
92 		C_RADEON_CAP0_ONESHOT_INT_EN			= BITS(6:6),
93 		C_RADEON_CAP0_ANC0_INT_EN				= BITS(7:7),
94 		C_RADEON_CAP0_ANC1_INT_EN				= BITS(8:8),
95 		C_RADEON_CAP0_VBI2_INT_EN				= BITS(9:9),
96 		C_RADEON_CAP0_VBI3_INT_EN				= BITS(10:10),
97 		C_RADEON_CAP0_ANC2_INT_EN				= BITS(11:11),
98 		C_RADEON_CAP0_ANC3_INT_EN				= BITS(12:12),
99 
100 	C_RADEON_CAP_INT_STATUS						= 0x090C,
101 		C_RADEON_CAP0_BUF0_INT					= BITS(0:0),
102 		C_RADEON_CAP0_BUF0_INT_AK				= BITS(0:0),
103 		C_RADEON_CAP0_BUF0_EVEN_INT				= BITS(1:1),
104 		C_RADEON_CAP0_BUF0_EVEN_INT_AK			= BITS(1:1),
105 		C_RADEON_CAP0_BUF1_INT					= BITS(2:2),
106 		C_RADEON_CAP0_BUF1_INT_AK				= BITS(2:2),
107 		C_RADEON_CAP0_BUF1_EVEN_INT				= BITS(3:3),
108 		C_RADEON_CAP0_BUF1_EVEN_INT_AK			= BITS(3:3),
109 		C_RADEON_CAP0_VBI0_INT					= BITS(4:4),
110 		C_RADEON_CAP0_VBI0_INT_AK				= BITS(4:4),
111 		C_RADEON_CAP0_VBI1_INT					= BITS(5:5),
112 		C_RADEON_CAP0_VBI1_INT_AK				= BITS(5:5),
113 		C_RADEON_CAP0_ONESHOT_INT				= BITS(6:6),
114 		C_RADEON_CAP0_ONESHOT_INT_AK			= BITS(6:6),
115 		C_RADEON_CAP0_ANC0_INT					= BITS(7:7),
116 		C_RADEON_CAP0_ANC0_INT_AK				= BITS(7:7),
117 		C_RADEON_CAP0_ANC1_INT					= BITS(8:8),
118 		C_RADEON_CAP0_ANC1_INT_AK				= BITS(8:8),
119 		C_RADEON_CAP0_VBI2_INT					= BITS(9:9),
120 		C_RADEON_CAP0_VBI2_INT_AK				= BITS(9:9),
121 		C_RADEON_CAP0_VBI3_INT					= BITS(10:10),
122 		C_RADEON_CAP0_VBI3_INT_AK				= BITS(10:10),
123 		C_RADEON_CAP0_ANC2_INT					= BITS(11:11),
124 		C_RADEON_CAP0_ANC2_INT_AK				= BITS(11:11),
125 		C_RADEON_CAP0_ANC3_INT					= BITS(12:12),
126 		C_RADEON_CAP0_ANC3_INT_AK				= BITS(12:12),
127 
128 	C_RADEON_FCP_CNTL							= 0x0910,
129 		C_RADEON_FCP0_SRC_SEL					= BITS(2:0),
130 			C_RADEON_FCP0_SRC_PCICLK			= 0 << 0,
131 			C_RADEON_FCP0_SRC_PCLK				= 1 << 0,
132 			C_RADEON_FCP0_SRC_PCLKb				= 2 << 0,
133 			C_RADEON_FCP0_SRC_HREF				= 3 << 0,
134 			C_RADEON_FCP0_SRC_GND				= 4 << 0,
135 			C_RADEON_FCP0_SRC_HREFb				= 5 << 0,
136 
137 	C_RADEON_CAP0_BUF0_OFFSET                   = 0x0920,
138 	C_RADEON_CAP0_BUF1_OFFSET                   = 0x0924,
139 	C_RADEON_CAP0_BUF0_EVEN_OFFSET              = 0x0928,
140 	C_RADEON_CAP0_BUF1_EVEN_OFFSET              = 0x092C,
141 
142 	C_RADEON_CAP0_BUF_PITCH                     = 0x0930,
143 		C_RADEON_CAP0_BUF_PITCH_MASK			= BITS(11:0),
144 
145 	C_RADEON_CAP0_V_WINDOW                      = 0x0934,
146 		C_RADEON_CAP0_V_START					= BITS(11:0),
147 		C_RADEON_CAP0_V_END						= BITS(27:16),
148 
149 	C_RADEON_CAP0_H_WINDOW                      = 0x0938,
150 		C_RADEON_CAP0_H_START					= BITS(11:0),
151 		C_RADEON_CAP0_H_WIDTH					= BITS(27:16),
152 
153 	C_RADEON_CAP0_VBI0_OFFSET                   = 0x093C,
154 	C_RADEON_CAP0_VBI1_OFFSET                   = 0x0940,
155 
156 	C_RADEON_CAP0_VBI_V_WINDOW                  = 0x0944,
157 		C_RADEON_CAP0_VBI_V_START				= BITS(11:0),
158 		C_RADEON_CAP0_VBI_V_END					= BITS(27:16),
159 
160 	C_RADEON_CAP0_VBI_H_WINDOW                  = 0x0948,
161 		C_RADEON_CAP0_VBI_H_START				= BITS(11:0),
162 		C_RADEON_CAP0_VBI_H_WIDTH				= BITS(27:16),
163 
164 	C_RADEON_CAP0_PORT_MODE_CNTL                = 0x094C,
165 		C_RADEON_CAP0_PORT_WIDTH				= BITS(1:1),
166 			C_RADEON_CAP0_PORT_WIDTH_8_BITS		= 0 << 1,
167 			C_RADEON_CAP0_PORT_WIDTH_16_BITS	= 1 << 1,
168 		C_RADEON_CAP0_PORT_BYTE_USED			= BITS(2:2),
169 			C_RADEON_CAP0_PORT_LOWER_BYTE_USED	= 0 << 2,
170 			C_RADEON_CAP0_PORT_UPPER_BYTE_USED	= 1 << 2,
171 
172 	C_RADEON_CAP0_TRIG_CNTL                     = 0x0950,
173 		C_RADEON_CAP0_TRIGGER_R					= BITS(1:0),
174 			C_RADEON_CAP0_TRIGGER_R_COMPLETE	= 0 << 0,
175 			C_RADEON_CAP0_TRIGGER_R_PENDING		= 1 << 0,
176 			C_RADEON_CAP0_TRIGGER_R_IN_PROGRESS	= 2 << 0,
177 		C_RADEON_CAP0_TRIGGER_W					= BITS(0:0),
178 			C_RADEON_CAP0_TRIGGER_W_NO_ACTION	= 0 << 0,
179 			C_RADEON_CAP0_TRIGGER_W_CAPTURE		= 1 << 0,
180 		C_RADEON_CAP0_EN						= BITS(4:4),
181 		C_RADEON_CAP0_VSYNC_CNT_R				= BITS(15:8),
182 		C_RADEON_CAP0_VSYNC_CLR					= BITS(16:16),
183 
184 	C_RADEON_CAP0_DEBUG                         = 0x0954,
185 		C_RADEON_CAP0_H_STATUS					= BITS(11:0),
186 		C_RADEON_CAP0_V_STATUS					= BITS(27:16),
187 		C_RADEON_CAP0_V_SYNC					= BITS(28:28),
188 
189 	C_RADEON_CAP0_CONFIG                        = 0x0958,
190 		C_RADEON_CAP0_INPUT_MODE				= BITS(0:0),
191 			C_RADEON_CAP0_INPUT_MODE_ONESHOT	= 0 << 0,
192 			C_RADEON_CAP0_INPUT_MODE_CONTINUOUS	= 1 << 0,
193 		C_RADEON_CAP0_START_FIELD				= BITS(1:1),
194 			C_RADEON_CAP0_START_ODD_FIELD		= 0 << 1,
195 			C_RADEON_CAP0_START_EVEN_FIELD		= 1 << 1,
196 		C_RADEON_CAP0_START_BUF_R				= BITS(2:2),
197 		C_RADEON_CAP0_START_BUF_W				= BITS(3:3),
198 		C_RADEON_CAP0_BUF_TYPE					= BITS(5:4),
199 			C_RADEON_CAP0_BUF_TYPE_FIELD		= 0 << 4,
200 			C_RADEON_CAP0_BUF_TYPE_ALTERNATING	= 1 << 4,
201 			C_RADEON_CAP0_BUF_TYPE_FRAME		= 2 << 4,
202 		C_RADEON_CAP0_ONESHOT_MODE				= BITS(6:6),
203 			C_RADEON_CAP0_ONESHOT_MODE_FIELD	= 0 << 6,
204 			C_RADEON_CAP0_ONESHOT_MODE_FRAME	= 1 << 6,
205 		C_RADEON_CAP0_BUF_MODE					= BITS(8:7),
206 			C_RADEON_CAP0_BUF_MODE_SINGLE		= 0 << 7,
207 			C_RADEON_CAP0_BUF_MODE_DOUBLE		= 1 << 7,
208 			C_RADEON_CAP0_BUF_MODE_TRIPLE		= 2 << 7,
209 		C_RADEON_CAP0_MIRROR_EN					= BITS(9:9),
210 		C_RADEON_CAP0_ONESHOT_MIRROR_EN			= BITS(10:10),
211 		C_RADEON_CAP0_VIDEO_SIGNED_UV			= BITS(11:11),
212 		C_RADEON_CAP0_ANC_DECODE_EN				= BITS(12:12),
213 		C_RADEON_CAP0_VBI_EN					= BITS(13:13),
214 		C_RADEON_CAP0_SOFT_PULL_DOWN_EN			= BITS(14:14),
215 		C_RADEON_CAP0_VIP_EXTEND_FLAG_EN		= BITS(15:15),
216 		C_RADEON_CAP0_FAKE_FIELD_EN				= BITS(16:16),
217 		C_RADEON_CAP0_FIELD_START_LINE_DIFF		= BITS(18:17),
218 		C_RADEON_CAP0_HORZ_DOWN					= BITS(20:19),
219 			C_RADEON_CAP0_HORZ_DOWN_1X			= 0 << 19,
220 			C_RADEON_CAP0_HORZ_DOWN_2X			= 1 << 19,
221 			C_RADEON_CAP0_HORZ_DOWN_3X			= 2 << 19,
222 		C_RADEON_CAP0_VERT_DOWN					= BITS(22:21),
223 			C_RADEON_CAP0_VERT_DOWN_1X			= 0 << 21,
224 			C_RADEON_CAP0_VERT_DOWN_2X			= 1 << 21,
225 			C_RADEON_CAP0_VERT_DOWN_3X			= 2 << 21,
226 		C_RADEON_CAP0_STREAM_FORMAT				= BITS(25:23),
227 			C_RADEON_CAP0_STREAM_BROOKTREE		= 0 << 23,
228 			C_RADEON_CAP0_STREAM_CCIR656		= 1 << 23,
229 			C_RADEON_CAP0_STREAM_ZV				= 2 << 23,
230 			C_RADEON_CAP0_STREAM_VIP			= 3 << 23,
231 			C_RADEON_CAP0_STREAM_TRANSPORT		= 4 << 23,
232 		C_RADEON_CAP0_HDWNS_DEC					= BITS(26:26),
233 			C_RADEON_CAP0_DOWNSCALER			= 0 << 26,
234 			C_RADEON_CAP0_DECIMATOR				= 1 << 26,
235 		C_RADEON_CAP0_VIDEO_IN_FORMAT			= BITS(29:29),
236 			C_RADEON_CAP0_VIDEO_IN_YVYU422		= 0 << 29,
237 			C_RADEON_CAP0_VIDEO_IN_VYUY422		= 1 << 29,
238 		C_RADEON_CAP0_VBI_HORZ_DOWN				= BITS(31:30),
239 			C_RADEON_CAP0_VBI_HORZ_DOWN_1X		= 0 << 30,
240 			C_RADEON_CAP0_VBI_HORZ_DOWN_2X		= 1 << 30,
241 			C_RADEON_CAP0_VBI_HORZ_DOWN_4X		= 2U << 30,
242 
243 	C_RADEON_CAP0_ANC0_OFFSET                   = 0x095C,
244 	C_RADEON_CAP0_ANC1_OFFSET                   = 0x0960,
245 
246 	C_RADEON_CAP0_ANC_H_WINDOW                  = 0x0964,
247 		C_RADEON_CAP0_ANC_WIDTH					= BITS(11:0),
248 
249 	C_RADEON_CAP0_VIDEO_SYNC_TEST               = 0x0968,
250 		C_RADEON_CAP0_TEST_VID_SOF				= BITS(0:0),
251 		C_RADEON_CAP0_TEST_VID_EOF				= BITS(1:1),
252 		C_RADEON_CAP0_TEST_VID_EOL				= BITS(2:2),
253 		C_RADEON_CAP0_TEST_VID_FIELD			= BITS(3:3),
254 		C_RADEON_CAP0_TEST_SYNC_EN				= BITS(5:5),
255 
256 	C_RADEON_CAP0_ONESHOT_BUF_OFFSET            = 0x096C,
257 
258 	C_RADEON_CAP0_BUF_STATUS                    = 0x0970,
259 		C_RADEON_CAP0_PRE_VID_BUF				= BITS(1:0),
260 		C_RADEON_CAP0_CUR_VID_BUF				= BITS(3:2),
261 		C_RADEON_CAP0_PRE_FIELD					= BITS(4:4),
262 		C_RADEON_CAP0_CUR_FIELD					= BITS(5:5),
263 		C_RADEON_CAP0_PRE_VBI_BUF				= BITS(7:6),
264 		C_RADEON_CAP0_CUR_VBI_BUF				= BITS(9:8),
265 		C_RADEON_CAP0_VBI_BUF_STATUS			= BITS(10:10),
266 		C_RADEON_CAP0_PRE_ANC_BUF				= BITS(12:11),
267 		C_RADEON_CAP0_CUR_ANC_BUF				= BITS(14:13),
268 		C_RADEON_CAP0_ANC_BUF_STATUS			= BITS(16:16),
269 		C_RADEON_CAP0_ANC_PRE_BUF_CNT			= BITS(27:16),
270 		C_RADEON_CAP0_VIP_INC					= BITS(28:28),
271 		C_RADEON_CAP0_VIP_PRE_REPEAT_FIELD		= BITS(29:29),
272 		C_RADEON_CAP0_CAP_BUF_STATUS			= BITS(30:30),
273 
274 	C_RADEON_CAP0_VBI2_OFFSET                   = 0x0980,
275 	C_RADEON_CAP0_VBI3_OFFSET                   = 0x0984,
276 	C_RADEON_CAP0_ANC2_OFFSET                   = 0x0988,
277 	C_RADEON_CAP0_ANC3_OFFSET                   = 0x098C,
278 
279 	C_RADEON_VBI_BUFFER_CONTROL					= 0x0900,
280 		C_RADEON_CAP0_BUFFER_WATER_MARK			= BITS(4:0),
281 		C_RADEON_FULL_BUFFER_EN					= BITS(16:16),
282 		C_RADEON_CAP0_ANC_VBI_QUAD_BUF			= BITS(17:17),
283 		C_RADEON_VID_BUFFER_RESET				= BITS(20:20),
284 		C_RADEON_CAP_SWAP						= BITS(22:21),
285 		C_RADEON_CAP0_BUFFER_EMPTY_R			= BITS(24:24),
286 
287 	// Test and Debug control
288     C_RADEON_TEST_DEBUG_CNTL                    = 0x0120,
289         C_RADEON_TEST_DEBUG_OUT_EN              = 0x00000001
290 };
291 
292 
293 class CRadeonRect {
294 public:
295 	CRadeonRect();
296 
297 	CRadeonRect(int left, int top, int right, int bottom);
298 
299 	int Left() const;
300 
301 	int Top() const;
302 
303 	int Right() const;
304 
305 	int Bottom() const;
306 
307 	int Width() const;
308 
309 	int Height() const;
310 
311 	void SetLeft(int value);
312 
313 	void SetTop(int value);
314 
315 	void SetRight(int value);
316 
317 	void SetBottom(int value);
318 
319 	void SetTo(int left, int top, int right, int bottom);
320 
321 	void MoveTo(int left, int top);
322 
323 	void ResizeTo(int width, int height);
324 
325 private:
326 	int fLeft;
327 	int fTop;
328 	int fRight;
329 	int fBottom;
330 };
331 
332 class CRadeon {
333 public:
334 	CRadeon( const char *dev_name );
335 
336 	~CRadeon();
337 
338 	status_t InitCheck() const;
339 
340 	uint32 VirtualMemoryBase() const;
341 
342 public:
343 	int Register(radeon_register index) const;
344 
345 	void SetRegister(radeon_register index, int value);
346 
347 	int Register(radeon_register index, int mask) const;
348 
349 	void SetRegister(radeon_register index, int mask, int value);
350 
351 	int VIPRegister(int device, int address);
352 
353 	void SetVIPRegister(int device, int address, int value);
354 
355 	int VIPReadFifo(int device, uint32 address, uint32 count, uint8 *buffer);
356 
357 	int VIPWriteFifo(int device, uint32 address, uint32 count, uint8 *buffer);
358 
359 	int FindVIPDevice( uint32 device_id );
360 
361 public:
362 	void GetPLLParameters(int & refFreq, int & refDiv, int & minFreq, int & maxFreq, int & xclock);
363 
364 	void GetMMParameters(radeon_video_tuner & tuner,
365 						 radeon_video_decoder & video,
366 						 radeon_video_clock & clock,
367 						 int & tunerPort,
368 						 int & compositePort,
369 						 int & svideoPort);
370 
371 public:
372 	status_t AllocateGraphicsMemory(
373 		memory_type_e memory_type, int32 size,
374 		int32 *offset, int32 *handle );
375 
376 	void FreeGraphicsMemory(
377 		memory_type_e memory_type, int32 handle );
378 
379 	status_t DMACopy(
380 		uint32 src, void *target, size_t size, bool lock_mem, bool contiguous );
381 
382 public:
383 	status_t GetDeviceInformation(radeon_get_private_data & info);
384 
385 	status_t WaitInterrupt(int * mask, int * sequence, bigtime_t * time, bigtime_t timeout);
386 
387 	status_t CloneArea(const char * name, area_id src_area,
388 		area_id *cloned_area, void ** map);
389 
390 	shared_info* GetSharedInfo();
391 private:
392 	int fHandle;
393 	unsigned int * fRegister;
394 	unsigned char * fROM;
395 	virtual_card *fVirtualCard;
396 	shared_info *fSharedInfo;
397 
398 	area_id fRegisterArea;
399 	area_id fROMArea;
400 	area_id fVirtualCardArea;
401 	area_id fSharedInfoArea;
402 
403 	uint32 caps_video_in;
404 };
405 
406 template <typename T>
Clamp(T value,T min,T max)407 inline T Clamp(T value, T min, T max)
408 {
409 	return (value < min ? min : value > max ? max : value);
410 }
411 
412 #endif
413