1 /* 2 * Copyright 2009 Advanced Micro Devices, Inc. 3 * Copyright 2009 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 * Jerome Glisse 26 * Alexander von Gluck <kallisti5@unixzen.com> 27 */ 28 #ifndef __AVIVO_REG_H__ 29 #define __AVIVO_REG_H__ 30 31 32 #define AVIVO_D1CRTC_UPDATE_LOCK 0x60E8 33 #define AVIVO_D1GRPH_SWAP_CNTL 0x610C 34 #define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 35 #define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 36 37 #define AVIVO_D1VGA_CONTROL 0x0330 38 #define AVIVO_DVGA_CONTROL_MODE_ENABLE (1 << 0) 39 #define AVIVO_DVGA_CONTROL_TIMING_SELECT (1 << 8) 40 #define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT (1 << 9) 41 #define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1 << 10) 42 #define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN (1 << 16) 43 #define AVIVO_DVGA_CONTROL_ROTATE (1 << 24) 44 #define AVIVO_D2VGA_CONTROL 0x0338 45 46 #define AVIVO_VGA_HDP_CONTROL 0x328 47 #define AVIVO_VGA_MEM_PAGE_SELECT_EN (1 << 0) 48 #define AVIVO_VGA_MEMORY_DISABLE (1 << 4) 49 #define AVIVO_VGA_RBBM_LOCK_DISABLE (1 << 8) 50 #define AVIVO_VGA_SOFT_RESET (1 << 16) 51 #define AVIVO_VGA_MEMORY_BASE_ADDRESS 0x0310 52 #define AVIVO_VGA_RENDER_CONTROL 0x0300 53 #define AVIVO_VGA_VSTATUS_CNTL_MASK (3 << 16) 54 55 56 #define AVIVO_MC_INDEX 0x0070 57 #define AVIVO_MC_DATA 0x0074 58 59 #define AVIVO_CP_DYN_CNTL 0x000f /* PLL */ 60 #define AVIVO_CP_FORCEON (1 << 0) 61 #define AVIVO_E2_DYN_CNTL 0x0011 /* PLL */ 62 #define AVIVO_E2_FORCEON (1 << 0) 63 #define AVIVO_IDCT_DYN_CNTL 0x0013 /* PLL */ 64 #define AVIVO_IDCT_FORCEON (1 << 0) 65 66 #define AVIVO_HDP_FB_LOCATION 0x134 67 68 #define AVIVO_EXT1_PPLL_REF_DIV_SRC 0x400 69 #define AVIVO_EXT1_PPLL_REF_DIV 0x404 70 #define AVIVO_EXT1_PPLL_UPDATE_LOCK 0x408 71 #define AVIVO_EXT1_PPLL_UPDATE_CNTL 0x40c 72 73 #define AVIVO_EXT2_PPLL_REF_DIV_SRC 0x410 74 #define AVIVO_EXT2_PPLL_REF_DIV 0x414 75 #define AVIVO_EXT2_PPLL_UPDATE_LOCK 0x418 76 #define AVIVO_EXT2_PPLL_UPDATE_CNTL 0x41c 77 78 #define AVIVO_EXT1_PPLL_FB_DIV 0x430 79 #define AVIVO_EXT2_PPLL_FB_DIV 0x434 80 81 #define AVIVO_EXT1_PPLL_POST_DIV_SRC 0x438 82 #define AVIVO_EXT1_PPLL_POST_DIV 0x43c 83 84 #define AVIVO_EXT2_PPLL_POST_DIV_SRC 0x440 85 #define AVIVO_EXT2_PPLL_POST_DIV 0x444 86 87 #define AVIVO_EXT1_PPLL_CNTL 0x448 88 #define AVIVO_EXT2_PPLL_CNTL 0x44c 89 90 #define AVIVO_P1PLL_CNTL 0x450 91 #define AVIVO_P2PLL_CNTL 0x454 92 #define AVIVO_P1PLL_INT_SS_CNTL 0x458 93 #define AVIVO_P2PLL_INT_SS_CNTL 0x45c 94 #define AVIVO_P1PLL_TMDSA_CNTL 0x460 95 #define AVIVO_P2PLL_LVTMA_CNTL 0x464 96 97 #define AVIVO_PCLK_CRTC1_CNTL 0x480 98 #define AVIVO_PCLK_CRTC2_CNTL 0x484 99 100 /* first crtc */ 101 #define AVIVO_D1CRTC_H_TOTAL 0x6000 102 #define AVIVO_D1CRTC_H_BLANK_START_END 0x6004 103 #define AVIVO_D1CRTC_H_SYNC_A 0x6008 104 #define AVIVO_D1CRTC_H_SYNC_A_CNTL 0x600C 105 #define AVIVO_D1CRTC_H_SYNC_B 0x6010 106 #define AVIVO_D1CRTC_H_SYNC_B_CNTL 0x6014 107 108 #define AVIVO_D1CRTC_V_TOTAL 0x6020 109 #define AVIVO_D1CRTC_V_BLANK_START_END 0x6024 110 #define AVIVO_D1CRTC_V_SYNC_A 0x6028 111 #define AVIVO_D1CRTC_V_SYNC_A_CNTL 0x602C 112 #define AVIVO_D1CRTC_V_SYNC_B 0x6030 113 #define AVIVO_D1CRTC_V_SYNC_B_CNTL 0x6034 114 115 #define AVIVO_D1CRTC_CONTROL 0x6080 116 #define AVIVO_CRTC_EN (1 << 0) 117 #define AVIVO_CRTC_DISP_READ_REQUEST_DISABLE (1 << 24) 118 #define AVIVO_D1CRTC_BLANK_CONTROL 0x6084 119 #define AVIVO_D1CRTC_INTERLACE_CONTROL 0x6088 120 #define AVIVO_D1CRTC_INTERLACE_STATUS 0x608C 121 #define AVIVO_D1CRTC_STATUS 0x609C 122 #define AVIVO_D1CRTC_STATUS_POSITION 0x60A0 123 #define AVIVO_D1CRTC_FRAME_COUNT 0x60A4 124 #define AVIVO_D1CRTC_STEREO_CONTROL 0x60C4 125 126 #define AVIVO_D1MODE_MASTER_UPDATE_MODE 0x60e4 127 128 /* master controls */ 129 #define AVIVO_DC_CRTC_MASTER_EN 0x60f8 130 #define AVIVO_DC_CRTC_TV_CONTROL 0x60fc 131 132 #define AVIVO_D1GRPH_ENABLE 0x6100 133 #define AVIVO_D1GRPH_CONTROL 0x6104 134 #define AVIVO_D1GRPH_CONTROL_DEPTH_8BPP (0 << 0) 135 #define AVIVO_D1GRPH_CONTROL_DEPTH_16BPP (1 << 0) 136 #define AVIVO_D1GRPH_CONTROL_DEPTH_32BPP (2 << 0) 137 #define AVIVO_D1GRPH_CONTROL_DEPTH_64BPP (3 << 0) 138 139 #define AVIVO_D1GRPH_CONTROL_8BPP_INDEXED (0 << 8) 140 141 #define AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555 (0 << 8) 142 #define AVIVO_D1GRPH_CONTROL_16BPP_RGB565 (1 << 8) 143 #define AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444 (2 << 8) 144 #define AVIVO_D1GRPH_CONTROL_16BPP_AI88 (3 << 8) 145 #define AVIVO_D1GRPH_CONTROL_16BPP_MONO16 (4 << 8) 146 147 #define AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888 (0 << 8) 148 #define AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010 (1 << 8) 149 #define AVIVO_D1GRPH_CONTROL_32BPP_DIGITAL (2 << 8) 150 #define AVIVO_D1GRPH_CONTROL_32BPP_8B_ARGB2101010 (3 << 8) 151 152 153 #define AVIVO_D1GRPH_CONTROL_64BPP_ARGB16161616 (0 << 8) 154 155 #define AVIVO_D1GRPH_SWAP_RB (1 << 16) 156 #define AVIVO_D1GRPH_TILED (1 << 20) 157 #define AVIVO_D1GRPH_MACRO_ADDRESS_MODE (1 << 21) 158 159 #define R600_D1GRPH_ARRAY_MODE_LINEAR_GENERAL (0 << 20) 160 #define R600_D1GRPH_ARRAY_MODE_LINEAR_ALIGNED (1 << 20) 161 #define R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1 (2 << 20) 162 #define R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1 (4 << 20) 163 164 /* The R7xx *_HIGH surface regs are backwards; the D1 regs are in the D2 165 * block and vice versa. This applies to GRPH, CUR, etc. 166 */ 167 #define AVIVO_D1GRPH_LUT_SEL 0x6108 168 #define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 169 #define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 170 #define AVIVO_D1GRPH_PITCH 0x6120 171 #define AVIVO_D1GRPH_SURFACE_OFFSET_X 0x6124 172 #define AVIVO_D1GRPH_SURFACE_OFFSET_Y 0x6128 173 #define AVIVO_D1GRPH_X_START 0x612c 174 #define AVIVO_D1GRPH_Y_START 0x6130 175 #define AVIVO_D1GRPH_X_END 0x6134 176 #define AVIVO_D1GRPH_Y_END 0x6138 177 #define AVIVO_D1GRPH_UPDATE 0x6144 178 #define AVIVO_D1GRPH_SURFACE_UPDATE_PENDING (1 << 2) 179 #define AVIVO_D1GRPH_UPDATE_LOCK (1 << 16) 180 #define AVIVO_D1GRPH_FLIP_CONTROL 0x6148 181 #define AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN (1 << 0) 182 183 #define AVIVO_D1CUR_CONTROL 0x6400 184 #define AVIVO_D1CURSOR_EN (1 << 0) 185 #define AVIVO_D1CURSOR_MODE_SHIFT 8 186 #define AVIVO_D1CURSOR_MODE_MASK (3 << 8) 187 #define AVIVO_D1CURSOR_MODE_24BPP 2 188 #define AVIVO_D1CUR_SURFACE_ADDRESS 0x6408 189 #define R700_D1CUR_SURFACE_ADDRESS_HIGH 0x6c0c 190 #define R700_D2CUR_SURFACE_ADDRESS_HIGH 0x640c 191 #define AVIVO_D1CUR_SIZE 0x6410 192 #define AVIVO_D1CUR_POSITION 0x6414 193 #define AVIVO_D1CUR_HOT_SPOT 0x6418 194 #define AVIVO_D1CUR_UPDATE 0x6424 195 #define AVIVO_D1CURSOR_UPDATE_LOCK (1 << 16) 196 197 #define AVIVO_DC_LUT_RW_SELECT 0x6480 198 #define AVIVO_DC_LUT_RW_MODE 0x6484 199 #define AVIVO_DC_LUT_RW_INDEX 0x6488 200 #define AVIVO_DC_LUT_SEQ_COLOR 0x648c 201 #define AVIVO_DC_LUT_PWL_DATA 0x6490 202 #define AVIVO_DC_LUT_30_COLOR 0x6494 203 #define AVIVO_DC_LUT_READ_PIPE_SELECT 0x6498 204 #define AVIVO_DC_LUT_WRITE_EN_MASK 0x649c 205 #define AVIVO_DC_LUT_AUTOFILL 0x64a0 206 207 #define AVIVO_DC_LUTA_CONTROL 0x64c0 208 #define AVIVO_DC_LUTA_BLACK_OFFSET_BLUE 0x64c4 209 #define AVIVO_DC_LUTA_BLACK_OFFSET_GREEN 0x64c8 210 #define AVIVO_DC_LUTA_BLACK_OFFSET_RED 0x64cc 211 #define AVIVO_DC_LUTA_WHITE_OFFSET_BLUE 0x64d0 212 #define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4 213 #define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8 214 215 #define AVIVO_DC_LB_MEMORY_SPLIT 0x6520 216 #define AVIVO_DC_LB_MEMORY_SPLIT_MASK 0x3 217 #define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT 0 218 #define AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0 219 #define AVIVO_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1 220 #define AVIVO_DC_LB_MEMORY_SPLIT_D1_ONLY 2 221 #define AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3 222 #define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2) 223 #define AVIVO_DC_LB_DISP1_END_ADR_SHIFT 4 224 #define AVIVO_DC_LB_DISP1_END_ADR_MASK 0x7ff 225 226 #define AVIVO_D1MODE_DATA_FORMAT 0x6528 227 #define AVIVO_D1MODE_INTERLEAVE_EN (1 << 0) 228 #define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652C 229 #define AVIVO_D1MODE_VBLANK_STATUS 0x6534 230 #define AVIVO_VBLANK_ACK (1 << 4) 231 #define AVIVO_D1MODE_VLINE_START_END 0x6538 232 #define AVIVO_D1MODE_VLINE_STATUS 0x653c 233 #define AVIVO_D1MODE_VLINE_STAT (1 << 12) 234 #define AVIVO_DxMODE_INT_MASK 0x6540 235 #define AVIVO_D1MODE_INT_MASK (1 << 0) 236 #define AVIVO_D2MODE_INT_MASK (1 << 8) 237 #define AVIVO_D1MODE_VIEWPORT_START 0x6580 238 #define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584 239 #define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588 240 #define AVIVO_D1MODE_EXT_OVERSCAN_TOP_BOTTOM 0x658c 241 242 #define AVIVO_D1SCL_SCALER_ENABLE 0x6590 243 #define AVIVO_D1SCL_SCALER_TAP_CONTROL 0x6594 244 #define AVIVO_D1SCL_UPDATE 0x65cc 245 #define AVIVO_D1SCL_UPDATE_LOCK (1 << 16) 246 247 /* second crtc */ 248 #define AVIVO_D2CRTC_H_TOTAL 0x6800 249 #define AVIVO_D2CRTC_H_BLANK_START_END 0x6804 250 #define AVIVO_D2CRTC_H_SYNC_A 0x6808 251 #define AVIVO_D2CRTC_H_SYNC_A_CNTL 0x680c 252 #define AVIVO_D2CRTC_H_SYNC_B 0x6810 253 #define AVIVO_D2CRTC_H_SYNC_B_CNTL 0x6814 254 255 #define AVIVO_D2CRTC_V_TOTAL 0x6820 256 #define AVIVO_D2CRTC_V_BLANK_START_END 0x6824 257 #define AVIVO_D2CRTC_V_SYNC_A 0x6828 258 #define AVIVO_D2CRTC_V_SYNC_A_CNTL 0x682c 259 #define AVIVO_D2CRTC_V_SYNC_B 0x6830 260 #define AVIVO_D2CRTC_V_SYNC_B_CNTL 0x6834 261 262 #define AVIVO_D2CRTC_CONTROL 0x6880 263 #define AVIVO_D2CRTC_BLANK_CONTROL 0x6884 264 #define AVIVO_D2CRTC_INTERLACE_CONTROL 0x6888 265 #define AVIVO_D2CRTC_INTERLACE_STATUS 0x688C 266 #define AVIVO_D2CRTC_STATUS 0x689C 267 #define AVIVO_D2CRTC_STATUS_POSITION 0x68A0 268 #define AVIVO_D2CRTC_FRAME_COUNT 0x68A4 269 #define AVIVO_D2CRTC_STEREO_CONTROL 0x68C4 270 #define AVIVO_D2CRTC_UPDATE_LOCK 0x68E8 271 272 #define AVIVO_D2GRPH_ENABLE 0x6900 273 #define AVIVO_D2GRPH_CONTROL 0x6904 274 #define AVIVO_D2GRPH_LUT_SEL 0x6908 275 #define AVIVO_D2GRPH_SWAP_CNTL 0x690C 276 #define AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910 277 #define AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918 278 #define AVIVO_D2GRPH_PITCH 0x6920 279 #define AVIVO_D2GRPH_SURFACE_OFFSET_X 0x6924 280 #define AVIVO_D2GRPH_SURFACE_OFFSET_Y 0x6928 281 #define AVIVO_D2GRPH_X_START 0x692c 282 #define AVIVO_D2GRPH_Y_START 0x6930 283 #define AVIVO_D2GRPH_X_END 0x6934 284 #define AVIVO_D2GRPH_Y_END 0x6938 285 #define AVIVO_D2GRPH_UPDATE 0x6944 286 #define AVIVO_D2GRPH_FLIP_CONTROL 0x6948 287 288 #define AVIVO_D2CUR_CONTROL 0x6c00 289 #define AVIVO_D2CUR_SURFACE_ADDRESS 0x6c08 290 #define AVIVO_D2CUR_SIZE 0x6c10 291 #define AVIVO_D2CUR_POSITION 0x6c14 292 293 #define AVIVO_D2MODE_VBLANK_STATUS 0x6d34 294 #define AVIVO_D2MODE_VLINE_START_END 0x6d38 295 #define AVIVO_D2MODE_VLINE_STATUS 0x6d3c 296 #define AVIVO_D2MODE_VIEWPORT_START 0x6d80 297 #define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84 298 #define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88 299 #define AVIVO_D2MODE_EXT_OVERSCAN_TOP_BOTTOM 0x6d8c 300 301 #define AVIVO_D2SCL_SCALER_ENABLE 0x6d90 302 #define AVIVO_D2SCL_SCALER_TAP_CONTROL 0x6d94 303 304 #define AVIVO_DDIA_BIT_DEPTH_CONTROL 0x7214 305 306 #define AVIVO_DP_VID_STREAM_CNTL 0x770C 307 308 #define AVIVO_DACA_ENABLE 0x7800 309 #define AVIVO_DAC_ENABLE (1 << 0) 310 #define AVIVO_DACA_SOURCE_SELECT 0x7804 311 #define AVIVO_DAC_SOURCE_CRTC1 (0 << 0) 312 #define AVIVO_DAC_SOURCE_CRTC2 (1 << 0) 313 #define AVIVO_DAC_SOURCE_TV (2 << 0) 314 315 #define AVIVO_DACA_FORCE_OUTPUT_CNTL 0x783c 316 #define AVIVO_DACA_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0) 317 #define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8) 318 #define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0) 319 #define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1) 320 #define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2) 321 #define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24) 322 #define AVIVO_DACA_POWERDOWN 0x7850 323 #define AVIVO_DACA_POWERDOWN_POWERDOWN (1 << 0) 324 #define AVIVO_DACA_POWERDOWN_BLUE (1 << 8) 325 #define AVIVO_DACA_POWERDOWN_GREEN (1 << 16) 326 #define AVIVO_DACA_POWERDOWN_RED (1 << 24) 327 328 #define AVIVO_DACB_ENABLE 0x7a00 329 #define AVIVO_DACB_SOURCE_SELECT 0x7a04 330 #define AVIVO_DACB_FORCE_OUTPUT_CNTL 0x7a3c 331 #define AVIVO_DACB_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0) 332 #define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8) 333 #define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0) 334 #define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1) 335 #define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2) 336 #define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24) 337 #define AVIVO_DACB_POWERDOWN 0x7a50 338 #define AVIVO_DACB_POWERDOWN_POWERDOWN (1 << 0) 339 #define AVIVO_DACB_POWERDOWN_BLUE (1 << 8) 340 #define AVIVO_DACB_POWERDOWN_GREEN (1 << 16) 341 #define AVIVO_DACB_POWERDOWN_RED (1 << 24) 342 343 #define AVIVO_TMDSA_CNTL 0x7880 344 #define AVIVO_TMDSA_CNTL_ENABLE (1 << 0) 345 #define AVIVO_TMDSA_CNTL_HPD_MASK (1 << 4) 346 #define AVIVO_TMDSA_CNTL_HPD_SELECT (1 << 8) 347 #define AVIVO_TMDSA_CNTL_SYNC_PHASE (1 << 12) 348 #define AVIVO_TMDSA_CNTL_PIXEL_ENCODING (1 << 16) 349 #define AVIVO_TMDSA_CNTL_DUAL_LINK_ENABLE (1 << 24) 350 #define AVIVO_TMDSA_CNTL_SWAP (1 << 28) 351 #define AVIVO_TMDSA_SOURCE_SELECT 0x7884 352 /* 78a8 appears to be some kind of (reasonably tolerant) clock? 353 * 78d0 definitely hits the transmitter, definitely clock. */ 354 /* MYSTERY1 This appears to control dithering? */ 355 #define AVIVO_TMDSA_BIT_DEPTH_CONTROL 0x7894 356 #define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0) 357 #define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4) 358 #define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8) 359 #define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12) 360 #define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16) 361 #define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20) 362 #define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24) 363 #define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26) 364 #define AVIVO_TMDSA_DCBALANCER_CONTROL 0x78d0 365 #define AVIVO_TMDSA_DCBALANCER_CONTROL_EN (1 << 0) 366 #define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_EN (1 << 8) 367 #define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16) 368 #define AVIVO_TMDSA_DCBALANCER_CONTROL_FORCE (1 << 24) 369 #define AVIVO_TMDSA_DATA_SYNCHRONIZATION 0x78d8 370 #define AVIVO_TMDSA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0) 371 #define AVIVO_TMDSA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8) 372 #define AVIVO_TMDSA_CLOCK_ENABLE 0x7900 373 #define AVIVO_TMDSA_TRANSMITTER_ENABLE 0x7904 374 #define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX0_ENABLE (1 << 0) 375 #define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1) 376 #define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2) 377 #define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3) 378 #define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4) 379 #define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX1_ENABLE (1 << 8) 380 #define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10) 381 #define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11) 382 #define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12) 383 #define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX_ENABLE_HPD_MASK (1 << 16) 384 #define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17) 385 #define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18) 386 387 #define AVIVO_TMDSA_TRANSMITTER_CONTROL 0x7910 388 #define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0) 389 #define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1) 390 #define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2) 391 #define AVIVO_TMDSA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4) 392 #define AVIVO_TMDSA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5) 393 #define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6) 394 #define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK (1 << 8) 395 #define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13) 396 #define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK (1 << 14) 397 #define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15) 398 #define AVIVO_TMDSA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16) 399 #define AVIVO_TMDSA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28) 400 #define AVIVO_TMDSA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29) 401 #define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31) 402 403 #define AVIVO_LVTMA_CNTL 0x7a80 404 #define AVIVO_LVTMA_CNTL_ENABLE (1 << 0) 405 #define AVIVO_LVTMA_CNTL_HPD_MASK (1 << 4) 406 #define AVIVO_LVTMA_CNTL_HPD_SELECT (1 << 8) 407 #define AVIVO_LVTMA_CNTL_SYNC_PHASE (1 << 12) 408 #define AVIVO_LVTMA_CNTL_PIXEL_ENCODING (1 << 16) 409 #define AVIVO_LVTMA_CNTL_DUAL_LINK_ENABLE (1 << 24) 410 #define AVIVO_LVTMA_CNTL_SWAP (1 << 28) 411 #define AVIVO_LVTMA_SOURCE_SELECT 0x7a84 412 #define AVIVO_LVTMA_COLOR_FORMAT 0x7a88 413 #define AVIVO_LVTMA_BIT_DEPTH_CONTROL 0x7a94 414 #define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0) 415 #define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4) 416 #define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8) 417 #define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12) 418 #define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16) 419 #define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20) 420 #define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24) 421 #define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26) 422 423 424 425 #define AVIVO_LVTMA_DCBALANCER_CONTROL 0x7ad0 426 #define AVIVO_LVTMA_DCBALANCER_CONTROL_EN (1 << 0) 427 #define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_EN (1 << 8) 428 #define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16) 429 #define AVIVO_LVTMA_DCBALANCER_CONTROL_FORCE (1 << 24) 430 431 #define AVIVO_LVTMA_DATA_SYNCHRONIZATION 0x78d8 432 #define AVIVO_LVTMA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0) 433 #define AVIVO_LVTMA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8) 434 #define R500_LVTMA_CLOCK_ENABLE 0x7b00 435 #define R600_LVTMA_CLOCK_ENABLE 0x7b04 436 437 #define R500_LVTMA_TRANSMITTER_ENABLE 0x7b04 438 #define R600_LVTMA_TRANSMITTER_ENABLE 0x7b08 439 #define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1) 440 #define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2) 441 #define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3) 442 #define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4) 443 #define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD03EN (1 << 5) 444 #define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC1EN (1 << 9) 445 #define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10) 446 #define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11) 447 #define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12) 448 #define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17) 449 #define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18) 450 451 #define R500_LVTMA_TRANSMITTER_CONTROL 0x7b10 452 #define R600_LVTMA_TRANSMITTER_CONTROL 0x7b14 453 #define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0) 454 #define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1) 455 #define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2) 456 #define AVIVO_LVTMA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4) 457 #define AVIVO_LVTMA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5) 458 #define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6) 459 #define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK (1 << 8) 460 #define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13) 461 #define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK (1 << 14) 462 #define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15) 463 #define AVIVO_LVTMA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16) 464 #define AVIVO_LVTMA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28) 465 #define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29) 466 #define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31) 467 468 #define R500_LVTMA_PWRSEQ_CNTL 0x7af0 469 #define R600_LVTMA_PWRSEQ_CNTL 0x7af4 470 #define AVIVO_LVTMA_PWRSEQ_EN (1 << 0) 471 #define AVIVO_LVTMA_PWRSEQ_PLL_ENABLE_MASK (1 << 2) 472 #define AVIVO_LVTMA_PWRSEQ_PLL_RESET_MASK (1 << 3) 473 #define AVIVO_LVTMA_PWRSEQ_TARGET_STATE (1 << 4) 474 #define AVIVO_LVTMA_SYNCEN (1 << 8) 475 #define AVIVO_LVTMA_SYNCEN_OVRD (1 << 9) 476 #define AVIVO_LVTMA_SYNCEN_POL (1 << 10) 477 #define AVIVO_LVTMA_DIGON (1 << 16) 478 #define AVIVO_LVTMA_DIGON_OVRD (1 << 17) 479 #define AVIVO_LVTMA_DIGON_POL (1 << 18) 480 #define AVIVO_LVTMA_BLON (1 << 24) 481 #define AVIVO_LVTMA_BLON_OVRD (1 << 25) 482 #define AVIVO_LVTMA_BLON_POL (1 << 26) 483 484 #define R500_LVTMA_PWRSEQ_STATE 0x7af4 485 #define R600_LVTMA_PWRSEQ_STATE 0x7af8 486 #define AVIVO_LVTMA_PWRSEQ_STATE_TARGET_STATE_R (1 << 0) 487 #define AVIVO_LVTMA_PWRSEQ_STATE_DIGON (1 << 1) 488 #define AVIVO_LVTMA_PWRSEQ_STATE_SYNCEN (1 << 2) 489 #define AVIVO_LVTMA_PWRSEQ_STATE_BLON (1 << 3) 490 #define AVIVO_LVTMA_PWRSEQ_STATE_DONE (1 << 4) 491 #define AVIVO_LVTMA_PWRSEQ_STATE_STATUS_SHIFT (8) 492 493 #define AVIVO_LVDS_BACKLIGHT_CNTL 0x7af8 494 #define AVIVO_LVDS_BACKLIGHT_CNTL_EN (1 << 0) 495 #define AVIVO_LVDS_BACKLIGHT_LEVEL_MASK 0x0000ff00 496 #define AVIVO_LVDS_BACKLIGHT_LEVEL_SHIFT 8 497 498 #define AVIVO_DVOA_BIT_DEPTH_CONTROL 0x7988 499 500 #define AVIVO_DC_GPIO_HPD_A 0x7e94 501 #define AVIVO_DC_GPIO_HPD_Y 0x7e9c 502 503 #define AVIVO_DC_I2C_STATUS1 0x7d30 504 #define AVIVO_DC_I2C_DONE (1 << 0) 505 #define AVIVO_DC_I2C_NACK (1 << 1) 506 #define AVIVO_DC_I2C_HALT (1 << 2) 507 #define AVIVO_DC_I2C_GO (1 << 3) 508 #define AVIVO_DC_I2C_RESET 0x7d34 509 #define AVIVO_DC_I2C_SOFT_RESET (1 << 0) 510 #define AVIVO_DC_I2C_ABORT (1 << 8) 511 #define AVIVO_DC_I2C_CONTROL1 0x7d38 512 #define AVIVO_DC_I2C_START (1 << 0) 513 #define AVIVO_DC_I2C_STOP (1 << 1) 514 #define AVIVO_DC_I2C_RECEIVE (1 << 2) 515 #define AVIVO_DC_I2C_EN (1 << 8) 516 #define AVIVO_DC_I2C_PIN_SELECT(x) ((x) << 16) 517 #define AVIVO_SEL_DDC1 0 518 #define AVIVO_SEL_DDC2 1 519 #define AVIVO_SEL_DDC3 2 520 #define AVIVO_DC_I2C_CONTROL2 0x7d3c 521 #define AVIVO_DC_I2C_ADDR_COUNT(x) ((x) << 0) 522 #define AVIVO_DC_I2C_DATA_COUNT(x) ((x) << 8) 523 #define AVIVO_DC_I2C_CONTROL3 0x7d40 524 #define AVIVO_DC_I2C_DATA_DRIVE_EN (1 << 0) 525 #define AVIVO_DC_I2C_DATA_DRIVE_SEL (1 << 1) 526 #define AVIVO_DC_I2C_CLK_DRIVE_EN (1 << 7) 527 #define AVIVO_DC_I2C_RD_INTRA_BYTE_DELAY(x) ((x) << 8) 528 #define AVIVO_DC_I2C_WR_INTRA_BYTE_DELAY(x) ((x) << 16) 529 #define AVIVO_DC_I2C_TIME_LIMIT(x) ((x) << 24) 530 #define AVIVO_DC_I2C_DATA 0x7d44 531 #define AVIVO_DC_I2C_INTERRUPT_CONTROL 0x7d48 532 #define AVIVO_DC_I2C_INTERRUPT_STATUS (1 << 0) 533 #define AVIVO_DC_I2C_INTERRUPT_AK (1 << 8) 534 #define AVIVO_DC_I2C_INTERRUPT_ENABLE (1 << 16) 535 #define AVIVO_DC_I2C_ARBITRATION 0x7d50 536 #define AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C (1 << 0) 537 #define AVIVO_DC_I2C_SW_CAN_USE_I2C (1 << 1) 538 #define AVIVO_DC_I2C_SW_DONE_USING_I2C (1 << 8) 539 #define AVIVO_DC_I2C_HW_NEEDS_I2C (1 << 9) 540 #define AVIVO_DC_I2C_ABORT_HDCP_I2C (1 << 16) 541 #define AVIVO_DC_I2C_HW_USING_I2C (1 << 17) 542 543 #define AVIVO_DC_GPIO_DDC1_MASK 0x7e40 544 #define AVIVO_DC_GPIO_DDC1_A 0x7e44 545 #define AVIVO_DC_GPIO_DDC1_EN 0x7e48 546 #define AVIVO_DC_GPIO_DDC1_Y 0x7e4c 547 548 #define AVIVO_DC_GPIO_DDC2_MASK 0x7e50 549 #define AVIVO_DC_GPIO_DDC2_A 0x7e54 550 #define AVIVO_DC_GPIO_DDC2_EN 0x7e58 551 #define AVIVO_DC_GPIO_DDC2_Y 0x7e5c 552 553 #define AVIVO_DC_GPIO_DDC3_MASK 0x7e60 554 #define AVIVO_DC_GPIO_DDC3_A 0x7e64 555 #define AVIVO_DC_GPIO_DDC3_EN 0x7e68 556 #define AVIVO_DC_GPIO_DDC3_Y 0x7e6c 557 558 #define AVIVO_DISP_INTERRUPT_STATUS 0x7edc 559 #define AVIVO_D1_VBLANK_INTERRUPT (1 << 4) 560 #define AVIVO_D2_VBLANK_INTERRUPT (1 << 5) 561 562 563 #endif /* __AVIVO_REG_H__ */ 564