1 /* $NetBSD: gcscaudioreg.h,v 1.1 2008/12/28 15:16:25 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2008 SHIMIZU Ryo <ryo@nerv.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef _I386_PCI_GCSCAUDIOREG_H_ 30 #define _I386_PCI_GCSCAUDIOREG_H_ 31 32 /* 33 * Reference: 34 * - AMD Geode CS5536 Companion Device Data Book 35 * http://www.amd.com/files/connectivitysolutions/geode/geode_lx/33238G_cs5536_db.pdf 36 */ 37 38 #define ACC_GLD_MSR_CAP 0x51500000 /* GeodeLinkDevice Capabilities */ 39 40 /* 41 * AC97 Audio Codec Controller (ACC) Registers 42 */ 43 #define ACC_GPIO_STATUS 0x00 /* Codec GPIO Status Register */ 44 # define ACC_GPIO_STATUS_GPIO_EN 0x80000000 /* GPIO Enable */ 45 # define ACC_GPIO_STATUS_INT_EN 0x40000000 /* Codec GPIO Interrupt Enable */ 46 # define ACC_GPIO_STATUS_WU_INT_EN 0x20000000 /* Codec GPIO Wakeup Interrupt Enable */ 47 # define ACC_GPIO_STATUS_INT_FLAG 0x00200000 /* Codec GPIO Interrupt Flag (Read to Clear) */ 48 # define ACC_GPIO_STATUS_WU_INT_FLAG 0x00100000 /* Codec GPIO Wakeup Interrupt Flag (Read to Clear) */ 49 # define ACC_GPIO_STATUS_PIN_STS_MASK 0x000fffff /* Codec GPIO Pin Status (Read Only) */ 50 51 #define ACC_GPIO_CNTL 0x04 /* Codec GPIO Control Register */ 52 # define ACC_GPIO_CNTL_PIN_DATA_MASK 0x000fffff /* Codec GPIO Pin Data */ 53 54 #define ACC_CODEC_REG2ADDR(reg) (((reg) & 0x7f) << 24) 55 #define ACC_CODEC_ADDR2REG(adr) (((adr) >> 24) & 0x7f) 56 57 #define ACC_CODEC_STATUS 0x08 /* Codec Status Register */ 58 # define ACC_CODEC_STATUS_STS_ADD_MASK 0xff000000 /* Codec Status Address (Read Only) */ 59 # define ACC_CODEC_STATUS_PRM_RDY_STS 0x00800000 /* Primary Codec Ready (Read Only) */ 60 # define ACC_CODEC_STATUS_SEC_RDY_STS 0x00400000 /* Secondary Codec Ready (Read Only) */ 61 # define ACC_CODEC_STATUS_SDATAIN2_EN 0x00200000 /* Enable Second Serial Data Input (AC_S_IN2) */ 62 # define ACC_CODEC_STATUS_BM5_SEL 0x00100000 /* Audio Bus Master 5 AC97 Slot Select */ 63 # define ACC_CODEC_STATUS_BM4_SEL 0x00080000 /* Audio Bus Master 4 AC97 Slot Select */ 64 # define ACC_CODEC_STATUS_STS_NEW 0x00020000 /* Codec Status New (Read to Clear) */ 65 # define ACC_CODEC_STATUS_STS_DATA_MASK 0x0000ffff /* Codec Status Data (Read Only) */ 66 67 #define ACC_CODEC_CNTL 0x0c /* Codec Control Register */ 68 # define ACC_CODEC_CNTL_RW_CMD 0x80000000 /* Codec Read/Write Command */ 69 # define ACC_CODEC_CNTL_READ_CMD 0x80000000 /* Codec Read Command */ 70 # define ACC_CODEC_CNTL_WRITE_CMD 0x00000000 /* Codec Write Command */ 71 # define ACC_CODEC_CNTL_ADD_MASK 0x7f000000 /* CMD_ADD Codec Command Address */ 72 # define ACC_CODEC_CNTL_COMM_SEL_MASK 0x00c00000 /* COMM_SEL Audio Codec Communication */ 73 # define ACC_CODEC_CNTL_PD_PRIM 0x00200000 /* Power-down Semaphore for Primary Codec */ 74 # define ACC_CODEC_CNTL_PD_SEC 0x00100000 /* Power-down Semaphore for Secondary Codec */ 75 # define ACC_CODEC_CNTL_LNK_SHTDWN 0x00040000 /* AC Link Shutdown */ 76 # define ACC_CODEC_CNTL_LNK_WRM_RST 0x00020000 /* AC Link Warm Reset */ 77 # define ACC_CODEC_CNTL_CMD_NEW 0x00010000 /* Codec Command New */ 78 # define ACC_CODEC_CNTL_CMD_DATA_MASK 0x0000ffff /* Codec Command Data */ 79 80 #define ACC_IRQ_STATUS 0x12 /* Second Level Audio IRQ Status Register */ 81 # define ACC_IRQ_STATUS_BM7_IRQ_STS 0x0200 /* Audio Bus Master 7 IRQ Status */ 82 # define ACC_IRQ_STATUS_BM6_IRQ_STS 0x0100 /* Audio Bus Master 6 IRQ Status */ 83 # define ACC_IRQ_STATUS_BM5_IRQ_STS 0x0080 /* Audio Bus Master 5 IRQ Status */ 84 # define ACC_IRQ_STATUS_BM4_IRQ_STS 0x0040 /* Audio Bus Master 4 IRQ Status */ 85 # define ACC_IRQ_STATUS_BM3_IRQ_STS 0x0020 /* Audio Bus Master 3 IRQ Status */ 86 # define ACC_IRQ_STATUS_BM2_IRQ_STS 0x0010 /* Audio Bus Master 2 IRQ Status */ 87 # define ACC_IRQ_STATUS_BM1_IRQ_STS 0x0008 /* Audio Bus Master 1 IRQ Status */ 88 # define ACC_IRQ_STATUS_BM0_IRQ_STS 0x0004 /* Audio Bus Master 0 IRQ Status */ 89 # define ACC_IRQ_STATUS_WU_IRQ_STS 0x0002 /* Codec GPIO Wakeup IRQ Status */ 90 # define ACC_IRQ_STATUS_IRQ_STS 0x0001 /* Codec GPIO IRQ Status */ 91 92 #define ACC_ENGINE_CNTL 0x14 /* Bus Master Engine Control Register */ 93 # define ACC_ENGINE_CNTL_SSND_MODE 0x00000001 /* Surround Sound (5.1) Synchronization Mode */ 94 95 #define ACC_BM0_CMD 0x20 /* Bus Master 0 Command */ 96 #define ACC_BM0_STATUS 0x21 /* Bus Master 0 IRQ Status */ 97 #define ACC_BM0_PRD 0x24 /* Bus Master 0 PRD Table Address */ 98 #define ACC_BM1_CMD 0x28 /* Bus Master 1 Command */ 99 #define ACC_BM1_STATUS 0x29 /* Bus Master 1 IRQ Status */ 100 #define ACC_BM1_PRD 0x2c /* Bus Master 1 PRD Table Address */ 101 #define ACC_BM2_CMD 0x30 /* Bus Master 2 Command */ 102 #define ACC_BM2_STATUS 0x31 /* Bus Master 2 IRQ Status */ 103 #define ACC_BM2_PRD 0x34 /* Bus Master 2 PRD Table Address */ 104 #define ACC_BM3_CMD 0x38 /* Bus Master 3 Command */ 105 #define ACC_BM3_STATUS 0x39 /* Bus Master 3 IRQ Status */ 106 #define ACC_BM3_PRD 0x3c /* Bus Master 3 PRD Table Address */ 107 #define ACC_BM4_CMD 0x40 /* Bus Master 4 Command */ 108 #define ACC_BM4_STATUS 0x41 /* Bus Master 4 IRQ Status */ 109 #define ACC_BM4_PRD 0x44 /* Bus Master 4 PRD Table Address */ 110 #define ACC_BM5_CMD 0x48 /* Bus Master 5 Command */ 111 #define ACC_BM5_STATUS 0x49 /* Bus Master 5 IRQ Status */ 112 #define ACC_BM5_PRD 0x4c /* Bus Master 5 PRD Table Address */ 113 #define ACC_BM6_CMD 0x50 /* Bus Master 6 Command */ 114 #define ACC_BM6_STATUS 0x51 /* Bus Master 6 IRQ Status */ 115 #define ACC_BM6_PRD 0x54 /* Bus Master 6 PRD Table Address */ 116 #define ACC_BM7_CMD 0x58 /* Bus Master 7 Command */ 117 #define ACC_BM7_STATUS 0x59 /* Bus Master 7 IRQ Status */ 118 #define ACC_BM7_PRD 0x5c /* Bus Master 7 PRD Table Address */ 119 # define ACC_BMx_CMD_RW_MASK 0x08 120 # define ACC_BMx_CMD_READ 0x08 /* Codec to Memory */ 121 # define ACC_BMx_CMD_WRITE 0x00 /* Memory to Codec */ 122 # define ACC_BMx_CMD_BYTE_ORD_MASK 0x04 123 # define ACC_BMx_CMD_BYTE_ORD_EL 0x00 /* Little Endian */ 124 # define ACC_BMx_CMD_BYTE_ORD_EB 0x04 /* Big Endian */ 125 # define ACC_BMx_CMD_BM_CTL_MASK 0x03 126 # define ACC_BMx_CMD_BM_CTL_DISABLE 0x00 /* Disable bus master */ 127 # define ACC_BMx_CMD_BM_CTL_ENABLE 0x01 /* Enable bus master */ 128 # define ACC_BMx_CMD_BM_CTL_PAUSE 0x03 /* Pause bus master */ 129 # define ACC_BMx_STATUS_BM_EOP_ERR 0x02 /* Bus Master Error */ 130 # define ACC_BMx_STATUS_EOP 0x01 /* End of Page */ 131 132 /* PRD - Physical Region Descriptor Table (addressed by ACC_BMx_PRD) */ 133 struct acc_prd { 134 uint32 address; 135 uint32 ctrlsize; 136 #define ACC_BMx_PRD_CTRL_EOT 0x80000000 137 #define ACC_BMx_PRD_CTRL_EOP 0x40000000 138 #define ACC_BMx_PRD_CTRL_JMP 0x20000000 139 #define ACC_BMx_PRD_SIZE_MASK 0x0000ffff 140 }; 141 142 #define ACC_BM0_PNTR 0x60 /* Bus Master 0 DMA Pointer */ 143 #define ACC_BM1_PNTR 0x64 /* Bus Master 1 DMA Pointer */ 144 #define ACC_BM2_PNTR 0x68 /* Bus Master 2 DMA Pointer */ 145 #define ACC_BM3_PNTR 0x6C /* Bus Master 3 DMA Pointer */ 146 #define ACC_BM4_PNTR 0x70 /* Bus Master 4 DMA Pointer */ 147 #define ACC_BM5_PNTR 0x74 /* Bus Master 5 DMA Pointer */ 148 #define ACC_BM6_PNTR 0x78 /* Bus Master 6 DMA Pointer */ 149 #define ACC_BM7_PNTR 0x7C /* Bus Master 7 DMA Pointer */ 150 151 #endif /* _I386_PCI_GCSCAUDIOREG_H_ */ 152