Searched hist:cbd4081064f0aee215b62407ecfd0462cdc204ff (Results 1 – 5 of 5) sorted by relevance
| /haiku/src/add-ons/accelerants/intel_extreme/ |
| H A D | accelerant_protos.h | cbd4081064f0aee215b62407ecfd0462cdc204ff Mon Sep 24 09:02:35 UTC 2007 Axel Dörfler <axeld@pinc-software.de> * Fixed PLL timing computation for the i9xx chips - I mixed post2 min/max values, and did
not take the VCO limits into account; both could (and would during testing) create invalid
frequencies.
* Also reverted the order in which the PLL divisors are traversed to match the order of what
is used in the X driver to create comparable output (our error computation is based on float,
though, and should therefore create more accurate values).
* The i965 introduced a special register for the surface; the former display base register
is now only used for the view offset. Instead of setting the base manually here and there,
there is now a set_frame_buffer_base() function.
* The DPMS code will now also turn off/on the PLL clock generator.
* The code needs some more cleanup, and while the driver now produces the correct timing on
my i965 system, I'm now greeted by a black screen after startup.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@22289 a95241bf-73f2-0310-859d-f6bbb57e9c96
|
| H A D | dpms.cpp | cbd4081064f0aee215b62407ecfd0462cdc204ff Mon Sep 24 09:02:35 UTC 2007 Axel Dörfler <axeld@pinc-software.de> * Fixed PLL timing computation for the i9xx chips - I mixed post2 min/max values, and did
not take the VCO limits into account; both could (and would during testing) create invalid
frequencies.
* Also reverted the order in which the PLL divisors are traversed to match the order of what
is used in the X driver to create comparable output (our error computation is based on float,
though, and should therefore create more accurate values).
* The i965 introduced a special register for the surface; the former display base register
is now only used for the view offset. Instead of setting the base manually here and there,
there is now a set_frame_buffer_base() function.
* The DPMS code will now also turn off/on the PLL clock generator.
* The code needs some more cleanup, and while the driver now produces the correct timing on
my i965 system, I'm now greeted by a black screen after startup.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@22289 a95241bf-73f2-0310-859d-f6bbb57e9c96
|
| H A D | accelerant.h | cbd4081064f0aee215b62407ecfd0462cdc204ff Mon Sep 24 09:02:35 UTC 2007 Axel Dörfler <axeld@pinc-software.de> * Fixed PLL timing computation for the i9xx chips - I mixed post2 min/max values, and did
not take the VCO limits into account; both could (and would during testing) create invalid
frequencies.
* Also reverted the order in which the PLL divisors are traversed to match the order of what
is used in the X driver to create comparable output (our error computation is based on float,
though, and should therefore create more accurate values).
* The i965 introduced a special register for the surface; the former display base register
is now only used for the view offset. Instead of setting the base manually here and there,
there is now a set_frame_buffer_base() function.
* The DPMS code will now also turn off/on the PLL clock generator.
* The code needs some more cleanup, and while the driver now produces the correct timing on
my i965 system, I'm now greeted by a black screen after startup.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@22289 a95241bf-73f2-0310-859d-f6bbb57e9c96
|
| H A D | mode.cpp | cbd4081064f0aee215b62407ecfd0462cdc204ff Mon Sep 24 09:02:35 UTC 2007 Axel Dörfler <axeld@pinc-software.de> * Fixed PLL timing computation for the i9xx chips - I mixed post2 min/max values, and did
not take the VCO limits into account; both could (and would during testing) create invalid
frequencies.
* Also reverted the order in which the PLL divisors are traversed to match the order of what
is used in the X driver to create comparable output (our error computation is based on float,
though, and should therefore create more accurate values).
* The i965 introduced a special register for the surface; the former display base register
is now only used for the view offset. Instead of setting the base manually here and there,
there is now a set_frame_buffer_base() function.
* The DPMS code will now also turn off/on the PLL clock generator.
* The code needs some more cleanup, and while the driver now produces the correct timing on
my i965 system, I'm now greeted by a black screen after startup.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@22289 a95241bf-73f2-0310-859d-f6bbb57e9c96
|
| /haiku/headers/private/graphics/intel_extreme/ |
| H A D | intel_extreme.h | cbd4081064f0aee215b62407ecfd0462cdc204ff Mon Sep 24 09:02:35 UTC 2007 Axel Dörfler <axeld@pinc-software.de> * Fixed PLL timing computation for the i9xx chips - I mixed post2 min/max values, and did
not take the VCO limits into account; both could (and would during testing) create invalid
frequencies.
* Also reverted the order in which the PLL divisors are traversed to match the order of what
is used in the X driver to create comparable output (our error computation is based on float,
though, and should therefore create more accurate values).
* The i965 introduced a special register for the surface; the former display base register
is now only used for the view offset. Instead of setting the base manually here and there,
there is now a set_frame_buffer_base() function.
* The DPMS code will now also turn off/on the PLL clock generator.
* The code needs some more cleanup, and while the driver now produces the correct timing on
my i965 system, I'm now greeted by a black screen after startup.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@22289 a95241bf-73f2-0310-859d-f6bbb57e9c96
|