Searched hist:"83 f755b5d82174d560d2bf4a6b84a304df436ea2" (Results 1 – 3 of 3) sorted by relevance
| /haiku/src/system/kernel/arch/arm/ |
| H A D | arch_cpu.cpp | 83f755b5d82174d560d2bf4a6b84a304df436ea2 Sat Apr 23 08:12:48 UTC 2022 David Karoly <karolyd577@gmail.com> kernel/arm: add memory barriers for page table ops
Introduce memory barriers according to ARMARM,
section G.5.3 TLB maintenance operations and barriers
Sequence for mapping memory in (both L1 and L2):
* DSB
* Invalidate i-cache (TODO)
* Insert new entry in page directory / page table
* DSB
* ISB
Sequence for mapping memory out:
* Remove page table entry
* DSB
* Invalidate TLB entry
* DSB
* ISB
Sequence for updating a page table entry:
* Update page table entry
* DSB
* Invalidate TLB entry
* Invalidate branch predictor (TODO)
* DSB
* ISB
Note: i-cache invalidation and branch predictor invalidation is
not implemented yet as this commit focuses on implementing memory
barriers.
Change-Id: I192fa80f6b43117236a4be6fa8c988afca90e015
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5241
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
Reviewed-by: Fredrik Holmqvist <fredrik.holmqvist@gmail.com>
|
| /haiku/headers/private/kernel/arch/arm/ |
| H A D | arch_cpu.h | 83f755b5d82174d560d2bf4a6b84a304df436ea2 Sat Apr 23 08:12:48 UTC 2022 David Karoly <karolyd577@gmail.com> kernel/arm: add memory barriers for page table ops
Introduce memory barriers according to ARMARM,
section G.5.3 TLB maintenance operations and barriers
Sequence for mapping memory in (both L1 and L2):
* DSB
* Invalidate i-cache (TODO)
* Insert new entry in page directory / page table
* DSB
* ISB
Sequence for mapping memory out:
* Remove page table entry
* DSB
* Invalidate TLB entry
* DSB
* ISB
Sequence for updating a page table entry:
* Update page table entry
* DSB
* Invalidate TLB entry
* Invalidate branch predictor (TODO)
* DSB
* ISB
Note: i-cache invalidation and branch predictor invalidation is
not implemented yet as this commit focuses on implementing memory
barriers.
Change-Id: I192fa80f6b43117236a4be6fa8c988afca90e015
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5241
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
Reviewed-by: Fredrik Holmqvist <fredrik.holmqvist@gmail.com>
|
| /haiku/src/system/kernel/arch/arm/paging/32bit/ |
| H A D | ARMPagingMethod32Bit.cpp | 83f755b5d82174d560d2bf4a6b84a304df436ea2 Sat Apr 23 08:12:48 UTC 2022 David Karoly <karolyd577@gmail.com> kernel/arm: add memory barriers for page table ops
Introduce memory barriers according to ARMARM,
section G.5.3 TLB maintenance operations and barriers
Sequence for mapping memory in (both L1 and L2):
* DSB
* Invalidate i-cache (TODO)
* Insert new entry in page directory / page table
* DSB
* ISB
Sequence for mapping memory out:
* Remove page table entry
* DSB
* Invalidate TLB entry
* DSB
* ISB
Sequence for updating a page table entry:
* Update page table entry
* DSB
* Invalidate TLB entry
* Invalidate branch predictor (TODO)
* DSB
* ISB
Note: i-cache invalidation and branch predictor invalidation is
not implemented yet as this commit focuses on implementing memory
barriers.
Change-Id: I192fa80f6b43117236a4be6fa8c988afca90e015
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5241
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
Reviewed-by: Fredrik Holmqvist <fredrik.holmqvist@gmail.com>
|