1 /* 2 Copyright 1999, Be Incorporated. All Rights Reserved. 3 This file may be used under the terms of the Be Sample Code License. 4 */ 5 6 #ifndef _SYM53C8XX_H 7 #define _SYM53C8XX_H 8 9 /*======================================================================*/ 10 /* operating registers definitions */ 11 12 #define sym_scntl0 0x00 /* scsi control 0 */ 13 #define sym_scntl1 0x01 /* scsi control 1 */ 14 #define sym_scntl2 0x02 /* scsi control 2 */ 15 #define sym_scntl3 0x03 /* scsi control 3 */ 16 #define sym_scid 0x04 /* scsi chip ID */ 17 #define sym_sxfer 0x05 /* scsi transfer */ 18 #define sym_sdid 0x06 /* scsi destination ID */ 19 #define sym_gpreg 0x07 /* general purpose bits */ 20 #define sym_sfbr 0x08 /* scsi first byte received */ 21 #define sym_socl 0x09 /* scsi output control latch */ 22 #define sym_ssid 0x0a /* scsi selector ID */ 23 #define sym_sbcl 0x0b /* scsi bus control lines */ 24 #define sym_dstat 0x0c /* dma status */ 25 #define sym_sstat0 0x0d /* scsi status 0 */ 26 #define sym_sstat1 0x0e /* scsi status 1 */ 27 #define sym_sstat2 0x0f /* scsi status 2 */ 28 #define sym_dsa 0x10 /* data structure address [4 bytes] */ 29 #define sym_istat 0x14 /* interrupt status */ 30 #define sym_ctest0 0x18 /* chip test 0 */ 31 #define sym_ctest1 0x19 /* chip test 1 */ 32 #define sym_ctest2 0x1a /* chip test 2 */ 33 #define sym_ctest3 0x1b /* chip test 3 */ 34 #define sym_temp 0x1c /* temporary stack [4 bytes] */ 35 #define sym_dfifo 0x20 /* dma fifo */ 36 #define sym_ctest4 0x21 /* chip test 4 */ 37 #define sym_ctest5 0x22 /* chip test 5 */ 38 #define sym_ctest6 0x23 /* chip test 6 */ 39 #define sym_dbc 0x24 /* dma byte counter [3 bytes] */ 40 #define sym_dcmd 0x27 /* dma command */ 41 #define sym_dnad 0x28 /* dma next address for data [4 bytes] */ 42 #define sym_dsp 0x2c /* dma scripts pointer [4 bytes] */ 43 #define sym_dsps 0x30 /* dma scripts pointer save [4 bytes] */ 44 #define sym_scratcha 0x34 /* general purpose scratch pad a [4 bytes] */ 45 #define sym_dmode 0x38 /* dma mode */ 46 #define sym_dien 0x39 /* dma interrupt enable */ 47 #define sym_dwt 0x3a /* dma watchdog timer */ 48 #define sym_dcntl 0x3b /* dma control */ 49 #define sym_adder 0x3c /* sum output of internal adder [4 bytes] */ 50 #define sym_sien0 0x40 /* scsi interrupt enable 0 */ 51 #define sym_sien1 0x41 /* scsi interrupt enable 1 */ 52 #define sym_sist0 0x42 /* scsi interrupt status 0 */ 53 #define sym_sist1 0x43 /* scsi interrupt status 1 */ 54 #define sym_slpar 0x44 /* scsi longitudinal parity */ 55 #define sym_macntl 0x46 /* memory access control */ 56 #define sym_gpcntl 0x47 /* general purpose control */ 57 #define sym_stime0 0x48 /* scsi timer 0 */ 58 #define sym_stime1 0x49 /* scsi timer 1 */ 59 #define sym_respid 0x4a /* responce ID */ 60 #define sym_stest0 0x4c /* scsi test 0 */ 61 #define sym_stest1 0x4d /* scsi test 1 */ 62 #define sym_stest2 0x4e /* scsi test 2 */ 63 #define sym_stest3 0x4f /* scsi test 3 */ 64 #define sym_sidl 0x50 /* scsi input data latch */ 65 #define sym_stest4 0x52 /* new with 895/896 */ 66 #define sym_sodl 0x54 /* scsi output data latch */ 67 #define sym_sbdl 0x58 /* scsi bus data lines */ 68 #define sym_scratchb 0x5c /* general purpose scratch pad b [4 bytes] */ 69 70 71 /*----------------------------------------------------------------------*/ 72 /* operating registers bit definitions */ 73 74 /* 0x00 - scntl0 (scsi control 0) bit definitions */ 75 76 #define sym_scntl0_trg 0x01 /* target mode [1 = target, 0 = initiator */ 77 #define sym_scntl0_aap 0x02 /* assert SATN on parity */ 78 #define sym_scntl0_epc 0x08 /* enable parity checking */ 79 #define sym_scntl0_watn 0x10 /* select with SATN on a start sequence */ 80 #define sym_scntl0_start 0x20 /* start sequence */ 81 #define sym_scntl0_arb0 0x40 /* arbitration mode bit 0 */ 82 #define sym_scntl0_arb1 0x80 /* arbitration mode bit 1 */ 83 84 85 /* 0x01 - scntl1 (scsi control 1) bit definitions */ 86 87 #define sym_scntl1_sst 0x01 /* start scsi transfer */ 88 #define sym_scntl1_iarb 0x02 /* immediate arbitration */ 89 #define sym_scntl1_aesp 0x04 /* assert even scsi parity (force bad parity) */ 90 #define sym_scntl1_rst 0x08 /* assert scsi RST signal */ 91 #define sym_scntl1_con 0x10 /* connected */ 92 #define sym_scntl1_dhp 0x20 /* disable halt on parity error or ATN */ 93 #define sym_scntl1_adb 0x40 /* assert scsi data bus */ 94 #define sym_scntl1_exc 0x80 /* extra clock cycle of data setup */ 95 96 97 /* 0x02 - scntl2 (scsi control 2) bit definitions */ 98 99 #define sym_scntl2_sdu 0x80 /* scsi disconnect unexpected */ 100 101 102 /* 0x03 - scntl3 (scsi control 3) bit definitions */ 103 104 #define sym_scntl3_ccf 0x07 /* clock conversion factor [mask] */ 105 #define sym_scntl3_scf 0x70 /* synchronous clock conversion factor [mask] */ 106 107 108 /* 0x04 - scid (scsi chip id) bit definitions */ 109 110 #define sym_scid_enc 0x07 /* encoded scsi id [mask] */ 111 #define sym_scid_sre 0x20 /* enable responce to selection */ 112 #define sym_scid_rre 0x40 /* enable responce to reselection */ 113 114 115 /* 0x05 - sxfer (scsi transfer) bit definitions */ 116 117 #define sym_sxfer_mo 0x0f /* max scsi synchronous offset [mask] */ 118 #define sym_sxfer_tp 0xe0 /* scsi synchronous transfer period [mask] */ 119 120 121 /* 0x06 - sdid (scsi destination id) bit definitions */ 122 123 #define sym_sdid_enc 0x07 /* encoded destination scsi id [mask] */ 124 125 126 /* 0x07 - gpreg (general purpose) bit definitions */ 127 128 #define sym_gpreg_gpio0 0x01 /* general purpose */ 129 #define sym_gpreg_gpio1 0x02 /* general purpose */ 130 131 132 /* 0x09 - socl (scsi output control latch) bit definitions */ 133 134 #define sym_socl_io 0x01 /* assert i/o signal */ 135 #define sym_socl_cd 0x02 /* assert c/d signal */ 136 #define sym_socl_msg 0x04 /* assert msg signal */ 137 #define sym_socl_atn 0x08 /* assert atn signal */ 138 #define sym_socl_sel 0x10 /* assert sel signal */ 139 #define sym_socl_bsy 0x20 /* assert bsy signal */ 140 #define sym_socl_ack 0x40 /* assert ack signal */ 141 #define sym_socl_req 0x80 /* assert req signal */ 142 143 144 /* 0x0a - ssid (scsi selector id) bit definitions */ 145 146 #define sym_ssid_encid 0x07 /* encoded destination scsi id [mask] */ 147 #define sym_ssid_val 0x80 /* scsi valid bit */ 148 149 150 /* 0x0b - sbcl (scsi bus control lines) bit definitions */ 151 152 #define sym_sbcl_io 0x01 /* i/o status */ 153 #define sym_sbcl_cd 0x02 /* c/d status */ 154 #define sym_sbcl_msg 0x04 /* msg status */ 155 #define sym_sbcl_atn 0x08 /* atn status */ 156 #define sym_sbcl_sel 0x10 /* sel status */ 157 #define sym_sbcl_bsy 0x20 /* bsy status */ 158 #define sym_sbcl_ack 0x40 /* ack status */ 159 #define sym_sbcl_req 0x80 /* req status */ 160 161 162 /* 0x0c - dstat (dma status) bit definitions */ 163 164 #define sym_dstat_iid 0x01 /* illegal instruction detected */ 165 #define sym_dstat_sir 0x04 /* scripts interrupt instruction received */ 166 #define sym_dstat_ssi 0x08 /* single step interrupt */ 167 #define sym_dstat_abrt 0x10 /* aborted */ 168 #define sym_dstat_bf 0x20 /* bus fault */ 169 #define sym_dstat_mdpe 0x40 /* master data parity error */ 170 #define sym_dstat_dfe 0x80 /* dma fifo empty */ 171 172 173 /* 0x0d - sstat0 (scsi status 0) bit definitions */ 174 175 #define sym_sstat0_sdp 0x01 /* scsi parity signal */ 176 #define sym_sstat0_rst 0x02 /* scsi reset signal */ 177 #define sym_sstat0_woa 0x04 /* won arbitration */ 178 #define sym_sstat0_loa 0x08 /* lost arbitration */ 179 #define sym_sstat0_aip 0x10 /* arbitration in progress */ 180 #define sym_sstat0_olf 0x20 /* scsi output data latch full */ 181 #define sym_sstat0_orf 0x40 /* scsi output data register full */ 182 #define sym_sstat0_ilf 0x80 /* scsi input data latch full */ 183 184 185 /* 0x0e - sstat1 (scsi status 1) bit definitions */ 186 187 #define sym_sstat1_io 0x01 /* scsi i/o signal */ 188 #define sym_sstat1_cd 0x02 /* scsi c/d signal */ 189 #define sym_sstat1_msg 0x04 /* scsi msg signal */ 190 #define sym_sstat1_sdpl 0x08 /* latched scsi parity */ 191 #define sym_sstat1_fifo 0xf0 /* mask for fifo flags [mask] */ 192 193 194 /* 0x0f - sstat2 (scsi status 2) bit definitions */ 195 196 #define sym_sstat2_ldsc 0x02 /* last disconnect */ 197 198 199 /* 0x14 - istat (interrupt status) bit definitions */ 200 201 #define sym_istat_dip 0x01 /* dma interrupt pending */ 202 #define sym_istat_sip 0x02 /* scsi interrupt pending */ 203 #define sym_istat_intf 0x04 /* interrupt on the fly */ 204 #define sym_istat_con 0x08 /* connected */ 205 #define sym_istat_sem 0x10 /* semaphore */ 206 #define sym_istat_sigp 0x20 /* signal process */ 207 #define sym_istat_srst 0x40 /* software reset */ 208 #define sym_istat_abrt 0x80 /* abort operation */ 209 210 211 /* 0x19 - ctest1 (chip test 1) bit definitions */ 212 213 #define sym_ctest1_ffl 0x0f /* byte empty in dma fifo [mask] */ 214 #define sym_ctest1_fmt 0xf0 /* byte full in dma fifo [mask] */ 215 216 217 /* 0x1a - ctest2 (chip test 2) bit definitions */ 218 219 #define sym_ctest2_dack 0x01 /* data acknowledge status */ 220 #define sym_ctest2_dreq 0x02 /* data request status */ 221 #define sym_ctest2_teop 0x04 /* scsi true end of process */ 222 #define sym_ctest2_cm 0x10 /* configured as memory */ 223 #define sym_ctest2_cio 0x20 /* configured as i/o */ 224 #define sym_ctest2_sigp 0x40 /* signal process */ 225 #define sym_ctest2_ddir 0x80 /* data transfer direction */ 226 227 228 /* 0x1b - ctest3 (chip test 3) bit definitions */ 229 230 #define sym_ctest3_fm 0x02 /* fetch pin mode */ 231 #define sym_ctest3_clf 0x04 /* clear dma fifo */ 232 #define sym_ctest3_flf 0x08 /* flush dma fifo */ 233 #define sym_ctest3_v 0xf0 /* chip revision level [mask] */ 234 235 236 /* 0x20 - dfifo (dma fifo) bit definitions */ 237 238 #define sym_dfifo_bo 0x7f /* byte offset counter */ 239 240 241 /* 0x21 - ctest4 (chip test 4) bit definitions */ 242 243 #define sym_ctest4_fbl 0x07 /* fifo byte control [mask] */ 244 #define sym_ctest4_mpee 0x08 /* master parity error enable */ 245 #define sym_ctest4_srtm 0x10 /* shadow register test mode */ 246 #define sym_ctest4_zsd 0x20 /* scsi data high impedance */ 247 #define sym_ctest4_zmod 0x40 /* high impedance mode */ 248 #define sym_ctest4_bdis 0x80 /* burst disable */ 249 250 /* 0x22 - ctest5 (chip test 5) bit definitions */ 251 252 #define sym_ctest5_ddir 0x08 /* dma direction */ 253 #define sym_ctest5_masr 0x10 /* master control for set or reset pulses */ 254 #define sym_ctest5_bbck 0x40 /* clock byte counter */ 255 #define sym_ctest5_adck 0x80 /* clock address incrementor */ 256 257 258 /* 0x38 - dmode (dma mode) bit definitions */ 259 260 #define sym_dmode_man 0x01 /* manual start mode */ 261 #define sym_dmode_erl 0x08 /* enable read line */ 262 #define sym_dmode_diom 0x10 /* destination i/o memory enable */ 263 #define sym_dmode_siom 0x20 /* source i/o memory enable */ 264 #define sym_dmode_bl 0xc0 /* burst length */ 265 266 267 /* 0x39 - dien (dma interrupt enable) bit definitions */ 268 269 #define sym_dien_iid 0x01 /* illegal instruction detected */ 270 #define sym_dien_sir 0x04 /* scripts interrupt instruction received */ 271 #define sym_dien_ssi 0x08 /* single step instruction */ 272 #define sym_dien_abrt 0x10 /* aborted */ 273 #define sym_dien_bf 0x20 /* bus fault */ 274 #define sym_dien_mdpe 0x40 /* master data parity error */ 275 276 277 /* 0x3b - dcntl (dma control) bit definitions */ 278 279 #define sym_dcntl_com 0x01 /* 53c700 compatibility */ 280 #define sym_dcntl_std 0x04 /* start dma operation */ 281 #define sym_dcntl_irqm 0x08 /* irq mode */ 282 #define sym_dcntl_ssm 0x10 /* single step mode */ 283 284 285 /* 0x40 - sien0 (scsi interrupt enable 0) bit definitions */ 286 287 #define sym_sien0_par 0x01 /* scsi parity error */ 288 #define sym_sien0_rst 0x02 /* scsi reset condition */ 289 #define sym_sien0_udc 0x04 /* unexpected disconnect */ 290 #define sym_sien0_sge 0x08 /* scsi gross error */ 291 #define sym_sien0_rsl 0x10 /* reselected */ 292 #define sym_sien0_sel 0x20 /* selected */ 293 #define sym_sien0_cmp 0x40 /* function complete */ 294 #define sym_sien0_ma 0x80 /* scsi phase mismatch or scsi atn condition */ 295 296 297 /* 0x41 - sien1 (scsi interrupt enable 1) bit definitions */ 298 299 #define sym_sien1_hth 0x01 /* handshake to handshake timer expired */ 300 #define sym_sien1_gen 0x02 /* general purpose timer expired */ 301 #define sym_sien1_sto 0x04 /* selection or reselection timeout */ 302 #define sym_sien1_sbmc 0x10 /* SCSI Bus Mode Change */ 303 304 /* 0x42 - sist0 (scsi interrupt status 0) bit definitions */ 305 306 #define sym_sist0_par 0x01 /* parity error */ 307 #define sym_sist0_rst 0x02 /* scsi rst/received */ 308 #define sym_sist0_udc 0x04 /* unexpected disconnect */ 309 #define sym_sist0_sge 0x08 /* scsi gross error */ 310 #define sym_sist0_rsl 0x10 /* reselected */ 311 #define sym_sist0_sel 0x20 /* selected */ 312 #define sym_sist0_cmp 0x40 /* function complete */ 313 #define sym_sist0_ma 0x80 /* scsi phase mismatch or scsi atn condition */ 314 315 316 /* 0x43 - sist1 (scsi interrupt status 1) bit definitions */ 317 318 #define sym_sist1_hth 0x01 /* handshake to handshake timer expired */ 319 #define sym_sist1_gen 0x02 /* general purpose timer expired */ 320 #define sym_sist1_sto 0x04 /* selection or reselection timeout */ 321 #define sym_sist1_sbmc 0x10 /* SCSI Bus Mode Change */ 322 323 /* 0x46 - macntl (memory access control) bit definitions */ 324 325 #define sym_macntl_scpts 0x01 /* scripts */ 326 #define sym_macntl_pscpt 0x02 /* pointer scripts */ 327 #define sym_macntl_drd 0x04 /* data read */ 328 #define sym_macntl_dwr 0x08 /* data write */ 329 #define sym_macntl_typ 0xf0 /* chip type [mask] */ 330 331 332 /* 0x47 - gpcntl (general purpose pin control) bit definitions */ 333 334 #define sym_gpcntl_gpio0 0x01 /* gpio 0 */ 335 #define sym_gpcntl_gpio1 0x02 /* gpio 1 */ 336 #define sym_gpcntl_fe 0x40 /* fetch enable */ 337 #define sym_gpcntl_me 0x80 /* master enable */ 338 339 340 /* 0x48 - stime0 (scsi timer 0) bit definitions */ 341 342 #define sym_stime0_sel 0x07 /* selection time-out [mask] */ 343 #define sym_stime0_hth 0xf8 /* handshake to handshake timer period [mask] */ 344 345 346 /* 0x49 - stime1 (scsi timer 1) bit definitions */ 347 348 #define sym_stime1_gen 0x0f /* general purpose timer period [mask] */ 349 350 351 /* 0x4c - stest0 (scsi test 0) bit definitions */ 352 353 #define sym_stest0_som 0x01 /* scsi synchronous offset maximum */ 354 #define sym_stest0_soz 0x02 /* scsi synchronous offset zero */ 355 #define sym_stest0_art 0x04 /* arbitration priority encoder test */ 356 #define sym_stest0_slt 0x08 /* selection response logic test */ 357 358 359 /* 0x4d - stest1 (scsi test 1) bit definitions */ 360 361 #define sym_stest1_sclk 0x80 /* sclk */ 362 363 364 /* 0x4e - stest2 (scsi test 2) bit definitions */ 365 366 #define sym_stest2_low 0x01 /* scsi low level mode */ 367 #define sym_stest2_ext 0x02 /* extend sreq/sack filtering */ 368 #define sym_stest2_szm 0x08 /* scsi high-impedance mode */ 369 #define sym_stest2_slb 0x10 /* scsi loopback mode */ 370 #define sym_stest2_rof 0x40 /* reset scsi offset */ 371 #define sym_stest2_sce 0x80 /* scsi control enable */ 372 373 374 /* 0x4f - stest3 (scsi test 3) bit definitions */ 375 376 #define sym_stest3_stw 0x01 /* scsi fifo test write */ 377 #define sym_stest3_csf 0x02 /* clear scsi fifo */ 378 #define sym_stest3_ttm 0x04 /* timer test mode */ 379 #define sym_stest3_dsi 0x10 /* disable single initiator response */ 380 #define sym_stest3_hsc 0x20 /* halt scsi clock */ 381 #define sym_stest3_str 0x40 /* scsi fifo test read */ 382 #define sym_stest3_te 0x80 /* tolerant enable */ 383 384 #define sym_stest4_hvd 0x40 /* high voltage diff */ 385 #define sym_stest4_se 0x80 /* single ended */ 386 #define sym_stest4_lvd 0xc0 /* low voltage diff */ 387 #define sym_stest4_lock 0x20 /* clock quadrupler locker */ 388 389 #endif 390