1 /* $OpenBSD: if_sk.c,v 2.33 2003/08/12 05:23:06 nate Exp $ */
2
3 /*-
4 * SPDX-License-Identifier: BSD-4-Clause
5 *
6 * Copyright (c) 1997, 1998, 1999, 2000
7 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by Bill Paul.
20 * 4. Neither the name of the author nor the names of any co-contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGE.
35 */
36 /*-
37 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
38 *
39 * Permission to use, copy, modify, and distribute this software for any
40 * purpose with or without fee is hereby granted, provided that the above
41 * copyright notice and this permission notice appear in all copies.
42 *
43 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
44 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
45 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
46 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
47 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
48 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
49 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
50 */
51
52 #include <sys/cdefs.h>
53 /*
54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
55 * the SK-984x series adapters, both single port and dual port.
56 * References:
57 * The XaQti XMAC II datasheet,
58 * https://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
59 * The SysKonnect GEnesis manual, http://www.syskonnect.com
60 *
61 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the
62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
63 * convenience to others until Vitesse corrects this problem:
64 *
65 * https://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
66 *
67 * Written by Bill Paul <wpaul@ee.columbia.edu>
68 * Department of Electrical Engineering
69 * Columbia University, New York City
70 */
71 /*
72 * The SysKonnect gigabit ethernet adapters consist of two main
73 * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
74 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
75 * components and a PHY while the GEnesis controller provides a PCI
76 * interface with DMA support. Each card may have between 512K and
77 * 2MB of SRAM on board depending on the configuration.
78 *
79 * The SysKonnect GEnesis controller can have either one or two XMAC
80 * chips connected to it, allowing single or dual port NIC configurations.
81 * SysKonnect has the distinction of being the only vendor on the market
82 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
83 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
84 * XMAC registers. This driver takes advantage of these features to allow
85 * both XMACs to operate as independent interfaces.
86 */
87
88 #include <sys/param.h>
89 #include <sys/systm.h>
90 #include <sys/bus.h>
91 #include <sys/endian.h>
92 #include <sys/mbuf.h>
93 #include <sys/malloc.h>
94 #include <sys/kernel.h>
95 #include <sys/module.h>
96 #include <sys/socket.h>
97 #include <sys/sockio.h>
98 #include <sys/queue.h>
99 #include <sys/sysctl.h>
100
101 #include <net/bpf.h>
102 #include <net/ethernet.h>
103 #include <net/if.h>
104 #include <net/if_var.h>
105 #include <net/if_arp.h>
106 #include <net/if_dl.h>
107 #include <net/if_media.h>
108 #include <net/if_types.h>
109 #include <net/if_vlan_var.h>
110
111 #include <netinet/in.h>
112 #include <netinet/in_systm.h>
113 #include <netinet/ip.h>
114
115 #include <machine/bus.h>
116 #include <machine/in_cksum.h>
117 #include <machine/resource.h>
118 #include <sys/rman.h>
119
120 #include <dev/mii/mii.h>
121 #include <dev/mii/miivar.h>
122 #include <dev/mii/brgphyreg.h>
123
124 #include <dev/pci/pcireg.h>
125 #include <dev/pci/pcivar.h>
126
127 #if 0
128 #define SK_USEIOSPACE
129 #endif
130
131 #include <dev/sk/if_skreg.h>
132 #include <dev/sk/xmaciireg.h>
133 #include <dev/sk/yukonreg.h>
134
135 MODULE_DEPEND(sk, pci, 1, 1, 1);
136 MODULE_DEPEND(sk, ether, 1, 1, 1);
137 MODULE_DEPEND(sk, miibus, 1, 1, 1);
138
139 /* "device miibus" required. See GENERIC if you get errors here. */
140 #include "miibus_if.h"
141
142 static const struct sk_type sk_devs[] = {
143 {
144 VENDORID_SK,
145 DEVICEID_SK_V1,
146 "SysKonnect Gigabit Ethernet (V1.0)"
147 },
148 {
149 VENDORID_SK,
150 DEVICEID_SK_V2,
151 "SysKonnect Gigabit Ethernet (V2.0)"
152 },
153 {
154 VENDORID_MARVELL,
155 DEVICEID_SK_V2,
156 "Marvell Gigabit Ethernet"
157 },
158 {
159 VENDORID_MARVELL,
160 DEVICEID_BELKIN_5005,
161 "Belkin F5D5005 Gigabit Ethernet"
162 },
163 {
164 VENDORID_3COM,
165 DEVICEID_3COM_3C940,
166 "3Com 3C940 Gigabit Ethernet"
167 },
168 {
169 VENDORID_LINKSYS,
170 DEVICEID_LINKSYS_EG1032,
171 "Linksys EG1032 Gigabit Ethernet"
172 },
173 {
174 VENDORID_DLINK,
175 DEVICEID_DLINK_DGE530T_A1,
176 "D-Link DGE-530T Gigabit Ethernet"
177 },
178 {
179 VENDORID_DLINK,
180 DEVICEID_DLINK_DGE530T_B1,
181 "D-Link DGE-530T Gigabit Ethernet"
182 },
183 { 0, 0, NULL }
184 };
185
186 static int skc_probe(device_t);
187 static int skc_attach(device_t);
188 static int skc_detach(device_t);
189 static int skc_shutdown(device_t);
190 static int skc_suspend(device_t);
191 static int skc_resume(device_t);
192 static bus_dma_tag_t skc_get_dma_tag(device_t, device_t);
193 static int sk_detach(device_t);
194 static int sk_probe(device_t);
195 static int sk_attach(device_t);
196 static void sk_tick(void *);
197 static void sk_yukon_tick(void *);
198 static void sk_intr(void *);
199 static void sk_intr_xmac(struct sk_if_softc *);
200 static void sk_intr_bcom(struct sk_if_softc *);
201 static void sk_intr_yukon(struct sk_if_softc *);
202 static __inline void sk_rxcksum(if_t, struct mbuf *, u_int32_t);
203 static __inline int sk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t);
204 static void sk_rxeof(struct sk_if_softc *);
205 static void sk_jumbo_rxeof(struct sk_if_softc *);
206 static void sk_txeof(struct sk_if_softc *);
207 static void sk_txcksum(if_t, struct mbuf *, struct sk_tx_desc *);
208 static int sk_encap(struct sk_if_softc *, struct mbuf **);
209 static void sk_start(if_t);
210 static void sk_start_locked(if_t);
211 static int sk_ioctl(if_t, u_long, caddr_t);
212 static void sk_init(void *);
213 static void sk_init_locked(struct sk_if_softc *);
214 static void sk_init_xmac(struct sk_if_softc *);
215 static void sk_init_yukon(struct sk_if_softc *);
216 static void sk_stop(struct sk_if_softc *);
217 static void sk_watchdog(void *);
218 static int sk_ifmedia_upd(if_t);
219 static void sk_ifmedia_sts(if_t, struct ifmediareq *);
220 static void sk_reset(struct sk_softc *);
221 static __inline void sk_discard_rxbuf(struct sk_if_softc *, int);
222 static __inline void sk_discard_jumbo_rxbuf(struct sk_if_softc *, int);
223 static int sk_newbuf(struct sk_if_softc *, int);
224 static int sk_jumbo_newbuf(struct sk_if_softc *, int);
225 static void sk_dmamap_cb(void *, bus_dma_segment_t *, int, int);
226 static int sk_dma_alloc(struct sk_if_softc *);
227 static int sk_dma_jumbo_alloc(struct sk_if_softc *);
228 static void sk_dma_free(struct sk_if_softc *);
229 static void sk_dma_jumbo_free(struct sk_if_softc *);
230 static int sk_init_rx_ring(struct sk_if_softc *);
231 static int sk_init_jumbo_rx_ring(struct sk_if_softc *);
232 static void sk_init_tx_ring(struct sk_if_softc *);
233 static u_int32_t sk_win_read_4(struct sk_softc *, int);
234 static u_int16_t sk_win_read_2(struct sk_softc *, int);
235 static u_int8_t sk_win_read_1(struct sk_softc *, int);
236 static void sk_win_write_4(struct sk_softc *, int, u_int32_t);
237 static void sk_win_write_2(struct sk_softc *, int, u_int32_t);
238 static void sk_win_write_1(struct sk_softc *, int, u_int32_t);
239
240 static int sk_miibus_readreg(device_t, int, int);
241 static int sk_miibus_writereg(device_t, int, int, int);
242 static void sk_miibus_statchg(device_t);
243
244 static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int);
245 static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int,
246 int);
247 static void sk_xmac_miibus_statchg(struct sk_if_softc *);
248
249 static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int);
250 static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int,
251 int);
252 static void sk_marv_miibus_statchg(struct sk_if_softc *);
253
254 static uint32_t sk_xmchash(const uint8_t *);
255 static void sk_setfilt(struct sk_if_softc *, u_int16_t *, int);
256 static void sk_rxfilter(struct sk_if_softc *);
257 static void sk_rxfilter_genesis(struct sk_if_softc *);
258 static void sk_rxfilter_yukon(struct sk_if_softc *);
259
260 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high);
261 static int sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS);
262
263 /* Tunables. */
264 static int jumbo_disable = 0;
265 TUNABLE_INT("hw.skc.jumbo_disable", &jumbo_disable);
266
267 #ifdef __HAIKU__
268 static u_short in_addword(u_short a, u_short b);
269 #endif
270
271 /*
272 * It seems that SK-NET GENESIS supports very simple checksum offload
273 * capability for Tx and I believe it can generate 0 checksum value for
274 * UDP packets in Tx as the hardware can't differenciate UDP packets from
275 * TCP packets. 0 chcecksum value for UDP packet is an invalid one as it
276 * means sender didn't perforam checksum computation. For the safety I
277 * disabled UDP checksum offload capability at the moment. Alternatively
278 * we can intrduce a LINK0/LINK1 flag as hme(4) did in its Tx checksum
279 * offload routine.
280 */
281 #define SK_CSUM_FEATURES (CSUM_TCP)
282
283 /*
284 * Note that we have newbus methods for both the GEnesis controller
285 * itself and the XMAC(s). The XMACs are children of the GEnesis, and
286 * the miibus code is a child of the XMACs. We need to do it this way
287 * so that the miibus drivers can access the PHY registers on the
288 * right PHY. It's not quite what I had in mind, but it's the only
289 * design that achieves the desired effect.
290 */
291 static device_method_t skc_methods[] = {
292 /* Device interface */
293 DEVMETHOD(device_probe, skc_probe),
294 DEVMETHOD(device_attach, skc_attach),
295 DEVMETHOD(device_detach, skc_detach),
296 DEVMETHOD(device_suspend, skc_suspend),
297 DEVMETHOD(device_resume, skc_resume),
298 DEVMETHOD(device_shutdown, skc_shutdown),
299
300 DEVMETHOD(bus_get_dma_tag, skc_get_dma_tag),
301
302 DEVMETHOD_END
303 };
304
305 static driver_t skc_driver = {
306 "skc",
307 skc_methods,
308 sizeof(struct sk_softc)
309 };
310
311 static device_method_t sk_methods[] = {
312 /* Device interface */
313 DEVMETHOD(device_probe, sk_probe),
314 DEVMETHOD(device_attach, sk_attach),
315 DEVMETHOD(device_detach, sk_detach),
316 DEVMETHOD(device_shutdown, bus_generic_shutdown),
317
318 /* MII interface */
319 DEVMETHOD(miibus_readreg, sk_miibus_readreg),
320 DEVMETHOD(miibus_writereg, sk_miibus_writereg),
321 DEVMETHOD(miibus_statchg, sk_miibus_statchg),
322
323 DEVMETHOD_END
324 };
325
326 static driver_t sk_driver = {
327 "sk",
328 sk_methods,
329 sizeof(struct sk_if_softc)
330 };
331
332 DRIVER_MODULE(skc, pci, skc_driver, NULL, NULL);
333 DRIVER_MODULE(sk, skc, sk_driver, NULL, NULL);
334 DRIVER_MODULE(miibus, sk, miibus_driver, NULL, NULL);
335
336 static struct resource_spec sk_res_spec_io[] = {
337 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE },
338 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
339 { -1, 0, 0 }
340 };
341
342 static struct resource_spec sk_res_spec_mem[] = {
343 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
344 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
345 { -1, 0, 0 }
346 };
347
348 #define SK_SETBIT(sc, reg, x) \
349 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
350
351 #define SK_CLRBIT(sc, reg, x) \
352 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
353
354 #define SK_WIN_SETBIT_4(sc, reg, x) \
355 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x)
356
357 #define SK_WIN_CLRBIT_4(sc, reg, x) \
358 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x)
359
360 #define SK_WIN_SETBIT_2(sc, reg, x) \
361 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x)
362
363 #define SK_WIN_CLRBIT_2(sc, reg, x) \
364 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x)
365
366 static u_int32_t
sk_win_read_4(struct sk_softc * sc,int reg)367 sk_win_read_4(struct sk_softc *sc, int reg)
368 {
369 #ifdef SK_USEIOSPACE
370 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
371 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)));
372 #else
373 return(CSR_READ_4(sc, reg));
374 #endif
375 }
376
377 static u_int16_t
sk_win_read_2(struct sk_softc * sc,int reg)378 sk_win_read_2(struct sk_softc *sc, int reg)
379 {
380 #ifdef SK_USEIOSPACE
381 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
382 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)));
383 #else
384 return(CSR_READ_2(sc, reg));
385 #endif
386 }
387
388 static u_int8_t
sk_win_read_1(struct sk_softc * sc,int reg)389 sk_win_read_1(struct sk_softc *sc, int reg)
390 {
391 #ifdef SK_USEIOSPACE
392 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
393 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)));
394 #else
395 return(CSR_READ_1(sc, reg));
396 #endif
397 }
398
399 static void
sk_win_write_4(struct sk_softc * sc,int reg,u_int32_t val)400 sk_win_write_4(struct sk_softc *sc, int reg, u_int32_t val)
401 {
402 #ifdef SK_USEIOSPACE
403 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
404 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val);
405 #else
406 CSR_WRITE_4(sc, reg, val);
407 #endif
408 return;
409 }
410
411 static void
sk_win_write_2(struct sk_softc * sc,int reg,u_int32_t val)412 sk_win_write_2(struct sk_softc *sc, int reg, u_int32_t val)
413 {
414 #ifdef SK_USEIOSPACE
415 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
416 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val);
417 #else
418 CSR_WRITE_2(sc, reg, val);
419 #endif
420 return;
421 }
422
423 static void
sk_win_write_1(struct sk_softc * sc,int reg,u_int32_t val)424 sk_win_write_1(struct sk_softc *sc, int reg, u_int32_t val)
425 {
426 #ifdef SK_USEIOSPACE
427 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
428 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val);
429 #else
430 CSR_WRITE_1(sc, reg, val);
431 #endif
432 return;
433 }
434
435 #ifdef __HAIKU__
436 /* stole these from in_cksum.c */
437 #define ADDCARRY(x) (x > 65535 ? x -= 65535 : x)
438 static u_short
in_addword(u_short a,u_short b)439 in_addword(u_short a, u_short b)
440 {
441 u_int64_t sum = a + b;
442
443 ADDCARRY(sum);
444 return (sum);
445 }
446 #endif
447
448 static int
sk_miibus_readreg(device_t dev,int phy,int reg)449 sk_miibus_readreg(device_t dev, int phy, int reg)
450 {
451 struct sk_if_softc *sc_if;
452 int v;
453
454 sc_if = device_get_softc(dev);
455
456 SK_IF_MII_LOCK(sc_if);
457 switch(sc_if->sk_softc->sk_type) {
458 case SK_GENESIS:
459 v = sk_xmac_miibus_readreg(sc_if, phy, reg);
460 break;
461 case SK_YUKON:
462 case SK_YUKON_LITE:
463 case SK_YUKON_LP:
464 v = sk_marv_miibus_readreg(sc_if, phy, reg);
465 break;
466 default:
467 v = 0;
468 break;
469 }
470 SK_IF_MII_UNLOCK(sc_if);
471
472 return (v);
473 }
474
475 static int
sk_miibus_writereg(device_t dev,int phy,int reg,int val)476 sk_miibus_writereg(device_t dev, int phy, int reg, int val)
477 {
478 struct sk_if_softc *sc_if;
479 int v;
480
481 sc_if = device_get_softc(dev);
482
483 SK_IF_MII_LOCK(sc_if);
484 switch(sc_if->sk_softc->sk_type) {
485 case SK_GENESIS:
486 v = sk_xmac_miibus_writereg(sc_if, phy, reg, val);
487 break;
488 case SK_YUKON:
489 case SK_YUKON_LITE:
490 case SK_YUKON_LP:
491 v = sk_marv_miibus_writereg(sc_if, phy, reg, val);
492 break;
493 default:
494 v = 0;
495 break;
496 }
497 SK_IF_MII_UNLOCK(sc_if);
498
499 return (v);
500 }
501
502 static void
sk_miibus_statchg(device_t dev)503 sk_miibus_statchg(device_t dev)
504 {
505 struct sk_if_softc *sc_if;
506
507 sc_if = device_get_softc(dev);
508
509 SK_IF_MII_LOCK(sc_if);
510 switch(sc_if->sk_softc->sk_type) {
511 case SK_GENESIS:
512 sk_xmac_miibus_statchg(sc_if);
513 break;
514 case SK_YUKON:
515 case SK_YUKON_LITE:
516 case SK_YUKON_LP:
517 sk_marv_miibus_statchg(sc_if);
518 break;
519 }
520 SK_IF_MII_UNLOCK(sc_if);
521
522 return;
523 }
524
525 static int
sk_xmac_miibus_readreg(struct sk_if_softc * sc_if,int phy,int reg)526 sk_xmac_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg)
527 {
528 int i;
529
530 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
531 SK_XM_READ_2(sc_if, XM_PHY_DATA);
532 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
533 for (i = 0; i < SK_TIMEOUT; i++) {
534 DELAY(1);
535 if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
536 XM_MMUCMD_PHYDATARDY)
537 break;
538 }
539
540 if (i == SK_TIMEOUT) {
541 if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
542 return(0);
543 }
544 }
545 DELAY(1);
546 i = SK_XM_READ_2(sc_if, XM_PHY_DATA);
547
548 return(i);
549 }
550
551 static int
sk_xmac_miibus_writereg(struct sk_if_softc * sc_if,int phy,int reg,int val)552 sk_xmac_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val)
553 {
554 int i;
555
556 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
557 for (i = 0; i < SK_TIMEOUT; i++) {
558 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
559 break;
560 }
561
562 if (i == SK_TIMEOUT) {
563 if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
564 return (ETIMEDOUT);
565 }
566
567 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
568 for (i = 0; i < SK_TIMEOUT; i++) {
569 DELAY(1);
570 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
571 break;
572 }
573 if (i == SK_TIMEOUT)
574 if_printf(sc_if->sk_ifp, "phy write timed out\n");
575
576 return(0);
577 }
578
579 static void
sk_xmac_miibus_statchg(struct sk_if_softc * sc_if)580 sk_xmac_miibus_statchg(struct sk_if_softc *sc_if)
581 {
582 struct mii_data *mii;
583
584 mii = device_get_softc(sc_if->sk_miibus);
585
586 /*
587 * If this is a GMII PHY, manually set the XMAC's
588 * duplex mode accordingly.
589 */
590 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
591 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
592 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
593 } else {
594 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
595 }
596 }
597 }
598
599 static int
sk_marv_miibus_readreg(struct sk_if_softc * sc_if,int phy,int reg)600 sk_marv_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg)
601 {
602 u_int16_t val;
603 int i;
604
605 if (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER &&
606 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER) {
607 return(0);
608 }
609
610 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
611 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
612
613 for (i = 0; i < SK_TIMEOUT; i++) {
614 DELAY(1);
615 val = SK_YU_READ_2(sc_if, YUKON_SMICR);
616 if (val & YU_SMICR_READ_VALID)
617 break;
618 }
619
620 if (i == SK_TIMEOUT) {
621 if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
622 return(0);
623 }
624
625 val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
626
627 return(val);
628 }
629
630 static int
sk_marv_miibus_writereg(struct sk_if_softc * sc_if,int phy,int reg,int val)631 sk_marv_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val)
632 {
633 int i;
634
635 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
636 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
637 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
638
639 for (i = 0; i < SK_TIMEOUT; i++) {
640 DELAY(1);
641 if ((SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) == 0)
642 break;
643 }
644 if (i == SK_TIMEOUT)
645 if_printf(sc_if->sk_ifp, "phy write timeout\n");
646
647 return(0);
648 }
649
650 static void
sk_marv_miibus_statchg(struct sk_if_softc * sc_if)651 sk_marv_miibus_statchg(struct sk_if_softc *sc_if)
652 {
653 return;
654 }
655
656 #define HASH_BITS 6
657
658 static u_int32_t
sk_xmchash(const uint8_t * addr)659 sk_xmchash(const uint8_t *addr)
660 {
661 uint32_t crc;
662
663 /* Compute CRC for the address value. */
664 crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
665
666 return (~crc & ((1 << HASH_BITS) - 1));
667 }
668
669 static void
sk_setfilt(struct sk_if_softc * sc_if,u_int16_t * addr,int slot)670 sk_setfilt(struct sk_if_softc *sc_if, u_int16_t *addr, int slot)
671 {
672 int base;
673
674 base = XM_RXFILT_ENTRY(slot);
675
676 SK_XM_WRITE_2(sc_if, base, addr[0]);
677 SK_XM_WRITE_2(sc_if, base + 2, addr[1]);
678 SK_XM_WRITE_2(sc_if, base + 4, addr[2]);
679
680 return;
681 }
682
683 static void
sk_rxfilter(struct sk_if_softc * sc_if)684 sk_rxfilter(struct sk_if_softc *sc_if)
685 {
686 struct sk_softc *sc;
687
688 SK_IF_LOCK_ASSERT(sc_if);
689
690 sc = sc_if->sk_softc;
691 if (sc->sk_type == SK_GENESIS)
692 sk_rxfilter_genesis(sc_if);
693 else
694 sk_rxfilter_yukon(sc_if);
695 }
696
697 struct sk_add_maddr_genesis_ctx {
698 struct sk_if_softc *sc_if;
699 uint32_t hashes[2];
700 uint32_t mode;
701 };
702
703 static u_int
sk_add_maddr_genesis(void * arg,struct sockaddr_dl * sdl,u_int cnt)704 sk_add_maddr_genesis(void *arg, struct sockaddr_dl *sdl, u_int cnt)
705 {
706 struct sk_add_maddr_genesis_ctx *ctx = arg;
707 int h;
708
709 /*
710 * Program the first XM_RXFILT_MAX multicast groups
711 * into the perfect filter.
712 */
713 if (cnt + 1 < XM_RXFILT_MAX) {
714 sk_setfilt(ctx->sc_if, (uint16_t *)LLADDR(sdl), cnt + 1);
715 ctx->mode |= XM_MODE_RX_USE_PERFECT;
716 return (1);
717 }
718 h = sk_xmchash((const uint8_t *)LLADDR(sdl));
719 if (h < 32)
720 ctx->hashes[0] |= (1 << h);
721 else
722 ctx->hashes[1] |= (1 << (h - 32));
723 ctx->mode |= XM_MODE_RX_USE_HASH;
724
725 return (1);
726 }
727
728 static void
sk_rxfilter_genesis(struct sk_if_softc * sc_if)729 sk_rxfilter_genesis(struct sk_if_softc *sc_if)
730 {
731 if_t ifp = sc_if->sk_ifp;
732 struct sk_add_maddr_genesis_ctx ctx = { sc_if, { 0, 0 } };
733 int i;
734 u_int16_t dummy[] = { 0, 0, 0 };
735
736 SK_IF_LOCK_ASSERT(sc_if);
737
738 ctx.mode = SK_XM_READ_4(sc_if, XM_MODE);
739 ctx.mode &= ~(XM_MODE_RX_PROMISC | XM_MODE_RX_USE_HASH |
740 XM_MODE_RX_USE_PERFECT);
741 /* First, zot all the existing perfect filters. */
742 for (i = 1; i < XM_RXFILT_MAX; i++)
743 sk_setfilt(sc_if, dummy, i);
744
745 /* Now program new ones. */
746 if (if_getflags(ifp) & IFF_ALLMULTI || if_getflags(ifp) & IFF_PROMISC) {
747 if (if_getflags(ifp) & IFF_ALLMULTI)
748 ctx.mode |= XM_MODE_RX_USE_HASH;
749 if (if_getflags(ifp) & IFF_PROMISC)
750 ctx.mode |= XM_MODE_RX_PROMISC;
751 ctx.hashes[0] = 0xFFFFFFFF;
752 ctx.hashes[1] = 0xFFFFFFFF;
753 } else
754 /* XXX want to maintain reverse semantics */
755 if_foreach_llmaddr(ifp, sk_add_maddr_genesis, &ctx);
756
757 SK_XM_WRITE_4(sc_if, XM_MODE, ctx.mode);
758 SK_XM_WRITE_4(sc_if, XM_MAR0, ctx.hashes[0]);
759 SK_XM_WRITE_4(sc_if, XM_MAR2, ctx.hashes[1]);
760 }
761
762 static u_int
sk_hash_maddr_yukon(void * arg,struct sockaddr_dl * sdl,u_int cnt)763 sk_hash_maddr_yukon(void *arg, struct sockaddr_dl *sdl, u_int cnt)
764 {
765 uint32_t crc, *hashes = arg;
766
767 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN);
768 /* Just want the 6 least significant bits. */
769 crc &= 0x3f;
770 /* Set the corresponding bit in the hash table. */
771 hashes[crc >> 5] |= 1 << (crc & 0x1f);
772
773 return (1);
774 }
775
776 static void
sk_rxfilter_yukon(struct sk_if_softc * sc_if)777 sk_rxfilter_yukon(struct sk_if_softc *sc_if)
778 {
779 if_t ifp;
780 uint32_t hashes[2] = { 0, 0 }, mode;
781
782 SK_IF_LOCK_ASSERT(sc_if);
783
784 ifp = sc_if->sk_ifp;
785 mode = SK_YU_READ_2(sc_if, YUKON_RCR);
786 if (if_getflags(ifp) & IFF_PROMISC)
787 mode &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN);
788 else if (if_getflags(ifp) & IFF_ALLMULTI) {
789 mode |= YU_RCR_UFLEN | YU_RCR_MUFLEN;
790 hashes[0] = 0xFFFFFFFF;
791 hashes[1] = 0xFFFFFFFF;
792 } else {
793 mode |= YU_RCR_UFLEN;
794 if_foreach_llmaddr(ifp, sk_hash_maddr_yukon, hashes);
795 if (hashes[0] != 0 || hashes[1] != 0)
796 mode |= YU_RCR_MUFLEN;
797 }
798
799 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
800 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
801 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
802 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
803 SK_YU_WRITE_2(sc_if, YUKON_RCR, mode);
804 }
805
806 static int
sk_init_rx_ring(struct sk_if_softc * sc_if)807 sk_init_rx_ring(struct sk_if_softc *sc_if)
808 {
809 struct sk_ring_data *rd;
810 bus_addr_t addr;
811 u_int32_t csum_start;
812 int i;
813
814 sc_if->sk_cdata.sk_rx_cons = 0;
815
816 csum_start = (ETHER_HDR_LEN + sizeof(struct ip)) << 16 |
817 ETHER_HDR_LEN;
818 rd = &sc_if->sk_rdata;
819 bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT);
820 for (i = 0; i < SK_RX_RING_CNT; i++) {
821 if (sk_newbuf(sc_if, i) != 0)
822 return (ENOBUFS);
823 if (i == (SK_RX_RING_CNT - 1))
824 addr = SK_RX_RING_ADDR(sc_if, 0);
825 else
826 addr = SK_RX_RING_ADDR(sc_if, i + 1);
827 rd->sk_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
828 rd->sk_rx_ring[i].sk_csum_start = htole32(csum_start);
829 }
830
831 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
832 sc_if->sk_cdata.sk_rx_ring_map,
833 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
834
835 return(0);
836 }
837
838 static int
sk_init_jumbo_rx_ring(struct sk_if_softc * sc_if)839 sk_init_jumbo_rx_ring(struct sk_if_softc *sc_if)
840 {
841 struct sk_ring_data *rd;
842 bus_addr_t addr;
843 u_int32_t csum_start;
844 int i;
845
846 sc_if->sk_cdata.sk_jumbo_rx_cons = 0;
847
848 csum_start = ((ETHER_HDR_LEN + sizeof(struct ip)) << 16) |
849 ETHER_HDR_LEN;
850 rd = &sc_if->sk_rdata;
851 bzero(rd->sk_jumbo_rx_ring,
852 sizeof(struct sk_rx_desc) * SK_JUMBO_RX_RING_CNT);
853 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
854 if (sk_jumbo_newbuf(sc_if, i) != 0)
855 return (ENOBUFS);
856 if (i == (SK_JUMBO_RX_RING_CNT - 1))
857 addr = SK_JUMBO_RX_RING_ADDR(sc_if, 0);
858 else
859 addr = SK_JUMBO_RX_RING_ADDR(sc_if, i + 1);
860 rd->sk_jumbo_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
861 rd->sk_jumbo_rx_ring[i].sk_csum_start = htole32(csum_start);
862 }
863
864 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
865 sc_if->sk_cdata.sk_jumbo_rx_ring_map,
866 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
867
868 return (0);
869 }
870
871 static void
sk_init_tx_ring(struct sk_if_softc * sc_if)872 sk_init_tx_ring(struct sk_if_softc *sc_if)
873 {
874 struct sk_ring_data *rd;
875 struct sk_txdesc *txd;
876 bus_addr_t addr;
877 int i;
878
879 STAILQ_INIT(&sc_if->sk_cdata.sk_txfreeq);
880 STAILQ_INIT(&sc_if->sk_cdata.sk_txbusyq);
881
882 sc_if->sk_cdata.sk_tx_prod = 0;
883 sc_if->sk_cdata.sk_tx_cons = 0;
884 sc_if->sk_cdata.sk_tx_cnt = 0;
885
886 rd = &sc_if->sk_rdata;
887 bzero(rd->sk_tx_ring, sizeof(struct sk_tx_desc) * SK_TX_RING_CNT);
888 for (i = 0; i < SK_TX_RING_CNT; i++) {
889 if (i == (SK_TX_RING_CNT - 1))
890 addr = SK_TX_RING_ADDR(sc_if, 0);
891 else
892 addr = SK_TX_RING_ADDR(sc_if, i + 1);
893 rd->sk_tx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
894 txd = &sc_if->sk_cdata.sk_txdesc[i];
895 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q);
896 }
897
898 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
899 sc_if->sk_cdata.sk_tx_ring_map,
900 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
901 }
902
903 static __inline void
sk_discard_rxbuf(struct sk_if_softc * sc_if,int idx)904 sk_discard_rxbuf(struct sk_if_softc *sc_if, int idx)
905 {
906 struct sk_rx_desc *r;
907 struct sk_rxdesc *rxd;
908 struct mbuf *m;
909
910 r = &sc_if->sk_rdata.sk_rx_ring[idx];
911 rxd = &sc_if->sk_cdata.sk_rxdesc[idx];
912 m = rxd->rx_m;
913 r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM);
914 }
915
916 static __inline void
sk_discard_jumbo_rxbuf(struct sk_if_softc * sc_if,int idx)917 sk_discard_jumbo_rxbuf(struct sk_if_softc *sc_if, int idx)
918 {
919 struct sk_rx_desc *r;
920 struct sk_rxdesc *rxd;
921 struct mbuf *m;
922
923 r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx];
924 rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx];
925 m = rxd->rx_m;
926 r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM);
927 }
928
929 static int
sk_newbuf(struct sk_if_softc * sc_if,int idx)930 sk_newbuf(struct sk_if_softc *sc_if, int idx)
931 {
932 struct sk_rx_desc *r;
933 struct sk_rxdesc *rxd;
934 struct mbuf *m;
935 bus_dma_segment_t segs[1];
936 bus_dmamap_t map;
937 int nsegs;
938
939 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
940 if (m == NULL)
941 return (ENOBUFS);
942 m->m_len = m->m_pkthdr.len = MCLBYTES;
943 m_adj(m, ETHER_ALIGN);
944
945 if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_rx_tag,
946 sc_if->sk_cdata.sk_rx_sparemap, m, segs, &nsegs, 0) != 0) {
947 m_freem(m);
948 return (ENOBUFS);
949 }
950 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
951
952 rxd = &sc_if->sk_cdata.sk_rxdesc[idx];
953 if (rxd->rx_m != NULL) {
954 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap,
955 BUS_DMASYNC_POSTREAD);
956 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap);
957 }
958 map = rxd->rx_dmamap;
959 rxd->rx_dmamap = sc_if->sk_cdata.sk_rx_sparemap;
960 sc_if->sk_cdata.sk_rx_sparemap = map;
961 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap,
962 BUS_DMASYNC_PREREAD);
963 rxd->rx_m = m;
964 r = &sc_if->sk_rdata.sk_rx_ring[idx];
965 r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr));
966 r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr));
967 r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM);
968
969 return (0);
970 }
971
972 static int
sk_jumbo_newbuf(struct sk_if_softc * sc_if,int idx)973 sk_jumbo_newbuf(struct sk_if_softc *sc_if, int idx)
974 {
975 struct sk_rx_desc *r;
976 struct sk_rxdesc *rxd;
977 struct mbuf *m;
978 bus_dma_segment_t segs[1];
979 bus_dmamap_t map;
980 int nsegs;
981
982 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
983 if (m == NULL)
984 return (ENOBUFS);
985 m->m_pkthdr.len = m->m_len = MJUM9BYTES;
986 /*
987 * Adjust alignment so packet payload begins on a
988 * longword boundary. Mandatory for Alpha, useful on
989 * x86 too.
990 */
991 m_adj(m, ETHER_ALIGN);
992
993 if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_jumbo_rx_tag,
994 sc_if->sk_cdata.sk_jumbo_rx_sparemap, m, segs, &nsegs, 0) != 0) {
995 m_freem(m);
996 return (ENOBUFS);
997 }
998 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
999
1000 rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx];
1001 if (rxd->rx_m != NULL) {
1002 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap,
1003 BUS_DMASYNC_POSTREAD);
1004 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag,
1005 rxd->rx_dmamap);
1006 }
1007 map = rxd->rx_dmamap;
1008 rxd->rx_dmamap = sc_if->sk_cdata.sk_jumbo_rx_sparemap;
1009 sc_if->sk_cdata.sk_jumbo_rx_sparemap = map;
1010 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap,
1011 BUS_DMASYNC_PREREAD);
1012 rxd->rx_m = m;
1013 r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx];
1014 r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr));
1015 r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr));
1016 r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM);
1017
1018 return (0);
1019 }
1020
1021 /*
1022 * Set media options.
1023 */
1024 static int
sk_ifmedia_upd(if_t ifp)1025 sk_ifmedia_upd(if_t ifp)
1026 {
1027 struct sk_if_softc *sc_if = if_getsoftc(ifp);
1028 struct mii_data *mii;
1029
1030 mii = device_get_softc(sc_if->sk_miibus);
1031 sk_init(sc_if);
1032 mii_mediachg(mii);
1033
1034 return(0);
1035 }
1036
1037 /*
1038 * Report current media status.
1039 */
1040 static void
sk_ifmedia_sts(if_t ifp,struct ifmediareq * ifmr)1041 sk_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
1042 {
1043 struct sk_if_softc *sc_if;
1044 struct mii_data *mii;
1045
1046 sc_if = if_getsoftc(ifp);
1047 mii = device_get_softc(sc_if->sk_miibus);
1048
1049 mii_pollstat(mii);
1050 ifmr->ifm_active = mii->mii_media_active;
1051 ifmr->ifm_status = mii->mii_media_status;
1052
1053 return;
1054 }
1055
1056 static int
sk_ioctl(if_t ifp,u_long command,caddr_t data)1057 sk_ioctl(if_t ifp, u_long command, caddr_t data)
1058 {
1059 struct sk_if_softc *sc_if = if_getsoftc(ifp);
1060 struct ifreq *ifr = (struct ifreq *) data;
1061 int error, mask;
1062 struct mii_data *mii;
1063
1064 error = 0;
1065 switch(command) {
1066 case SIOCSIFMTU:
1067 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > SK_JUMBO_MTU)
1068 error = EINVAL;
1069 else if (if_getmtu(ifp) != ifr->ifr_mtu) {
1070 if (sc_if->sk_jumbo_disable != 0 &&
1071 ifr->ifr_mtu > SK_MAX_FRAMELEN)
1072 error = EINVAL;
1073 else {
1074 SK_IF_LOCK(sc_if);
1075 if_setmtu(ifp, ifr->ifr_mtu);
1076 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
1077 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1078 sk_init_locked(sc_if);
1079 }
1080 SK_IF_UNLOCK(sc_if);
1081 }
1082 }
1083 break;
1084 case SIOCSIFFLAGS:
1085 SK_IF_LOCK(sc_if);
1086 if (if_getflags(ifp) & IFF_UP) {
1087 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
1088 if ((if_getflags(ifp) ^ sc_if->sk_if_flags)
1089 & (IFF_PROMISC | IFF_ALLMULTI))
1090 sk_rxfilter(sc_if);
1091 } else
1092 sk_init_locked(sc_if);
1093 } else {
1094 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1095 sk_stop(sc_if);
1096 }
1097 sc_if->sk_if_flags = if_getflags(ifp);
1098 SK_IF_UNLOCK(sc_if);
1099 break;
1100 case SIOCADDMULTI:
1101 case SIOCDELMULTI:
1102 SK_IF_LOCK(sc_if);
1103 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1104 sk_rxfilter(sc_if);
1105 SK_IF_UNLOCK(sc_if);
1106 break;
1107 case SIOCGIFMEDIA:
1108 case SIOCSIFMEDIA:
1109 mii = device_get_softc(sc_if->sk_miibus);
1110 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1111 break;
1112 case SIOCSIFCAP:
1113 SK_IF_LOCK(sc_if);
1114 if (sc_if->sk_softc->sk_type == SK_GENESIS) {
1115 SK_IF_UNLOCK(sc_if);
1116 break;
1117 }
1118 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
1119 if ((mask & IFCAP_TXCSUM) != 0 &&
1120 (IFCAP_TXCSUM & if_getcapabilities(ifp)) != 0) {
1121 if_togglecapenable(ifp, IFCAP_TXCSUM);
1122 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
1123 if_sethwassistbits(ifp, SK_CSUM_FEATURES, 0);
1124 else
1125 if_sethwassistbits(ifp, 0, SK_CSUM_FEATURES);
1126 }
1127 if ((mask & IFCAP_RXCSUM) != 0 &&
1128 (IFCAP_RXCSUM & if_getcapabilities(ifp)) != 0)
1129 if_togglecapenable(ifp, IFCAP_RXCSUM);
1130 SK_IF_UNLOCK(sc_if);
1131 break;
1132 default:
1133 error = ether_ioctl(ifp, command, data);
1134 break;
1135 }
1136
1137 return (error);
1138 }
1139
1140 /*
1141 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
1142 * IDs against our list and return a device name if we find a match.
1143 */
1144 static int
skc_probe(device_t dev)1145 skc_probe(device_t dev)
1146 {
1147 const struct sk_type *t = sk_devs;
1148
1149 while(t->sk_name != NULL) {
1150 if ((pci_get_vendor(dev) == t->sk_vid) &&
1151 (pci_get_device(dev) == t->sk_did)) {
1152 /*
1153 * Only attach to rev. 2 of the Linksys EG1032 adapter.
1154 * Rev. 3 is supported by re(4).
1155 */
1156 if ((t->sk_vid == VENDORID_LINKSYS) &&
1157 (t->sk_did == DEVICEID_LINKSYS_EG1032) &&
1158 (pci_get_subdevice(dev) !=
1159 SUBDEVICEID_LINKSYS_EG1032_REV2)) {
1160 t++;
1161 continue;
1162 }
1163 device_set_desc(dev, t->sk_name);
1164 return (BUS_PROBE_DEFAULT);
1165 }
1166 t++;
1167 }
1168
1169 return(ENXIO);
1170 }
1171
1172 /*
1173 * Force the GEnesis into reset, then bring it out of reset.
1174 */
1175 static void
sk_reset(struct sk_softc * sc)1176 sk_reset(struct sk_softc *sc)
1177 {
1178
1179 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
1180 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
1181 if (SK_YUKON_FAMILY(sc->sk_type))
1182 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
1183
1184 DELAY(1000);
1185 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
1186 DELAY(2);
1187 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
1188 if (SK_YUKON_FAMILY(sc->sk_type))
1189 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
1190
1191 if (sc->sk_type == SK_GENESIS) {
1192 /* Configure packet arbiter */
1193 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
1194 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
1195 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
1196 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
1197 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
1198 }
1199
1200 /* Enable RAM interface */
1201 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
1202
1203 /*
1204 * Configure interrupt moderation. The moderation timer
1205 * defers interrupts specified in the interrupt moderation
1206 * timer mask based on the timeout specified in the interrupt
1207 * moderation timer init register. Each bit in the timer
1208 * register represents one tick, so to specify a timeout in
1209 * microseconds, we have to multiply by the correct number of
1210 * ticks-per-microsecond.
1211 */
1212 switch (sc->sk_type) {
1213 case SK_GENESIS:
1214 sc->sk_int_ticks = SK_IMTIMER_TICKS_GENESIS;
1215 break;
1216 default:
1217 sc->sk_int_ticks = SK_IMTIMER_TICKS_YUKON;
1218 break;
1219 }
1220 if (bootverbose)
1221 device_printf(sc->sk_dev, "interrupt moderation is %d us\n",
1222 sc->sk_int_mod);
1223 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod,
1224 sc->sk_int_ticks));
1225 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
1226 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
1227 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
1228
1229 return;
1230 }
1231
1232 static int
sk_probe(device_t dev)1233 sk_probe(device_t dev)
1234 {
1235 struct sk_softc *sc;
1236
1237 sc = device_get_softc(device_get_parent(dev));
1238
1239 /*
1240 * Not much to do here. We always know there will be
1241 * at least one XMAC present, and if there are two,
1242 * skc_attach() will create a second device instance
1243 * for us.
1244 */
1245 switch (sc->sk_type) {
1246 case SK_GENESIS:
1247 device_set_desc(dev, "XaQti Corp. XMAC II");
1248 break;
1249 case SK_YUKON:
1250 case SK_YUKON_LITE:
1251 case SK_YUKON_LP:
1252 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon");
1253 break;
1254 }
1255
1256 return (BUS_PROBE_DEFAULT);
1257 }
1258
1259 /*
1260 * Each XMAC chip is attached as a separate logical IP interface.
1261 * Single port cards will have only one logical interface of course.
1262 */
1263 static int
sk_attach(device_t dev)1264 sk_attach(device_t dev)
1265 {
1266 struct sk_softc *sc;
1267 struct sk_if_softc *sc_if;
1268 if_t ifp;
1269 u_int32_t r;
1270 int error, i, phy, port;
1271 u_char eaddr[6];
1272 u_char inv_mac[] = {0, 0, 0, 0, 0, 0};
1273
1274 if (dev == NULL)
1275 return(EINVAL);
1276
1277 error = 0;
1278 sc_if = device_get_softc(dev);
1279 sc = device_get_softc(device_get_parent(dev));
1280 port = *(int *)device_get_ivars(dev);
1281
1282 sc_if->sk_if_dev = dev;
1283 sc_if->sk_port = port;
1284 sc_if->sk_softc = sc;
1285 sc->sk_if[port] = sc_if;
1286 if (port == SK_PORT_A)
1287 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
1288 if (port == SK_PORT_B)
1289 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
1290
1291 callout_init_mtx(&sc_if->sk_tick_ch, &sc_if->sk_softc->sk_mtx, 0);
1292 callout_init_mtx(&sc_if->sk_watchdog_ch, &sc_if->sk_softc->sk_mtx, 0);
1293
1294 if (sk_dma_alloc(sc_if) != 0) {
1295 error = ENOMEM;
1296 goto fail;
1297 }
1298 sk_dma_jumbo_alloc(sc_if);
1299
1300 ifp = sc_if->sk_ifp = if_alloc(IFT_ETHER);
1301 if (ifp == NULL) {
1302 device_printf(sc_if->sk_if_dev, "can not if_alloc()\n");
1303 error = ENOSPC;
1304 goto fail;
1305 }
1306 if_setsoftc(ifp, sc_if);
1307 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1308 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
1309 /*
1310 * SK_GENESIS has a bug in checksum offload - From linux.
1311 */
1312 if (sc_if->sk_softc->sk_type != SK_GENESIS) {
1313 if_setcapabilities(ifp, IFCAP_TXCSUM | IFCAP_RXCSUM);
1314 if_sethwassist(ifp, 0);
1315 } else {
1316 if_setcapabilities(ifp, 0);
1317 if_sethwassist(ifp, 0);
1318 }
1319 if_setcapenable(ifp, if_getcapabilities(ifp));
1320 /*
1321 * Some revision of Yukon controller generates corrupted
1322 * frame when TX checksum offloading is enabled. The
1323 * frame has a valid checksum value so payload might be
1324 * modified during TX checksum calculation. Disable TX
1325 * checksum offloading but give users chance to enable it
1326 * when they know their controller works without problems
1327 * with TX checksum offloading.
1328 */
1329 if_setcapenablebit(ifp, 0, IFCAP_TXCSUM);
1330 if_setioctlfn(ifp, sk_ioctl);
1331 if_setstartfn(ifp, sk_start);
1332 if_setinitfn(ifp, sk_init);
1333 if_setsendqlen(ifp, SK_TX_RING_CNT - 1);
1334 if_setsendqready(ifp);
1335
1336 /*
1337 * Get station address for this interface. Note that
1338 * dual port cards actually come with three station
1339 * addresses: one for each port, plus an extra. The
1340 * extra one is used by the SysKonnect driver software
1341 * as a 'virtual' station address for when both ports
1342 * are operating in failover mode. Currently we don't
1343 * use this extra address.
1344 */
1345 SK_IF_LOCK(sc_if);
1346 for (i = 0; i < ETHER_ADDR_LEN; i++)
1347 eaddr[i] =
1348 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i);
1349
1350 /* Verify whether the station address is invalid or not. */
1351 if (bcmp(eaddr, inv_mac, sizeof(inv_mac)) == 0) {
1352 device_printf(sc_if->sk_if_dev,
1353 "Generating random ethernet address\n");
1354 r = arc4random();
1355 /*
1356 * Set OUI to convenient locally assigned address. 'b'
1357 * is 0x62, which has the locally assigned bit set, and
1358 * the broadcast/multicast bit clear.
1359 */
1360 eaddr[0] = 'b';
1361 eaddr[1] = 's';
1362 eaddr[2] = 'd';
1363 eaddr[3] = (r >> 16) & 0xff;
1364 eaddr[4] = (r >> 8) & 0xff;
1365 eaddr[5] = (r >> 0) & 0xff;
1366 }
1367 /*
1368 * Set up RAM buffer addresses. The NIC will have a certain
1369 * amount of SRAM on it, somewhere between 512K and 2MB. We
1370 * need to divide this up a) between the transmitter and
1371 * receiver and b) between the two XMACs, if this is a
1372 * dual port NIC. Our algotithm is to divide up the memory
1373 * evenly so that everyone gets a fair share.
1374 *
1375 * Just to be contrary, Yukon2 appears to have separate memory
1376 * for each MAC.
1377 */
1378 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
1379 u_int32_t chunk, val;
1380
1381 chunk = sc->sk_ramsize / 2;
1382 val = sc->sk_rboff / sizeof(u_int64_t);
1383 sc_if->sk_rx_ramstart = val;
1384 val += (chunk / sizeof(u_int64_t));
1385 sc_if->sk_rx_ramend = val - 1;
1386 sc_if->sk_tx_ramstart = val;
1387 val += (chunk / sizeof(u_int64_t));
1388 sc_if->sk_tx_ramend = val - 1;
1389 } else {
1390 u_int32_t chunk, val;
1391
1392 chunk = sc->sk_ramsize / 4;
1393 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
1394 sizeof(u_int64_t);
1395 sc_if->sk_rx_ramstart = val;
1396 val += (chunk / sizeof(u_int64_t));
1397 sc_if->sk_rx_ramend = val - 1;
1398 sc_if->sk_tx_ramstart = val;
1399 val += (chunk / sizeof(u_int64_t));
1400 sc_if->sk_tx_ramend = val - 1;
1401 }
1402
1403 /* Read and save PHY type and set PHY address */
1404 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
1405 if (!SK_YUKON_FAMILY(sc->sk_type)) {
1406 switch(sc_if->sk_phytype) {
1407 case SK_PHYTYPE_XMAC:
1408 sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
1409 break;
1410 case SK_PHYTYPE_BCOM:
1411 sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
1412 break;
1413 default:
1414 device_printf(sc->sk_dev, "unsupported PHY type: %d\n",
1415 sc_if->sk_phytype);
1416 error = ENODEV;
1417 SK_IF_UNLOCK(sc_if);
1418 goto fail;
1419 }
1420 } else {
1421 if (sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER &&
1422 sc->sk_pmd != 'S') {
1423 /* not initialized, punt */
1424 sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER;
1425 sc->sk_coppertype = 1;
1426 }
1427
1428 sc_if->sk_phyaddr = SK_PHYADDR_MARV;
1429
1430 if (!(sc->sk_coppertype))
1431 sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER;
1432 }
1433
1434 /*
1435 * Call MI attach routine. Can't hold locks when calling into ether_*.
1436 */
1437 SK_IF_UNLOCK(sc_if);
1438 ether_ifattach(ifp, eaddr);
1439 SK_IF_LOCK(sc_if);
1440
1441 /*
1442 * The hardware should be ready for VLAN_MTU by default:
1443 * XMAC II has 0x8100 in VLAN Tag Level 1 register initially;
1444 * YU_SMR_MFL_VLAN is set by this driver in Yukon.
1445 *
1446 */
1447 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0);
1448 if_setcapenablebit(ifp, IFCAP_VLAN_MTU, 0);
1449 /*
1450 * Tell the upper layer(s) we support long frames.
1451 * Must appear after the call to ether_ifattach() because
1452 * ether_ifattach() sets ifi_hdrlen to the default value.
1453 */
1454 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
1455
1456 /*
1457 * Do miibus setup.
1458 */
1459 phy = MII_PHY_ANY;
1460 switch (sc->sk_type) {
1461 case SK_GENESIS:
1462 sk_init_xmac(sc_if);
1463 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
1464 phy = 0;
1465 break;
1466 case SK_YUKON:
1467 case SK_YUKON_LITE:
1468 case SK_YUKON_LP:
1469 sk_init_yukon(sc_if);
1470 phy = 0;
1471 break;
1472 }
1473
1474 SK_IF_UNLOCK(sc_if);
1475 error = mii_attach(dev, &sc_if->sk_miibus, ifp, sk_ifmedia_upd,
1476 sk_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
1477 if (error != 0) {
1478 device_printf(sc_if->sk_if_dev, "attaching PHYs failed\n");
1479 ether_ifdetach(ifp);
1480 goto fail;
1481 }
1482
1483 fail:
1484 if (error) {
1485 /* Access should be ok even though lock has been dropped */
1486 sc->sk_if[port] = NULL;
1487 sk_detach(dev);
1488 }
1489
1490 return(error);
1491 }
1492
1493 /*
1494 * Attach the interface. Allocate softc structures, do ifmedia
1495 * setup and ethernet/BPF attach.
1496 */
1497 static int
skc_attach(device_t dev)1498 skc_attach(device_t dev)
1499 {
1500 struct sk_softc *sc;
1501 int error = 0, *port;
1502 uint8_t skrs;
1503 const char *pname = NULL;
1504 char *revstr;
1505
1506 sc = device_get_softc(dev);
1507 sc->sk_dev = dev;
1508
1509 mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1510 MTX_DEF);
1511 mtx_init(&sc->sk_mii_mtx, "sk_mii_mutex", NULL, MTX_DEF);
1512 /*
1513 * Map control/status registers.
1514 */
1515 pci_enable_busmaster(dev);
1516
1517 /* Allocate resources */
1518 #ifdef SK_USEIOSPACE
1519 sc->sk_res_spec = sk_res_spec_io;
1520 #else
1521 sc->sk_res_spec = sk_res_spec_mem;
1522 #endif
1523 error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res);
1524 if (error) {
1525 if (sc->sk_res_spec == sk_res_spec_mem)
1526 sc->sk_res_spec = sk_res_spec_io;
1527 else
1528 sc->sk_res_spec = sk_res_spec_mem;
1529 error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res);
1530 if (error) {
1531 device_printf(dev, "couldn't allocate %s resources\n",
1532 sc->sk_res_spec == sk_res_spec_mem ? "memory" :
1533 "I/O");
1534 goto fail;
1535 }
1536 }
1537
1538 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER);
1539 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4) & 0xf;
1540
1541 /* Bail out if chip is not recognized. */
1542 if (sc->sk_type != SK_GENESIS && !SK_YUKON_FAMILY(sc->sk_type)) {
1543 device_printf(dev, "unknown device: chipver=%02x, rev=%x\n",
1544 sc->sk_type, sc->sk_rev);
1545 error = ENXIO;
1546 goto fail;
1547 }
1548
1549 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
1550 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1551 OID_AUTO, "int_mod",
1552 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
1553 &sc->sk_int_mod, 0, sysctl_hw_sk_int_mod, "I",
1554 "SK interrupt moderation");
1555
1556 /* Pull in device tunables. */
1557 sc->sk_int_mod = SK_IM_DEFAULT;
1558 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
1559 "int_mod", &sc->sk_int_mod);
1560 if (error == 0) {
1561 if (sc->sk_int_mod < SK_IM_MIN ||
1562 sc->sk_int_mod > SK_IM_MAX) {
1563 device_printf(dev, "int_mod value out of range; "
1564 "using default: %d\n", SK_IM_DEFAULT);
1565 sc->sk_int_mod = SK_IM_DEFAULT;
1566 }
1567 }
1568
1569 /* Reset the adapter. */
1570 sk_reset(sc);
1571
1572 skrs = sk_win_read_1(sc, SK_EPROM0);
1573 if (sc->sk_type == SK_GENESIS) {
1574 /* Read and save RAM size and RAMbuffer offset */
1575 switch(skrs) {
1576 case SK_RAMSIZE_512K_64:
1577 sc->sk_ramsize = 0x80000;
1578 sc->sk_rboff = SK_RBOFF_0;
1579 break;
1580 case SK_RAMSIZE_1024K_64:
1581 sc->sk_ramsize = 0x100000;
1582 sc->sk_rboff = SK_RBOFF_80000;
1583 break;
1584 case SK_RAMSIZE_1024K_128:
1585 sc->sk_ramsize = 0x100000;
1586 sc->sk_rboff = SK_RBOFF_0;
1587 break;
1588 case SK_RAMSIZE_2048K_128:
1589 sc->sk_ramsize = 0x200000;
1590 sc->sk_rboff = SK_RBOFF_0;
1591 break;
1592 default:
1593 device_printf(dev, "unknown ram size: %d\n", skrs);
1594 error = ENXIO;
1595 goto fail;
1596 }
1597 } else { /* SK_YUKON_FAMILY */
1598 if (skrs == 0x00)
1599 sc->sk_ramsize = 0x20000;
1600 else
1601 sc->sk_ramsize = skrs * (1<<12);
1602 sc->sk_rboff = SK_RBOFF_0;
1603 }
1604
1605 /* Read and save physical media type */
1606 sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE);
1607
1608 if (sc->sk_pmd == 'T' || sc->sk_pmd == '1')
1609 sc->sk_coppertype = 1;
1610 else
1611 sc->sk_coppertype = 0;
1612
1613 /* Determine whether to name it with VPD PN or just make it up.
1614 * Marvell Yukon VPD PN seems to freqently be bogus. */
1615 switch (pci_get_device(dev)) {
1616 case DEVICEID_SK_V1:
1617 case DEVICEID_BELKIN_5005:
1618 case DEVICEID_3COM_3C940:
1619 case DEVICEID_LINKSYS_EG1032:
1620 case DEVICEID_DLINK_DGE530T_A1:
1621 case DEVICEID_DLINK_DGE530T_B1:
1622 /* Stay with VPD PN. */
1623 (void) pci_get_vpd_ident(dev, &pname);
1624 break;
1625 case DEVICEID_SK_V2:
1626 /* YUKON VPD PN might bear no resemblance to reality. */
1627 switch (sc->sk_type) {
1628 case SK_GENESIS:
1629 /* Stay with VPD PN. */
1630 (void) pci_get_vpd_ident(dev, &pname);
1631 break;
1632 case SK_YUKON:
1633 pname = "Marvell Yukon Gigabit Ethernet";
1634 break;
1635 case SK_YUKON_LITE:
1636 pname = "Marvell Yukon Lite Gigabit Ethernet";
1637 break;
1638 case SK_YUKON_LP:
1639 pname = "Marvell Yukon LP Gigabit Ethernet";
1640 break;
1641 default:
1642 pname = "Marvell Yukon (Unknown) Gigabit Ethernet";
1643 break;
1644 }
1645
1646 /* Yukon Lite Rev. A0 needs special test. */
1647 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) {
1648 u_int32_t far;
1649 u_int8_t testbyte;
1650
1651 /* Save flash address register before testing. */
1652 far = sk_win_read_4(sc, SK_EP_ADDR);
1653
1654 sk_win_write_1(sc, SK_EP_ADDR+0x03, 0xff);
1655 testbyte = sk_win_read_1(sc, SK_EP_ADDR+0x03);
1656
1657 if (testbyte != 0x00) {
1658 /* Yukon Lite Rev. A0 detected. */
1659 sc->sk_type = SK_YUKON_LITE;
1660 sc->sk_rev = SK_YUKON_LITE_REV_A0;
1661 /* Restore flash address register. */
1662 sk_win_write_4(sc, SK_EP_ADDR, far);
1663 }
1664 }
1665 break;
1666 default:
1667 device_printf(dev, "unknown device: vendor=%04x, device=%04x, "
1668 "chipver=%02x, rev=%x\n",
1669 pci_get_vendor(dev), pci_get_device(dev),
1670 sc->sk_type, sc->sk_rev);
1671 error = ENXIO;
1672 goto fail;
1673 }
1674
1675 if (sc->sk_type == SK_YUKON_LITE) {
1676 switch (sc->sk_rev) {
1677 case SK_YUKON_LITE_REV_A0:
1678 revstr = "A0";
1679 break;
1680 case SK_YUKON_LITE_REV_A1:
1681 revstr = "A1";
1682 break;
1683 case SK_YUKON_LITE_REV_A3:
1684 revstr = "A3";
1685 break;
1686 default:
1687 revstr = "";
1688 break;
1689 }
1690 } else {
1691 revstr = "";
1692 }
1693
1694 /* Announce the product name and more VPD data if there. */
1695 if (pname != NULL)
1696 device_printf(dev, "%s rev. %s(0x%x)\n",
1697 pname, revstr, sc->sk_rev);
1698
1699 if (bootverbose) {
1700 device_printf(dev, "chip ver = 0x%02x\n", sc->sk_type);
1701 device_printf(dev, "chip rev = 0x%02x\n", sc->sk_rev);
1702 device_printf(dev, "SK_EPROM0 = 0x%02x\n", skrs);
1703 device_printf(dev, "SRAM size = 0x%06x\n", sc->sk_ramsize);
1704 }
1705
1706 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1);
1707 if (sc->sk_devs[SK_PORT_A] == NULL) {
1708 device_printf(dev, "failed to add child for PORT_A\n");
1709 error = ENXIO;
1710 goto fail;
1711 }
1712 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1713 if (port == NULL) {
1714 device_printf(dev, "failed to allocate memory for "
1715 "ivars of PORT_A\n");
1716 error = ENXIO;
1717 goto fail;
1718 }
1719 *port = SK_PORT_A;
1720 device_set_ivars(sc->sk_devs[SK_PORT_A], port);
1721
1722 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) {
1723 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1);
1724 if (sc->sk_devs[SK_PORT_B] == NULL) {
1725 device_printf(dev, "failed to add child for PORT_B\n");
1726 error = ENXIO;
1727 goto fail;
1728 }
1729 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1730 if (port == NULL) {
1731 device_printf(dev, "failed to allocate memory for "
1732 "ivars of PORT_B\n");
1733 error = ENXIO;
1734 goto fail;
1735 }
1736 *port = SK_PORT_B;
1737 device_set_ivars(sc->sk_devs[SK_PORT_B], port);
1738 }
1739
1740 /* Turn on the 'driver is loaded' LED. */
1741 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1742
1743 error = bus_generic_attach(dev);
1744 if (error) {
1745 device_printf(dev, "failed to attach port(s)\n");
1746 goto fail;
1747 }
1748
1749 /* Hook interrupt last to avoid having to lock softc */
1750 error = bus_setup_intr(dev, sc->sk_res[1], INTR_TYPE_NET|INTR_MPSAFE,
1751 NULL, sk_intr, sc, &sc->sk_intrhand);
1752
1753 if (error) {
1754 device_printf(dev, "couldn't set up irq\n");
1755 goto fail;
1756 }
1757
1758 fail:
1759 if (error)
1760 skc_detach(dev);
1761
1762 return(error);
1763 }
1764
1765 /*
1766 * Shutdown hardware and free up resources. This can be called any
1767 * time after the mutex has been initialized. It is called in both
1768 * the error case in attach and the normal detach case so it needs
1769 * to be careful about only freeing resources that have actually been
1770 * allocated.
1771 */
1772 static int
sk_detach(device_t dev)1773 sk_detach(device_t dev)
1774 {
1775 struct sk_if_softc *sc_if;
1776 if_t ifp;
1777
1778 sc_if = device_get_softc(dev);
1779 KASSERT(mtx_initialized(&sc_if->sk_softc->sk_mtx),
1780 ("sk mutex not initialized in sk_detach"));
1781 SK_IF_LOCK(sc_if);
1782
1783 ifp = sc_if->sk_ifp;
1784 /* These should only be active if attach_xmac succeeded */
1785 if (device_is_attached(dev)) {
1786 sk_stop(sc_if);
1787 /* Can't hold locks while calling detach */
1788 SK_IF_UNLOCK(sc_if);
1789 callout_drain(&sc_if->sk_tick_ch);
1790 callout_drain(&sc_if->sk_watchdog_ch);
1791 ether_ifdetach(ifp);
1792 SK_IF_LOCK(sc_if);
1793 }
1794 /*
1795 * We're generally called from skc_detach() which is using
1796 * device_delete_child() to get to here. It's already trashed
1797 * miibus for us, so don't do it here or we'll panic.
1798 */
1799 /*
1800 if (sc_if->sk_miibus != NULL)
1801 device_delete_child(dev, sc_if->sk_miibus);
1802 */
1803 bus_generic_detach(dev);
1804 sk_dma_jumbo_free(sc_if);
1805 sk_dma_free(sc_if);
1806 SK_IF_UNLOCK(sc_if);
1807 if (ifp)
1808 if_free(ifp);
1809
1810 return(0);
1811 }
1812
1813 static int
skc_detach(device_t dev)1814 skc_detach(device_t dev)
1815 {
1816 struct sk_softc *sc;
1817
1818 sc = device_get_softc(dev);
1819 KASSERT(mtx_initialized(&sc->sk_mtx), ("sk mutex not initialized"));
1820
1821 if (device_is_alive(dev)) {
1822 if (sc->sk_devs[SK_PORT_A] != NULL) {
1823 free(device_get_ivars(sc->sk_devs[SK_PORT_A]), M_DEVBUF);
1824 device_delete_child(dev, sc->sk_devs[SK_PORT_A]);
1825 }
1826 if (sc->sk_devs[SK_PORT_B] != NULL) {
1827 free(device_get_ivars(sc->sk_devs[SK_PORT_B]), M_DEVBUF);
1828 device_delete_child(dev, sc->sk_devs[SK_PORT_B]);
1829 }
1830 bus_generic_detach(dev);
1831 }
1832
1833 if (sc->sk_intrhand)
1834 bus_teardown_intr(dev, sc->sk_res[1], sc->sk_intrhand);
1835 bus_release_resources(dev, sc->sk_res_spec, sc->sk_res);
1836
1837 mtx_destroy(&sc->sk_mii_mtx);
1838 mtx_destroy(&sc->sk_mtx);
1839
1840 return(0);
1841 }
1842
1843 static bus_dma_tag_t
skc_get_dma_tag(device_t bus,device_t child __unused)1844 skc_get_dma_tag(device_t bus, device_t child __unused)
1845 {
1846
1847 return (bus_get_dma_tag(bus));
1848 }
1849
1850 struct sk_dmamap_arg {
1851 bus_addr_t sk_busaddr;
1852 };
1853
1854 static void
sk_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nseg,int error)1855 sk_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1856 {
1857 struct sk_dmamap_arg *ctx;
1858
1859 if (error != 0)
1860 return;
1861
1862 ctx = arg;
1863 ctx->sk_busaddr = segs[0].ds_addr;
1864 }
1865
1866 /*
1867 * Allocate jumbo buffer storage. The SysKonnect adapters support
1868 * "jumbograms" (9K frames), although SysKonnect doesn't currently
1869 * use them in their drivers. In order for us to use them, we need
1870 * large 9K receive buffers, however standard mbuf clusters are only
1871 * 2048 bytes in size. Consequently, we need to allocate and manage
1872 * our own jumbo buffer pool. Fortunately, this does not require an
1873 * excessive amount of additional code.
1874 */
1875 static int
sk_dma_alloc(struct sk_if_softc * sc_if)1876 sk_dma_alloc(struct sk_if_softc *sc_if)
1877 {
1878 struct sk_dmamap_arg ctx;
1879 struct sk_txdesc *txd;
1880 struct sk_rxdesc *rxd;
1881 int error, i;
1882
1883 /* create parent tag */
1884 /*
1885 * XXX
1886 * This driver should use BUS_SPACE_MAXADDR for lowaddr argument
1887 * in bus_dma_tag_create(9) as the NIC would support DAC mode.
1888 * However bz@ reported that it does not work on amd64 with > 4GB
1889 * RAM. Until we have more clues of the breakage, disable DAC mode
1890 * by limiting DMA address to be in 32bit address space.
1891 */
1892 error = bus_dma_tag_create(
1893 bus_get_dma_tag(sc_if->sk_if_dev),/* parent */
1894 1, 0, /* algnmnt, boundary */
1895 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1896 BUS_SPACE_MAXADDR, /* highaddr */
1897 NULL, NULL, /* filter, filterarg */
1898 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1899 0, /* nsegments */
1900 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1901 0, /* flags */
1902 NULL, NULL, /* lockfunc, lockarg */
1903 &sc_if->sk_cdata.sk_parent_tag);
1904 if (error != 0) {
1905 device_printf(sc_if->sk_if_dev,
1906 "failed to create parent DMA tag\n");
1907 goto fail;
1908 }
1909
1910 /* create tag for Tx ring */
1911 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1912 SK_RING_ALIGN, 0, /* algnmnt, boundary */
1913 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1914 BUS_SPACE_MAXADDR, /* highaddr */
1915 NULL, NULL, /* filter, filterarg */
1916 SK_TX_RING_SZ, /* maxsize */
1917 1, /* nsegments */
1918 SK_TX_RING_SZ, /* maxsegsize */
1919 0, /* flags */
1920 NULL, NULL, /* lockfunc, lockarg */
1921 &sc_if->sk_cdata.sk_tx_ring_tag);
1922 if (error != 0) {
1923 device_printf(sc_if->sk_if_dev,
1924 "failed to allocate Tx ring DMA tag\n");
1925 goto fail;
1926 }
1927
1928 /* create tag for Rx ring */
1929 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1930 SK_RING_ALIGN, 0, /* algnmnt, boundary */
1931 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1932 BUS_SPACE_MAXADDR, /* highaddr */
1933 NULL, NULL, /* filter, filterarg */
1934 SK_RX_RING_SZ, /* maxsize */
1935 1, /* nsegments */
1936 SK_RX_RING_SZ, /* maxsegsize */
1937 0, /* flags */
1938 NULL, NULL, /* lockfunc, lockarg */
1939 &sc_if->sk_cdata.sk_rx_ring_tag);
1940 if (error != 0) {
1941 device_printf(sc_if->sk_if_dev,
1942 "failed to allocate Rx ring DMA tag\n");
1943 goto fail;
1944 }
1945
1946 /* create tag for Tx buffers */
1947 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1948 1, 0, /* algnmnt, boundary */
1949 BUS_SPACE_MAXADDR, /* lowaddr */
1950 BUS_SPACE_MAXADDR, /* highaddr */
1951 NULL, NULL, /* filter, filterarg */
1952 MCLBYTES * SK_MAXTXSEGS, /* maxsize */
1953 SK_MAXTXSEGS, /* nsegments */
1954 MCLBYTES, /* maxsegsize */
1955 0, /* flags */
1956 NULL, NULL, /* lockfunc, lockarg */
1957 &sc_if->sk_cdata.sk_tx_tag);
1958 if (error != 0) {
1959 device_printf(sc_if->sk_if_dev,
1960 "failed to allocate Tx DMA tag\n");
1961 goto fail;
1962 }
1963
1964 /* create tag for Rx buffers */
1965 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1966 1, 0, /* algnmnt, boundary */
1967 BUS_SPACE_MAXADDR, /* lowaddr */
1968 BUS_SPACE_MAXADDR, /* highaddr */
1969 NULL, NULL, /* filter, filterarg */
1970 MCLBYTES, /* maxsize */
1971 1, /* nsegments */
1972 MCLBYTES, /* maxsegsize */
1973 0, /* flags */
1974 NULL, NULL, /* lockfunc, lockarg */
1975 &sc_if->sk_cdata.sk_rx_tag);
1976 if (error != 0) {
1977 device_printf(sc_if->sk_if_dev,
1978 "failed to allocate Rx DMA tag\n");
1979 goto fail;
1980 }
1981
1982 /* allocate DMA'able memory and load the DMA map for Tx ring */
1983 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_tx_ring_tag,
1984 (void **)&sc_if->sk_rdata.sk_tx_ring, BUS_DMA_NOWAIT |
1985 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->sk_cdata.sk_tx_ring_map);
1986 if (error != 0) {
1987 device_printf(sc_if->sk_if_dev,
1988 "failed to allocate DMA'able memory for Tx ring\n");
1989 goto fail;
1990 }
1991
1992 ctx.sk_busaddr = 0;
1993 error = bus_dmamap_load(sc_if->sk_cdata.sk_tx_ring_tag,
1994 sc_if->sk_cdata.sk_tx_ring_map, sc_if->sk_rdata.sk_tx_ring,
1995 SK_TX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
1996 if (error != 0) {
1997 device_printf(sc_if->sk_if_dev,
1998 "failed to load DMA'able memory for Tx ring\n");
1999 goto fail;
2000 }
2001 sc_if->sk_rdata.sk_tx_ring_paddr = ctx.sk_busaddr;
2002
2003 /* allocate DMA'able memory and load the DMA map for Rx ring */
2004 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_rx_ring_tag,
2005 (void **)&sc_if->sk_rdata.sk_rx_ring, BUS_DMA_NOWAIT |
2006 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->sk_cdata.sk_rx_ring_map);
2007 if (error != 0) {
2008 device_printf(sc_if->sk_if_dev,
2009 "failed to allocate DMA'able memory for Rx ring\n");
2010 goto fail;
2011 }
2012
2013 ctx.sk_busaddr = 0;
2014 error = bus_dmamap_load(sc_if->sk_cdata.sk_rx_ring_tag,
2015 sc_if->sk_cdata.sk_rx_ring_map, sc_if->sk_rdata.sk_rx_ring,
2016 SK_RX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2017 if (error != 0) {
2018 device_printf(sc_if->sk_if_dev,
2019 "failed to load DMA'able memory for Rx ring\n");
2020 goto fail;
2021 }
2022 sc_if->sk_rdata.sk_rx_ring_paddr = ctx.sk_busaddr;
2023
2024 /* create DMA maps for Tx buffers */
2025 for (i = 0; i < SK_TX_RING_CNT; i++) {
2026 txd = &sc_if->sk_cdata.sk_txdesc[i];
2027 txd->tx_m = NULL;
2028 txd->tx_dmamap = NULL;
2029 error = bus_dmamap_create(sc_if->sk_cdata.sk_tx_tag, 0,
2030 &txd->tx_dmamap);
2031 if (error != 0) {
2032 device_printf(sc_if->sk_if_dev,
2033 "failed to create Tx dmamap\n");
2034 goto fail;
2035 }
2036 }
2037
2038 /* create DMA maps for Rx buffers */
2039 if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0,
2040 &sc_if->sk_cdata.sk_rx_sparemap)) != 0) {
2041 device_printf(sc_if->sk_if_dev,
2042 "failed to create spare Rx dmamap\n");
2043 goto fail;
2044 }
2045 for (i = 0; i < SK_RX_RING_CNT; i++) {
2046 rxd = &sc_if->sk_cdata.sk_rxdesc[i];
2047 rxd->rx_m = NULL;
2048 rxd->rx_dmamap = NULL;
2049 error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0,
2050 &rxd->rx_dmamap);
2051 if (error != 0) {
2052 device_printf(sc_if->sk_if_dev,
2053 "failed to create Rx dmamap\n");
2054 goto fail;
2055 }
2056 }
2057
2058 fail:
2059 return (error);
2060 }
2061
2062 static int
sk_dma_jumbo_alloc(struct sk_if_softc * sc_if)2063 sk_dma_jumbo_alloc(struct sk_if_softc *sc_if)
2064 {
2065 struct sk_dmamap_arg ctx;
2066 struct sk_rxdesc *jrxd;
2067 int error, i;
2068
2069 if (jumbo_disable != 0) {
2070 device_printf(sc_if->sk_if_dev, "disabling jumbo frame support\n");
2071 sc_if->sk_jumbo_disable = 1;
2072 return (0);
2073 }
2074 /* create tag for jumbo Rx ring */
2075 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2076 SK_RING_ALIGN, 0, /* algnmnt, boundary */
2077 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
2078 BUS_SPACE_MAXADDR, /* highaddr */
2079 NULL, NULL, /* filter, filterarg */
2080 SK_JUMBO_RX_RING_SZ, /* maxsize */
2081 1, /* nsegments */
2082 SK_JUMBO_RX_RING_SZ, /* maxsegsize */
2083 0, /* flags */
2084 NULL, NULL, /* lockfunc, lockarg */
2085 &sc_if->sk_cdata.sk_jumbo_rx_ring_tag);
2086 if (error != 0) {
2087 device_printf(sc_if->sk_if_dev,
2088 "failed to allocate jumbo Rx ring DMA tag\n");
2089 goto jumbo_fail;
2090 }
2091
2092 /* create tag for jumbo Rx buffers */
2093 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2094 1, 0, /* algnmnt, boundary */
2095 BUS_SPACE_MAXADDR, /* lowaddr */
2096 BUS_SPACE_MAXADDR, /* highaddr */
2097 NULL, NULL, /* filter, filterarg */
2098 MJUM9BYTES, /* maxsize */
2099 1, /* nsegments */
2100 MJUM9BYTES, /* maxsegsize */
2101 0, /* flags */
2102 NULL, NULL, /* lockfunc, lockarg */
2103 &sc_if->sk_cdata.sk_jumbo_rx_tag);
2104 if (error != 0) {
2105 device_printf(sc_if->sk_if_dev,
2106 "failed to allocate jumbo Rx DMA tag\n");
2107 goto jumbo_fail;
2108 }
2109
2110 /* allocate DMA'able memory and load the DMA map for jumbo Rx ring */
2111 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2112 (void **)&sc_if->sk_rdata.sk_jumbo_rx_ring, BUS_DMA_NOWAIT |
2113 BUS_DMA_COHERENT | BUS_DMA_ZERO,
2114 &sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2115 if (error != 0) {
2116 device_printf(sc_if->sk_if_dev,
2117 "failed to allocate DMA'able memory for jumbo Rx ring\n");
2118 goto jumbo_fail;
2119 }
2120
2121 ctx.sk_busaddr = 0;
2122 error = bus_dmamap_load(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2123 sc_if->sk_cdata.sk_jumbo_rx_ring_map,
2124 sc_if->sk_rdata.sk_jumbo_rx_ring, SK_JUMBO_RX_RING_SZ, sk_dmamap_cb,
2125 &ctx, BUS_DMA_NOWAIT);
2126 if (error != 0) {
2127 device_printf(sc_if->sk_if_dev,
2128 "failed to load DMA'able memory for jumbo Rx ring\n");
2129 goto jumbo_fail;
2130 }
2131 sc_if->sk_rdata.sk_jumbo_rx_ring_paddr = ctx.sk_busaddr;
2132
2133 /* create DMA maps for jumbo Rx buffers */
2134 if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0,
2135 &sc_if->sk_cdata.sk_jumbo_rx_sparemap)) != 0) {
2136 device_printf(sc_if->sk_if_dev,
2137 "failed to create spare jumbo Rx dmamap\n");
2138 goto jumbo_fail;
2139 }
2140 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
2141 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
2142 jrxd->rx_m = NULL;
2143 jrxd->rx_dmamap = NULL;
2144 error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0,
2145 &jrxd->rx_dmamap);
2146 if (error != 0) {
2147 device_printf(sc_if->sk_if_dev,
2148 "failed to create jumbo Rx dmamap\n");
2149 goto jumbo_fail;
2150 }
2151 }
2152
2153 return (0);
2154
2155 jumbo_fail:
2156 sk_dma_jumbo_free(sc_if);
2157 device_printf(sc_if->sk_if_dev, "disabling jumbo frame support due to "
2158 "resource shortage\n");
2159 sc_if->sk_jumbo_disable = 1;
2160 return (0);
2161 }
2162
2163 static void
sk_dma_free(struct sk_if_softc * sc_if)2164 sk_dma_free(struct sk_if_softc *sc_if)
2165 {
2166 struct sk_txdesc *txd;
2167 struct sk_rxdesc *rxd;
2168 int i;
2169
2170 /* Tx ring */
2171 if (sc_if->sk_cdata.sk_tx_ring_tag) {
2172 if (sc_if->sk_rdata.sk_tx_ring_paddr)
2173 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_ring_tag,
2174 sc_if->sk_cdata.sk_tx_ring_map);
2175 if (sc_if->sk_rdata.sk_tx_ring)
2176 bus_dmamem_free(sc_if->sk_cdata.sk_tx_ring_tag,
2177 sc_if->sk_rdata.sk_tx_ring,
2178 sc_if->sk_cdata.sk_tx_ring_map);
2179 sc_if->sk_rdata.sk_tx_ring = NULL;
2180 sc_if->sk_rdata.sk_tx_ring_paddr = 0;
2181 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_ring_tag);
2182 sc_if->sk_cdata.sk_tx_ring_tag = NULL;
2183 }
2184 /* Rx ring */
2185 if (sc_if->sk_cdata.sk_rx_ring_tag) {
2186 if (sc_if->sk_rdata.sk_rx_ring_paddr)
2187 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_ring_tag,
2188 sc_if->sk_cdata.sk_rx_ring_map);
2189 if (sc_if->sk_rdata.sk_rx_ring)
2190 bus_dmamem_free(sc_if->sk_cdata.sk_rx_ring_tag,
2191 sc_if->sk_rdata.sk_rx_ring,
2192 sc_if->sk_cdata.sk_rx_ring_map);
2193 sc_if->sk_rdata.sk_rx_ring = NULL;
2194 sc_if->sk_rdata.sk_rx_ring_paddr = 0;
2195 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_ring_tag);
2196 sc_if->sk_cdata.sk_rx_ring_tag = NULL;
2197 }
2198 /* Tx buffers */
2199 if (sc_if->sk_cdata.sk_tx_tag) {
2200 for (i = 0; i < SK_TX_RING_CNT; i++) {
2201 txd = &sc_if->sk_cdata.sk_txdesc[i];
2202 if (txd->tx_dmamap) {
2203 bus_dmamap_destroy(sc_if->sk_cdata.sk_tx_tag,
2204 txd->tx_dmamap);
2205 txd->tx_dmamap = NULL;
2206 }
2207 }
2208 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_tag);
2209 sc_if->sk_cdata.sk_tx_tag = NULL;
2210 }
2211 /* Rx buffers */
2212 if (sc_if->sk_cdata.sk_rx_tag) {
2213 for (i = 0; i < SK_RX_RING_CNT; i++) {
2214 rxd = &sc_if->sk_cdata.sk_rxdesc[i];
2215 if (rxd->rx_dmamap) {
2216 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag,
2217 rxd->rx_dmamap);
2218 rxd->rx_dmamap = NULL;
2219 }
2220 }
2221 if (sc_if->sk_cdata.sk_rx_sparemap) {
2222 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag,
2223 sc_if->sk_cdata.sk_rx_sparemap);
2224 sc_if->sk_cdata.sk_rx_sparemap = NULL;
2225 }
2226 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_tag);
2227 sc_if->sk_cdata.sk_rx_tag = NULL;
2228 }
2229
2230 if (sc_if->sk_cdata.sk_parent_tag) {
2231 bus_dma_tag_destroy(sc_if->sk_cdata.sk_parent_tag);
2232 sc_if->sk_cdata.sk_parent_tag = NULL;
2233 }
2234 }
2235
2236 static void
sk_dma_jumbo_free(struct sk_if_softc * sc_if)2237 sk_dma_jumbo_free(struct sk_if_softc *sc_if)
2238 {
2239 struct sk_rxdesc *jrxd;
2240 int i;
2241
2242 /* jumbo Rx ring */
2243 if (sc_if->sk_cdata.sk_jumbo_rx_ring_tag) {
2244 if (sc_if->sk_rdata.sk_jumbo_rx_ring_paddr)
2245 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2246 sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2247 if (sc_if->sk_rdata.sk_jumbo_rx_ring)
2248 bus_dmamem_free(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2249 sc_if->sk_rdata.sk_jumbo_rx_ring,
2250 sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2251 sc_if->sk_rdata.sk_jumbo_rx_ring = NULL;
2252 sc_if->sk_rdata.sk_jumbo_rx_ring_paddr = 0;
2253 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_ring_tag);
2254 sc_if->sk_cdata.sk_jumbo_rx_ring_tag = NULL;
2255 }
2256
2257 /* jumbo Rx buffers */
2258 if (sc_if->sk_cdata.sk_jumbo_rx_tag) {
2259 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
2260 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
2261 if (jrxd->rx_dmamap) {
2262 bus_dmamap_destroy(
2263 sc_if->sk_cdata.sk_jumbo_rx_tag,
2264 jrxd->rx_dmamap);
2265 jrxd->rx_dmamap = NULL;
2266 }
2267 }
2268 if (sc_if->sk_cdata.sk_jumbo_rx_sparemap) {
2269 bus_dmamap_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag,
2270 sc_if->sk_cdata.sk_jumbo_rx_sparemap);
2271 sc_if->sk_cdata.sk_jumbo_rx_sparemap = NULL;
2272 }
2273 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag);
2274 sc_if->sk_cdata.sk_jumbo_rx_tag = NULL;
2275 }
2276 }
2277
2278 static void
sk_txcksum(if_t ifp,struct mbuf * m,struct sk_tx_desc * f)2279 sk_txcksum(if_t ifp, struct mbuf *m, struct sk_tx_desc *f)
2280 {
2281 struct ip *ip;
2282 u_int16_t offset;
2283 u_int8_t *p;
2284
2285 offset = sizeof(struct ip) + ETHER_HDR_LEN;
2286 for(; m && m->m_len == 0; m = m->m_next)
2287 ;
2288 if (m == NULL || m->m_len < ETHER_HDR_LEN) {
2289 if_printf(ifp, "%s: m_len < ETHER_HDR_LEN\n", __func__);
2290 /* checksum may be corrupted */
2291 goto sendit;
2292 }
2293 if (m->m_len < ETHER_HDR_LEN + sizeof(u_int32_t)) {
2294 if (m->m_len != ETHER_HDR_LEN) {
2295 if_printf(ifp, "%s: m_len != ETHER_HDR_LEN\n",
2296 __func__);
2297 /* checksum may be corrupted */
2298 goto sendit;
2299 }
2300 for(m = m->m_next; m && m->m_len == 0; m = m->m_next)
2301 ;
2302 if (m == NULL) {
2303 offset = sizeof(struct ip) + ETHER_HDR_LEN;
2304 /* checksum may be corrupted */
2305 goto sendit;
2306 }
2307 ip = mtod(m, struct ip *);
2308 } else {
2309 p = mtod(m, u_int8_t *);
2310 p += ETHER_HDR_LEN;
2311 ip = (struct ip *)p;
2312 }
2313 offset = (ip->ip_hl << 2) + ETHER_HDR_LEN;
2314
2315 sendit:
2316 f->sk_csum_startval = 0;
2317 f->sk_csum_start = htole32(((offset + m->m_pkthdr.csum_data) & 0xffff) |
2318 (offset << 16));
2319 }
2320
2321 static int
sk_encap(struct sk_if_softc * sc_if,struct mbuf ** m_head)2322 sk_encap(struct sk_if_softc *sc_if, struct mbuf **m_head)
2323 {
2324 struct sk_txdesc *txd;
2325 struct sk_tx_desc *f = NULL;
2326 struct mbuf *m;
2327 bus_dma_segment_t txsegs[SK_MAXTXSEGS];
2328 u_int32_t cflags, frag, si, sk_ctl;
2329 int error, i, nseg;
2330
2331 SK_IF_LOCK_ASSERT(sc_if);
2332
2333 if ((txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txfreeq)) == NULL)
2334 return (ENOBUFS);
2335
2336 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag,
2337 txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
2338 if (error == EFBIG) {
2339 m = m_defrag(*m_head, M_NOWAIT);
2340 if (m == NULL) {
2341 m_freem(*m_head);
2342 *m_head = NULL;
2343 return (ENOMEM);
2344 }
2345 *m_head = m;
2346 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag,
2347 txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
2348 if (error != 0) {
2349 m_freem(*m_head);
2350 *m_head = NULL;
2351 return (error);
2352 }
2353 } else if (error != 0)
2354 return (error);
2355 if (nseg == 0) {
2356 m_freem(*m_head);
2357 *m_head = NULL;
2358 return (EIO);
2359 }
2360 if (sc_if->sk_cdata.sk_tx_cnt + nseg >= SK_TX_RING_CNT) {
2361 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap);
2362 return (ENOBUFS);
2363 }
2364
2365 m = *m_head;
2366 if ((m->m_pkthdr.csum_flags & if_gethwassist(sc_if->sk_ifp)) != 0)
2367 cflags = SK_OPCODE_CSUM;
2368 else
2369 cflags = SK_OPCODE_DEFAULT;
2370 si = frag = sc_if->sk_cdata.sk_tx_prod;
2371 for (i = 0; i < nseg; i++) {
2372 f = &sc_if->sk_rdata.sk_tx_ring[frag];
2373 f->sk_data_lo = htole32(SK_ADDR_LO(txsegs[i].ds_addr));
2374 f->sk_data_hi = htole32(SK_ADDR_HI(txsegs[i].ds_addr));
2375 sk_ctl = txsegs[i].ds_len | cflags;
2376 if (i == 0) {
2377 if (cflags == SK_OPCODE_CSUM)
2378 sk_txcksum(sc_if->sk_ifp, m, f);
2379 sk_ctl |= SK_TXCTL_FIRSTFRAG;
2380 } else
2381 sk_ctl |= SK_TXCTL_OWN;
2382 f->sk_ctl = htole32(sk_ctl);
2383 sc_if->sk_cdata.sk_tx_cnt++;
2384 SK_INC(frag, SK_TX_RING_CNT);
2385 }
2386 sc_if->sk_cdata.sk_tx_prod = frag;
2387
2388 /* set EOF on the last descriptor */
2389 frag = (frag + SK_TX_RING_CNT - 1) % SK_TX_RING_CNT;
2390 f = &sc_if->sk_rdata.sk_tx_ring[frag];
2391 f->sk_ctl |= htole32(SK_TXCTL_LASTFRAG | SK_TXCTL_EOF_INTR);
2392
2393 /* turn the first descriptor ownership to NIC */
2394 f = &sc_if->sk_rdata.sk_tx_ring[si];
2395 f->sk_ctl |= htole32(SK_TXCTL_OWN);
2396
2397 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txfreeq, tx_q);
2398 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txbusyq, txd, tx_q);
2399 txd->tx_m = m;
2400
2401 /* sync descriptors */
2402 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap,
2403 BUS_DMASYNC_PREWRITE);
2404 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2405 sc_if->sk_cdata.sk_tx_ring_map,
2406 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2407
2408 return (0);
2409 }
2410
2411 static void
sk_start(if_t ifp)2412 sk_start(if_t ifp)
2413 {
2414 struct sk_if_softc *sc_if;
2415
2416 sc_if = if_getsoftc(ifp);
2417
2418 SK_IF_LOCK(sc_if);
2419 sk_start_locked(ifp);
2420 SK_IF_UNLOCK(sc_if);
2421
2422 return;
2423 }
2424
2425 static void
sk_start_locked(if_t ifp)2426 sk_start_locked(if_t ifp)
2427 {
2428 struct sk_softc *sc;
2429 struct sk_if_softc *sc_if;
2430 struct mbuf *m_head;
2431 int enq;
2432
2433 sc_if = if_getsoftc(ifp);
2434 sc = sc_if->sk_softc;
2435
2436 SK_IF_LOCK_ASSERT(sc_if);
2437
2438 for (enq = 0; !if_sendq_empty(ifp) &&
2439 sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 1; ) {
2440 m_head = if_dequeue(ifp);
2441 if (m_head == NULL)
2442 break;
2443
2444 /*
2445 * Pack the data into the transmit ring. If we
2446 * don't have room, set the OACTIVE flag and wait
2447 * for the NIC to drain the ring.
2448 */
2449 if (sk_encap(sc_if, &m_head)) {
2450 if (m_head == NULL)
2451 break;
2452 if_sendq_prepend(ifp, m_head);
2453 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
2454 break;
2455 }
2456
2457 enq++;
2458 /*
2459 * If there's a BPF listener, bounce a copy of this frame
2460 * to him.
2461 */
2462 BPF_MTAP(ifp, m_head);
2463 }
2464
2465 if (enq > 0) {
2466 /* Transmit */
2467 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
2468
2469 /* Set a timeout in case the chip goes out to lunch. */
2470 sc_if->sk_watchdog_timer = 5;
2471 }
2472 }
2473
2474 static void
sk_watchdog(void * arg)2475 sk_watchdog(void *arg)
2476 {
2477 struct sk_if_softc *sc_if;
2478 if_t ifp;
2479
2480 ifp = arg;
2481 sc_if = if_getsoftc(ifp);
2482
2483 SK_IF_LOCK_ASSERT(sc_if);
2484
2485 if (sc_if->sk_watchdog_timer == 0 || --sc_if->sk_watchdog_timer)
2486 goto done;
2487
2488 /*
2489 * Reclaim first as there is a possibility of losing Tx completion
2490 * interrupts.
2491 */
2492 sk_txeof(sc_if);
2493 if (sc_if->sk_cdata.sk_tx_cnt != 0) {
2494 if_printf(sc_if->sk_ifp, "watchdog timeout\n");
2495 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2496 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2497 sk_init_locked(sc_if);
2498 }
2499
2500 done:
2501 callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp);
2502
2503 return;
2504 }
2505
2506 static int
skc_shutdown(device_t dev)2507 skc_shutdown(device_t dev)
2508 {
2509 struct sk_softc *sc;
2510
2511 sc = device_get_softc(dev);
2512 SK_LOCK(sc);
2513
2514 /* Turn off the 'driver is loaded' LED. */
2515 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
2516
2517 /*
2518 * Reset the GEnesis controller. Doing this should also
2519 * assert the resets on the attached XMAC(s).
2520 */
2521 sk_reset(sc);
2522 SK_UNLOCK(sc);
2523
2524 return (0);
2525 }
2526
2527 static int
skc_suspend(device_t dev)2528 skc_suspend(device_t dev)
2529 {
2530 struct sk_softc *sc;
2531 struct sk_if_softc *sc_if0, *sc_if1;
2532 if_t ifp0 = NULL, ifp1 = NULL;
2533
2534 sc = device_get_softc(dev);
2535
2536 SK_LOCK(sc);
2537
2538 sc_if0 = sc->sk_if[SK_PORT_A];
2539 sc_if1 = sc->sk_if[SK_PORT_B];
2540 if (sc_if0 != NULL)
2541 ifp0 = sc_if0->sk_ifp;
2542 if (sc_if1 != NULL)
2543 ifp1 = sc_if1->sk_ifp;
2544 if (ifp0 != NULL)
2545 sk_stop(sc_if0);
2546 if (ifp1 != NULL)
2547 sk_stop(sc_if1);
2548 sc->sk_suspended = 1;
2549
2550 SK_UNLOCK(sc);
2551
2552 return (0);
2553 }
2554
2555 static int
skc_resume(device_t dev)2556 skc_resume(device_t dev)
2557 {
2558 struct sk_softc *sc;
2559 struct sk_if_softc *sc_if0, *sc_if1;
2560 if_t ifp0 = NULL, ifp1 = NULL;
2561
2562 sc = device_get_softc(dev);
2563
2564 SK_LOCK(sc);
2565
2566 sc_if0 = sc->sk_if[SK_PORT_A];
2567 sc_if1 = sc->sk_if[SK_PORT_B];
2568 if (sc_if0 != NULL)
2569 ifp0 = sc_if0->sk_ifp;
2570 if (sc_if1 != NULL)
2571 ifp1 = sc_if1->sk_ifp;
2572 if (ifp0 != NULL && if_getflags(ifp0) & IFF_UP)
2573 sk_init_locked(sc_if0);
2574 if (ifp1 != NULL && if_getflags(ifp1) & IFF_UP)
2575 sk_init_locked(sc_if1);
2576 sc->sk_suspended = 0;
2577
2578 SK_UNLOCK(sc);
2579
2580 return (0);
2581 }
2582
2583 /*
2584 * According to the data sheet from SK-NET GENESIS the hardware can compute
2585 * two Rx checksums at the same time(Each checksum start position is
2586 * programmed in Rx descriptors). However it seems that TCP/UDP checksum
2587 * does not work at least on my Yukon hardware. I tried every possible ways
2588 * to get correct checksum value but couldn't get correct one. So TCP/UDP
2589 * checksum offload was disabled at the moment and only IP checksum offload
2590 * was enabled.
2591 * As normal IP header size is 20 bytes I can't expect it would give an
2592 * increase in throughput. However it seems it doesn't hurt performance in
2593 * my testing. If there is a more detailed information for checksum secret
2594 * of the hardware in question please contact yongari@FreeBSD.org to add
2595 * TCP/UDP checksum offload support.
2596 */
2597 static __inline void
sk_rxcksum(if_t ifp,struct mbuf * m,u_int32_t csum)2598 sk_rxcksum(if_t ifp, struct mbuf *m, u_int32_t csum)
2599 {
2600 struct ether_header *eh;
2601 struct ip *ip;
2602 int32_t hlen, len, pktlen;
2603 u_int16_t csum1, csum2, ipcsum;
2604
2605 pktlen = m->m_pkthdr.len;
2606 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
2607 return;
2608 eh = mtod(m, struct ether_header *);
2609 if (eh->ether_type != htons(ETHERTYPE_IP))
2610 return;
2611 ip = (struct ip *)(eh + 1);
2612 if (ip->ip_v != IPVERSION)
2613 return;
2614 hlen = ip->ip_hl << 2;
2615 pktlen -= sizeof(struct ether_header);
2616 if (hlen < sizeof(struct ip))
2617 return;
2618 if (ntohs(ip->ip_len) < hlen)
2619 return;
2620 if (ntohs(ip->ip_len) != pktlen)
2621 return;
2622
2623 csum1 = htons(csum & 0xffff);
2624 csum2 = htons((csum >> 16) & 0xffff);
2625 ipcsum = in_addword(csum1, ~csum2 & 0xffff);
2626 /* checksum fixup for IP options */
2627 len = hlen - sizeof(struct ip);
2628 if (len > 0) {
2629 /*
2630 * If the second checksum value is correct we can compute IP
2631 * checksum with simple math. Unfortunately the second checksum
2632 * value is wrong so we can't verify the checksum from the
2633 * value(It seems there is some magic here to get correct
2634 * value). If the second checksum value is correct it also
2635 * means we can get TCP/UDP checksum) here. However, it still
2636 * needs pseudo header checksum calculation due to hardware
2637 * limitations.
2638 */
2639 return;
2640 }
2641 m->m_pkthdr.csum_flags = CSUM_IP_CHECKED;
2642 if (ipcsum == 0xffff)
2643 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2644 }
2645
2646 static __inline int
sk_rxvalid(struct sk_softc * sc,u_int32_t stat,u_int32_t len)2647 sk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len)
2648 {
2649
2650 if (sc->sk_type == SK_GENESIS) {
2651 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME ||
2652 XM_RXSTAT_BYTES(stat) != len)
2653 return (0);
2654 } else {
2655 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR |
2656 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC |
2657 YU_RXSTAT_JABBER)) != 0 ||
2658 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK ||
2659 YU_RXSTAT_BYTES(stat) != len)
2660 return (0);
2661 }
2662
2663 return (1);
2664 }
2665
2666 static void
sk_rxeof(struct sk_if_softc * sc_if)2667 sk_rxeof(struct sk_if_softc *sc_if)
2668 {
2669 struct sk_softc *sc;
2670 struct mbuf *m;
2671 if_t ifp;
2672 struct sk_rx_desc *cur_rx;
2673 struct sk_rxdesc *rxd;
2674 int cons, prog;
2675 u_int32_t csum, rxstat, sk_ctl;
2676
2677 sc = sc_if->sk_softc;
2678 ifp = sc_if->sk_ifp;
2679
2680 SK_IF_LOCK_ASSERT(sc_if);
2681
2682 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
2683 sc_if->sk_cdata.sk_rx_ring_map, BUS_DMASYNC_POSTREAD);
2684
2685 prog = 0;
2686 for (cons = sc_if->sk_cdata.sk_rx_cons; prog < SK_RX_RING_CNT;
2687 prog++, SK_INC(cons, SK_RX_RING_CNT)) {
2688 cur_rx = &sc_if->sk_rdata.sk_rx_ring[cons];
2689 sk_ctl = le32toh(cur_rx->sk_ctl);
2690 if ((sk_ctl & SK_RXCTL_OWN) != 0)
2691 break;
2692 rxd = &sc_if->sk_cdata.sk_rxdesc[cons];
2693 rxstat = le32toh(cur_rx->sk_xmac_rxstat);
2694
2695 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
2696 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
2697 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
2698 SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN ||
2699 SK_RXBYTES(sk_ctl) > SK_MAX_FRAMELEN ||
2700 sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) {
2701 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
2702 sk_discard_rxbuf(sc_if, cons);
2703 continue;
2704 }
2705
2706 m = rxd->rx_m;
2707 csum = le32toh(cur_rx->sk_csum);
2708 if (sk_newbuf(sc_if, cons) != 0) {
2709 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2710 /* reuse old buffer */
2711 sk_discard_rxbuf(sc_if, cons);
2712 continue;
2713 }
2714 m->m_pkthdr.rcvif = ifp;
2715 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl);
2716 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
2717 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
2718 sk_rxcksum(ifp, m, csum);
2719 SK_IF_UNLOCK(sc_if);
2720 if_input(ifp, m);
2721 SK_IF_LOCK(sc_if);
2722 }
2723
2724 if (prog > 0) {
2725 sc_if->sk_cdata.sk_rx_cons = cons;
2726 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
2727 sc_if->sk_cdata.sk_rx_ring_map,
2728 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2729 }
2730 }
2731
2732 static void
sk_jumbo_rxeof(struct sk_if_softc * sc_if)2733 sk_jumbo_rxeof(struct sk_if_softc *sc_if)
2734 {
2735 struct sk_softc *sc;
2736 struct mbuf *m;
2737 if_t ifp;
2738 struct sk_rx_desc *cur_rx;
2739 struct sk_rxdesc *jrxd;
2740 int cons, prog;
2741 u_int32_t csum, rxstat, sk_ctl;
2742
2743 sc = sc_if->sk_softc;
2744 ifp = sc_if->sk_ifp;
2745
2746 SK_IF_LOCK_ASSERT(sc_if);
2747
2748 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2749 sc_if->sk_cdata.sk_jumbo_rx_ring_map, BUS_DMASYNC_POSTREAD);
2750
2751 prog = 0;
2752 for (cons = sc_if->sk_cdata.sk_jumbo_rx_cons;
2753 prog < SK_JUMBO_RX_RING_CNT;
2754 prog++, SK_INC(cons, SK_JUMBO_RX_RING_CNT)) {
2755 cur_rx = &sc_if->sk_rdata.sk_jumbo_rx_ring[cons];
2756 sk_ctl = le32toh(cur_rx->sk_ctl);
2757 if ((sk_ctl & SK_RXCTL_OWN) != 0)
2758 break;
2759 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[cons];
2760 rxstat = le32toh(cur_rx->sk_xmac_rxstat);
2761
2762 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
2763 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
2764 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
2765 SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN ||
2766 SK_RXBYTES(sk_ctl) > SK_JUMBO_FRAMELEN ||
2767 sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) {
2768 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
2769 sk_discard_jumbo_rxbuf(sc_if, cons);
2770 continue;
2771 }
2772
2773 m = jrxd->rx_m;
2774 csum = le32toh(cur_rx->sk_csum);
2775 if (sk_jumbo_newbuf(sc_if, cons) != 0) {
2776 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2777 /* reuse old buffer */
2778 sk_discard_jumbo_rxbuf(sc_if, cons);
2779 continue;
2780 }
2781 m->m_pkthdr.rcvif = ifp;
2782 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl);
2783 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
2784 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
2785 sk_rxcksum(ifp, m, csum);
2786 SK_IF_UNLOCK(sc_if);
2787 if_input(ifp, m);
2788 SK_IF_LOCK(sc_if);
2789 }
2790
2791 if (prog > 0) {
2792 sc_if->sk_cdata.sk_jumbo_rx_cons = cons;
2793 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2794 sc_if->sk_cdata.sk_jumbo_rx_ring_map,
2795 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2796 }
2797 }
2798
2799 static void
sk_txeof(struct sk_if_softc * sc_if)2800 sk_txeof(struct sk_if_softc *sc_if)
2801 {
2802 struct sk_txdesc *txd;
2803 struct sk_tx_desc *cur_tx;
2804 if_t ifp;
2805 u_int32_t idx, sk_ctl;
2806
2807 ifp = sc_if->sk_ifp;
2808
2809 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq);
2810 if (txd == NULL)
2811 return;
2812 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2813 sc_if->sk_cdata.sk_tx_ring_map, BUS_DMASYNC_POSTREAD);
2814 /*
2815 * Go through our tx ring and free mbufs for those
2816 * frames that have been sent.
2817 */
2818 for (idx = sc_if->sk_cdata.sk_tx_cons;; SK_INC(idx, SK_TX_RING_CNT)) {
2819 if (sc_if->sk_cdata.sk_tx_cnt <= 0)
2820 break;
2821 cur_tx = &sc_if->sk_rdata.sk_tx_ring[idx];
2822 sk_ctl = le32toh(cur_tx->sk_ctl);
2823 if (sk_ctl & SK_TXCTL_OWN)
2824 break;
2825 sc_if->sk_cdata.sk_tx_cnt--;
2826 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
2827 if ((sk_ctl & SK_TXCTL_LASTFRAG) == 0)
2828 continue;
2829 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap,
2830 BUS_DMASYNC_POSTWRITE);
2831 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap);
2832
2833 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
2834 m_freem(txd->tx_m);
2835 txd->tx_m = NULL;
2836 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txbusyq, tx_q);
2837 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q);
2838 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq);
2839 }
2840 sc_if->sk_cdata.sk_tx_cons = idx;
2841 sc_if->sk_watchdog_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0;
2842
2843 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2844 sc_if->sk_cdata.sk_tx_ring_map,
2845 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2846 }
2847
2848 static void
sk_tick(void * xsc_if)2849 sk_tick(void *xsc_if)
2850 {
2851 struct sk_if_softc *sc_if;
2852 struct mii_data *mii;
2853 if_t ifp;
2854 int i;
2855
2856 sc_if = xsc_if;
2857 ifp = sc_if->sk_ifp;
2858 mii = device_get_softc(sc_if->sk_miibus);
2859
2860 if (!(if_getflags(ifp) & IFF_UP))
2861 return;
2862
2863 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2864 sk_intr_bcom(sc_if);
2865 return;
2866 }
2867
2868 /*
2869 * According to SysKonnect, the correct way to verify that
2870 * the link has come back up is to poll bit 0 of the GPIO
2871 * register three times. This pin has the signal from the
2872 * link_sync pin connected to it; if we read the same link
2873 * state 3 times in a row, we know the link is up.
2874 */
2875 for (i = 0; i < 3; i++) {
2876 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
2877 break;
2878 }
2879
2880 if (i != 3) {
2881 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
2882 return;
2883 }
2884
2885 /* Turn the GP0 interrupt back on. */
2886 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2887 SK_XM_READ_2(sc_if, XM_ISR);
2888 mii_tick(mii);
2889 callout_stop(&sc_if->sk_tick_ch);
2890 }
2891
2892 static void
sk_yukon_tick(void * xsc_if)2893 sk_yukon_tick(void *xsc_if)
2894 {
2895 struct sk_if_softc *sc_if;
2896 struct mii_data *mii;
2897
2898 sc_if = xsc_if;
2899 mii = device_get_softc(sc_if->sk_miibus);
2900
2901 mii_tick(mii);
2902 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if);
2903 }
2904
2905 static void
sk_intr_bcom(struct sk_if_softc * sc_if)2906 sk_intr_bcom(struct sk_if_softc *sc_if)
2907 {
2908 struct mii_data *mii;
2909 if_t ifp;
2910 int status;
2911 mii = device_get_softc(sc_if->sk_miibus);
2912 ifp = sc_if->sk_ifp;
2913
2914 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2915
2916 /*
2917 * Read the PHY interrupt register to make sure
2918 * we clear any pending interrupts.
2919 */
2920 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR);
2921
2922 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
2923 sk_init_xmac(sc_if);
2924 return;
2925 }
2926
2927 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) {
2928 int lstat;
2929 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM,
2930 BRGPHY_MII_AUXSTS);
2931
2932 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
2933 mii_mediachg(mii);
2934 /* Turn off the link LED. */
2935 SK_IF_WRITE_1(sc_if, 0,
2936 SK_LINKLED1_CTL, SK_LINKLED_OFF);
2937 sc_if->sk_link = 0;
2938 } else if (status & BRGPHY_ISR_LNK_CHG) {
2939 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2940 BRGPHY_MII_IMR, 0xFF00);
2941 mii_tick(mii);
2942 sc_if->sk_link = 1;
2943 /* Turn on the link LED. */
2944 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2945 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF|
2946 SK_LINKLED_BLINK_OFF);
2947 } else {
2948 mii_tick(mii);
2949 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
2950 }
2951 }
2952
2953 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2954
2955 return;
2956 }
2957
2958 static void
sk_intr_xmac(struct sk_if_softc * sc_if)2959 sk_intr_xmac(struct sk_if_softc *sc_if)
2960 {
2961 u_int16_t status;
2962
2963 status = SK_XM_READ_2(sc_if, XM_ISR);
2964
2965 /*
2966 * Link has gone down. Start MII tick timeout to
2967 * watch for link resync.
2968 */
2969 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) {
2970 if (status & XM_ISR_GP0_SET) {
2971 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2972 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
2973 }
2974
2975 if (status & XM_ISR_AUTONEG_DONE) {
2976 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
2977 }
2978 }
2979
2980 if (status & XM_IMR_TX_UNDERRUN)
2981 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
2982
2983 if (status & XM_IMR_RX_OVERRUN)
2984 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
2985
2986 status = SK_XM_READ_2(sc_if, XM_ISR);
2987
2988 return;
2989 }
2990
2991 static void
sk_intr_yukon(struct sk_if_softc * sc_if)2992 sk_intr_yukon(struct sk_if_softc *sc_if)
2993 {
2994 u_int8_t status;
2995
2996 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR);
2997 /* RX overrun */
2998 if ((status & SK_GMAC_INT_RX_OVER) != 0) {
2999 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
3000 SK_RFCTL_RX_FIFO_OVER);
3001 }
3002 /* TX underrun */
3003 if ((status & SK_GMAC_INT_TX_UNDER) != 0) {
3004 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
3005 SK_TFCTL_TX_FIFO_UNDER);
3006 }
3007 }
3008
3009 static void
sk_intr(void * xsc)3010 sk_intr(void *xsc)
3011 {
3012 struct sk_softc *sc = xsc;
3013 struct sk_if_softc *sc_if0, *sc_if1;
3014 if_t ifp0 = NULL, ifp1 = NULL;
3015 u_int32_t status;
3016
3017 SK_LOCK(sc);
3018
3019 #ifndef __HAIKU__
3020 status = CSR_READ_4(sc, SK_ISSR);
3021 if (status == 0 || status == 0xffffffff || sc->sk_suspended)
3022 goto done_locked;
3023 #endif
3024
3025 sc_if0 = sc->sk_if[SK_PORT_A];
3026 sc_if1 = sc->sk_if[SK_PORT_B];
3027
3028 if (sc_if0 != NULL)
3029 ifp0 = sc_if0->sk_ifp;
3030 if (sc_if1 != NULL)
3031 ifp1 = sc_if1->sk_ifp;
3032
3033 #ifndef __HAIKU__
3034 for (; (status &= sc->sk_intrmask) != 0;) {
3035 #else
3036 status = atomic_get((int32 *)&sc->sk_intstatus);
3037 status &= sc->sk_intrmask;
3038 while (true) {
3039
3040 if (status == 0 || status == 0xffffffff || sc->sk_suspended)
3041 goto done_locked;
3042 #endif
3043 /* Handle receive interrupts first. */
3044 if (status & SK_ISR_RX1_EOF) {
3045 if (if_getmtu(ifp0) > SK_MAX_FRAMELEN)
3046 sk_jumbo_rxeof(sc_if0);
3047 else
3048 sk_rxeof(sc_if0);
3049 CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
3050 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
3051 }
3052 if (status & SK_ISR_RX2_EOF) {
3053 if (if_getflags(ifp1) > SK_MAX_FRAMELEN)
3054 sk_jumbo_rxeof(sc_if1);
3055 else
3056 sk_rxeof(sc_if1);
3057 CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
3058 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
3059 }
3060
3061 /* Then transmit interrupts. */
3062 if (status & SK_ISR_TX1_S_EOF) {
3063 sk_txeof(sc_if0);
3064 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, SK_TXBMU_CLR_IRQ_EOF);
3065 }
3066 if (status & SK_ISR_TX2_S_EOF) {
3067 sk_txeof(sc_if1);
3068 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, SK_TXBMU_CLR_IRQ_EOF);
3069 }
3070
3071 /* Then MAC interrupts. */
3072 if (status & SK_ISR_MAC1 &&
3073 if_getdrvflags(ifp0) & IFF_DRV_RUNNING) {
3074 if (sc->sk_type == SK_GENESIS)
3075 sk_intr_xmac(sc_if0);
3076 else
3077 sk_intr_yukon(sc_if0);
3078 }
3079
3080 if (status & SK_ISR_MAC2 &&
3081 if_getdrvflags(ifp1) & IFF_DRV_RUNNING) {
3082 if (sc->sk_type == SK_GENESIS)
3083 sk_intr_xmac(sc_if1);
3084 else
3085 sk_intr_yukon(sc_if1);
3086 }
3087
3088 if (status & SK_ISR_EXTERNAL_REG) {
3089 if (ifp0 != NULL &&
3090 sc_if0->sk_phytype == SK_PHYTYPE_BCOM)
3091 sk_intr_bcom(sc_if0);
3092 if (ifp1 != NULL &&
3093 sc_if1->sk_phytype == SK_PHYTYPE_BCOM)
3094 sk_intr_bcom(sc_if1);
3095 }
3096 status = CSR_READ_4(sc, SK_ISSR);
3097 #ifdef __HAIKU__
3098 if (((status & sc->sk_intrmask) == 0) || status == 0xffffffff ||
3099 sc->sk_suspended) {
3100 break;
3101 }
3102 #endif
3103 }
3104
3105 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3106
3107 if (ifp0 != NULL && !if_sendq_empty(ifp0))
3108 sk_start_locked(ifp0);
3109 if (ifp1 != NULL && !if_sendq_empty(ifp1))
3110 sk_start_locked(ifp1);
3111
3112 done_locked:
3113 SK_UNLOCK(sc);
3114 }
3115
3116 static void
3117 sk_init_xmac(struct sk_if_softc *sc_if)
3118 {
3119 struct sk_softc *sc;
3120 if_t ifp;
3121 u_int16_t eaddr[(ETHER_ADDR_LEN+1)/2];
3122 static const struct sk_bcom_hack bhack[] = {
3123 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
3124 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
3125 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
3126 { 0, 0 } };
3127
3128 SK_IF_LOCK_ASSERT(sc_if);
3129
3130 sc = sc_if->sk_softc;
3131 ifp = sc_if->sk_ifp;
3132
3133 /* Unreset the XMAC. */
3134 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
3135 DELAY(1000);
3136
3137 /* Reset the XMAC's internal state. */
3138 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
3139
3140 /* Save the XMAC II revision */
3141 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
3142
3143 /*
3144 * Perform additional initialization for external PHYs,
3145 * namely for the 1000baseTX cards that use the XMAC's
3146 * GMII mode.
3147 */
3148 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
3149 int i = 0;
3150 u_int32_t val;
3151
3152 /* Take PHY out of reset. */
3153 val = sk_win_read_4(sc, SK_GPIO);
3154 if (sc_if->sk_port == SK_PORT_A)
3155 val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
3156 else
3157 val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
3158 sk_win_write_4(sc, SK_GPIO, val);
3159
3160 /* Enable GMII mode on the XMAC. */
3161 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
3162
3163 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3164 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
3165 DELAY(10000);
3166 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3167 BRGPHY_MII_IMR, 0xFFF0);
3168
3169 /*
3170 * Early versions of the BCM5400 apparently have
3171 * a bug that requires them to have their reserved
3172 * registers initialized to some magic values. I don't
3173 * know what the numbers do, I'm just the messenger.
3174 */
3175 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03)
3176 == 0x6041) {
3177 while(bhack[i].reg) {
3178 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3179 bhack[i].reg, bhack[i].val);
3180 i++;
3181 }
3182 }
3183 }
3184
3185 /* Set station address */
3186 bcopy(if_getlladdr(sc_if->sk_ifp), eaddr, ETHER_ADDR_LEN);
3187 SK_XM_WRITE_2(sc_if, XM_PAR0, eaddr[0]);
3188 SK_XM_WRITE_2(sc_if, XM_PAR1, eaddr[1]);
3189 SK_XM_WRITE_2(sc_if, XM_PAR2, eaddr[2]);
3190 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
3191
3192 if (if_getflags(ifp) & IFF_BROADCAST) {
3193 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
3194 } else {
3195 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
3196 }
3197
3198 /* We don't need the FCS appended to the packet. */
3199 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
3200
3201 /* We want short frames padded to 60 bytes. */
3202 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
3203
3204 /*
3205 * Enable the reception of all error frames. This is is
3206 * a necessary evil due to the design of the XMAC. The
3207 * XMAC's receive FIFO is only 8K in size, however jumbo
3208 * frames can be up to 9000 bytes in length. When bad
3209 * frame filtering is enabled, the XMAC's RX FIFO operates
3210 * in 'store and forward' mode. For this to work, the
3211 * entire frame has to fit into the FIFO, but that means
3212 * that jumbo frames larger than 8192 bytes will be
3213 * truncated. Disabling all bad frame filtering causes
3214 * the RX FIFO to operate in streaming mode, in which
3215 * case the XMAC will start transferring frames out of the
3216 * RX FIFO as soon as the FIFO threshold is reached.
3217 */
3218 if (if_getmtu(ifp) > SK_MAX_FRAMELEN) {
3219 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES|
3220 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS|
3221 XM_MODE_RX_INRANGELEN);
3222 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
3223 } else
3224 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
3225
3226 /*
3227 * Bump up the transmit threshold. This helps hold off transmit
3228 * underruns when we're blasting traffic from both ports at once.
3229 */
3230 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
3231
3232 /* Set Rx filter */
3233 sk_rxfilter_genesis(sc_if);
3234
3235 /* Clear and enable interrupts */
3236 SK_XM_READ_2(sc_if, XM_ISR);
3237 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
3238 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
3239 else
3240 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
3241
3242 /* Configure MAC arbiter */
3243 switch(sc_if->sk_xmac_rev) {
3244 case XM_XMAC_REV_B2:
3245 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
3246 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
3247 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
3248 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
3249 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
3250 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
3251 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
3252 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
3253 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
3254 break;
3255 case XM_XMAC_REV_C1:
3256 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
3257 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
3258 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
3259 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
3260 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
3261 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
3262 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
3263 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
3264 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
3265 break;
3266 default:
3267 break;
3268 }
3269 sk_win_write_2(sc, SK_MACARB_CTL,
3270 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF);
3271
3272 sc_if->sk_link = 1;
3273
3274 return;
3275 }
3276
3277 static void
3278 sk_init_yukon(struct sk_if_softc *sc_if)
3279 {
3280 u_int32_t phy, v;
3281 u_int16_t reg;
3282 struct sk_softc *sc;
3283 if_t ifp;
3284 u_int8_t *eaddr;
3285 int i;
3286
3287 SK_IF_LOCK_ASSERT(sc_if);
3288
3289 sc = sc_if->sk_softc;
3290 ifp = sc_if->sk_ifp;
3291
3292 if (sc->sk_type == SK_YUKON_LITE &&
3293 sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
3294 /*
3295 * Workaround code for COMA mode, set PHY reset.
3296 * Otherwise it will not correctly take chip out of
3297 * powerdown (coma)
3298 */
3299 v = sk_win_read_4(sc, SK_GPIO);
3300 v |= SK_GPIO_DIR9 | SK_GPIO_DAT9;
3301 sk_win_write_4(sc, SK_GPIO, v);
3302 }
3303
3304 /* GMAC and GPHY Reset */
3305 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
3306 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
3307 DELAY(1000);
3308
3309 if (sc->sk_type == SK_YUKON_LITE &&
3310 sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
3311 /*
3312 * Workaround code for COMA mode, clear PHY reset
3313 */
3314 v = sk_win_read_4(sc, SK_GPIO);
3315 v |= SK_GPIO_DIR9;
3316 v &= ~SK_GPIO_DAT9;
3317 sk_win_write_4(sc, SK_GPIO, v);
3318 }
3319
3320 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |
3321 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE;
3322
3323 if (sc->sk_coppertype)
3324 phy |= SK_GPHY_COPPER;
3325 else
3326 phy |= SK_GPHY_FIBER;
3327
3328 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
3329 DELAY(1000);
3330 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
3331 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
3332 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
3333
3334 /* unused read of the interrupt source register */
3335 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
3336
3337 reg = SK_YU_READ_2(sc_if, YUKON_PAR);
3338
3339 /* MIB Counter Clear Mode set */
3340 reg |= YU_PAR_MIB_CLR;
3341 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
3342
3343 /* MIB Counter Clear Mode clear */
3344 reg &= ~YU_PAR_MIB_CLR;
3345 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
3346
3347 /* receive control reg */
3348 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
3349
3350 /* transmit parameter register */
3351 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
3352 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) );
3353
3354 /* serial mode register */
3355 reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e);
3356 if (if_getmtu(ifp) > SK_MAX_FRAMELEN)
3357 reg |= YU_SMR_MFL_JUMBO;
3358 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);
3359
3360 /* Setup Yukon's station address */
3361 eaddr = if_getlladdr(sc_if->sk_ifp);
3362 for (i = 0; i < 3; i++)
3363 SK_YU_WRITE_2(sc_if, SK_MAC0_0 + i * 4,
3364 eaddr[i * 2] | eaddr[i * 2 + 1] << 8);
3365 /* Set GMAC source address of flow control. */
3366 for (i = 0; i < 3; i++)
3367 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4,
3368 eaddr[i * 2] | eaddr[i * 2 + 1] << 8);
3369 /* Set GMAC virtual address. */
3370 for (i = 0; i < 3; i++)
3371 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4,
3372 eaddr[i * 2] | eaddr[i * 2 + 1] << 8);
3373
3374 /* Set Rx filter */
3375 sk_rxfilter_yukon(sc_if);
3376
3377 /* enable interrupt mask for counter overflows */
3378 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
3379 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
3380 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
3381
3382 /* Configure RX MAC FIFO Flush Mask */
3383 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR |
3384 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT |
3385 YU_RXSTAT_JABBER;
3386 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v);
3387
3388 /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */
3389 if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0)
3390 v = SK_TFCTL_OPERATION_ON;
3391 else
3392 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON;
3393 /* Configure RX MAC FIFO */
3394 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
3395 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v);
3396
3397 /* Increase flush threshould to 64 bytes */
3398 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD,
3399 SK_RFCTL_FIFO_THRESHOLD + 1);
3400
3401 /* Configure TX MAC FIFO */
3402 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
3403 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
3404 }
3405
3406 /*
3407 * Note that to properly initialize any part of the GEnesis chip,
3408 * you first have to take it out of reset mode.
3409 */
3410 static void
3411 sk_init(void *xsc)
3412 {
3413 struct sk_if_softc *sc_if = xsc;
3414
3415 SK_IF_LOCK(sc_if);
3416 sk_init_locked(sc_if);
3417 SK_IF_UNLOCK(sc_if);
3418
3419 return;
3420 }
3421
3422 static void
3423 sk_init_locked(struct sk_if_softc *sc_if)
3424 {
3425 struct sk_softc *sc;
3426 if_t ifp;
3427 struct mii_data *mii;
3428 u_int16_t reg;
3429 u_int32_t imr;
3430 int error;
3431
3432 SK_IF_LOCK_ASSERT(sc_if);
3433
3434 ifp = sc_if->sk_ifp;
3435 sc = sc_if->sk_softc;
3436 mii = device_get_softc(sc_if->sk_miibus);
3437
3438 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
3439 return;
3440
3441 /* Cancel pending I/O and free all RX/TX buffers. */
3442 sk_stop(sc_if);
3443
3444 if (sc->sk_type == SK_GENESIS) {
3445 /* Configure LINK_SYNC LED */
3446 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
3447 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
3448 SK_LINKLED_LINKSYNC_ON);
3449
3450 /* Configure RX LED */
3451 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL,
3452 SK_RXLEDCTL_COUNTER_START);
3453
3454 /* Configure TX LED */
3455 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL,
3456 SK_TXLEDCTL_COUNTER_START);
3457 }
3458
3459 /*
3460 * Configure descriptor poll timer
3461 *
3462 * SK-NET GENESIS data sheet says that possibility of losing Start
3463 * transmit command due to CPU/cache related interim storage problems
3464 * under certain conditions. The document recommends a polling
3465 * mechanism to send a Start transmit command to initiate transfer
3466 * of ready descriptors regulary. To cope with this issue sk(4) now
3467 * enables descriptor poll timer to initiate descriptor processing
3468 * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still
3469 * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx
3470 * command instead of waiting for next descriptor polling time.
3471 * The same rule may apply to Rx side too but it seems that is not
3472 * needed at the moment.
3473 * Since sk(4) uses descriptor polling as a last resort there is no
3474 * need to set smaller polling time than maximum allowable one.
3475 */
3476 SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX);
3477
3478 /* Configure I2C registers */
3479
3480 /* Configure XMAC(s) */
3481 switch (sc->sk_type) {
3482 case SK_GENESIS:
3483 sk_init_xmac(sc_if);
3484 break;
3485 case SK_YUKON:
3486 case SK_YUKON_LITE:
3487 case SK_YUKON_LP:
3488 sk_init_yukon(sc_if);
3489 break;
3490 }
3491 mii_mediachg(mii);
3492
3493 if (sc->sk_type == SK_GENESIS) {
3494 /* Configure MAC FIFOs */
3495 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
3496 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
3497 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
3498
3499 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
3500 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
3501 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
3502 }
3503
3504 /* Configure transmit arbiter(s) */
3505 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
3506 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON);
3507
3508 /* Configure RAMbuffers */
3509 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
3510 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
3511 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
3512 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
3513 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
3514 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
3515
3516 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
3517 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
3518 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
3519 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
3520 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
3521 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
3522 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
3523
3524 /* Configure BMUs */
3525 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
3526 if (if_getmtu(ifp) > SK_MAX_FRAMELEN) {
3527 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
3528 SK_ADDR_LO(SK_JUMBO_RX_RING_ADDR(sc_if, 0)));
3529 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI,
3530 SK_ADDR_HI(SK_JUMBO_RX_RING_ADDR(sc_if, 0)));
3531 } else {
3532 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
3533 SK_ADDR_LO(SK_RX_RING_ADDR(sc_if, 0)));
3534 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI,
3535 SK_ADDR_HI(SK_RX_RING_ADDR(sc_if, 0)));
3536 }
3537
3538 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
3539 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
3540 SK_ADDR_LO(SK_TX_RING_ADDR(sc_if, 0)));
3541 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI,
3542 SK_ADDR_HI(SK_TX_RING_ADDR(sc_if, 0)));
3543
3544 /* Init descriptors */
3545 if (if_getmtu(ifp) > SK_MAX_FRAMELEN)
3546 error = sk_init_jumbo_rx_ring(sc_if);
3547 else
3548 error = sk_init_rx_ring(sc_if);
3549 if (error != 0) {
3550 device_printf(sc_if->sk_if_dev,
3551 "initialization failed: no memory for rx buffers\n");
3552 sk_stop(sc_if);
3553 return;
3554 }
3555 sk_init_tx_ring(sc_if);
3556
3557 /* Set interrupt moderation if changed via sysctl. */
3558 imr = sk_win_read_4(sc, SK_IMTIMERINIT);
3559 if (imr != SK_IM_USECS(sc->sk_int_mod, sc->sk_int_ticks)) {
3560 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod,
3561 sc->sk_int_ticks));
3562 if (bootverbose)
3563 device_printf(sc_if->sk_if_dev,
3564 "interrupt moderation is %d us.\n",
3565 sc->sk_int_mod);
3566 }
3567
3568 /* Configure interrupt handling */
3569 CSR_READ_4(sc, SK_ISSR);
3570 if (sc_if->sk_port == SK_PORT_A)
3571 sc->sk_intrmask |= SK_INTRS1;
3572 else
3573 sc->sk_intrmask |= SK_INTRS2;
3574
3575 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
3576
3577 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3578
3579 /* Start BMUs. */
3580 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
3581
3582 switch(sc->sk_type) {
3583 case SK_GENESIS:
3584 /* Enable XMACs TX and RX state machines */
3585 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
3586 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
3587 break;
3588 case SK_YUKON:
3589 case SK_YUKON_LITE:
3590 case SK_YUKON_LP:
3591 reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
3592 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
3593 #if 0
3594 /* XXX disable 100Mbps and full duplex mode? */
3595 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS);
3596 #endif
3597 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
3598 }
3599
3600 /* Activate descriptor polling timer */
3601 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START);
3602 /* start transfer of Tx descriptors */
3603 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
3604
3605 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
3606 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
3607
3608 switch (sc->sk_type) {
3609 case SK_YUKON:
3610 case SK_YUKON_LITE:
3611 case SK_YUKON_LP:
3612 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if);
3613 break;
3614 }
3615
3616 callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp);
3617
3618 return;
3619 }
3620
3621 static void
3622 sk_stop(struct sk_if_softc *sc_if)
3623 {
3624 int i;
3625 struct sk_softc *sc;
3626 struct sk_txdesc *txd;
3627 struct sk_rxdesc *rxd;
3628 struct sk_rxdesc *jrxd;
3629 if_t ifp;
3630 u_int32_t val;
3631
3632 SK_IF_LOCK_ASSERT(sc_if);
3633 sc = sc_if->sk_softc;
3634 ifp = sc_if->sk_ifp;
3635
3636 callout_stop(&sc_if->sk_tick_ch);
3637 callout_stop(&sc_if->sk_watchdog_ch);
3638
3639 /* stop Tx descriptor polling timer */
3640 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP);
3641 /* stop transfer of Tx descriptors */
3642 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP);
3643 for (i = 0; i < SK_TIMEOUT; i++) {
3644 val = CSR_READ_4(sc, sc_if->sk_tx_bmu);
3645 if ((val & SK_TXBMU_TX_STOP) == 0)
3646 break;
3647 DELAY(1);
3648 }
3649 if (i == SK_TIMEOUT)
3650 device_printf(sc_if->sk_if_dev,
3651 "can not stop transfer of Tx descriptor\n");
3652 /* stop transfer of Rx descriptors */
3653 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP);
3654 for (i = 0; i < SK_TIMEOUT; i++) {
3655 val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR);
3656 if ((val & SK_RXBMU_RX_STOP) == 0)
3657 break;
3658 DELAY(1);
3659 }
3660 if (i == SK_TIMEOUT)
3661 device_printf(sc_if->sk_if_dev,
3662 "can not stop transfer of Rx descriptor\n");
3663
3664 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
3665 /* Put PHY back into reset. */
3666 val = sk_win_read_4(sc, SK_GPIO);
3667 if (sc_if->sk_port == SK_PORT_A) {
3668 val |= SK_GPIO_DIR0;
3669 val &= ~SK_GPIO_DAT0;
3670 } else {
3671 val |= SK_GPIO_DIR2;
3672 val &= ~SK_GPIO_DAT2;
3673 }
3674 sk_win_write_4(sc, SK_GPIO, val);
3675 }
3676
3677 /* Turn off various components of this interface. */
3678 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
3679 switch (sc->sk_type) {
3680 case SK_GENESIS:
3681 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET);
3682 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
3683 break;
3684 case SK_YUKON:
3685 case SK_YUKON_LITE:
3686 case SK_YUKON_LP:
3687 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
3688 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
3689 break;
3690 }
3691 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
3692 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
3693 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
3694 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
3695 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
3696 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
3697 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
3698 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
3699 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
3700
3701 /* Disable interrupts */
3702 if (sc_if->sk_port == SK_PORT_A)
3703 sc->sk_intrmask &= ~SK_INTRS1;
3704 else
3705 sc->sk_intrmask &= ~SK_INTRS2;
3706 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3707
3708 SK_XM_READ_2(sc_if, XM_ISR);
3709 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
3710
3711 /* Free RX and TX mbufs still in the queues. */
3712 for (i = 0; i < SK_RX_RING_CNT; i++) {
3713 rxd = &sc_if->sk_cdata.sk_rxdesc[i];
3714 if (rxd->rx_m != NULL) {
3715 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag,
3716 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3717 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag,
3718 rxd->rx_dmamap);
3719 m_freem(rxd->rx_m);
3720 rxd->rx_m = NULL;
3721 }
3722 }
3723 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
3724 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
3725 if (jrxd->rx_m != NULL) {
3726 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag,
3727 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3728 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag,
3729 jrxd->rx_dmamap);
3730 m_freem(jrxd->rx_m);
3731 jrxd->rx_m = NULL;
3732 }
3733 }
3734 for (i = 0; i < SK_TX_RING_CNT; i++) {
3735 txd = &sc_if->sk_cdata.sk_txdesc[i];
3736 if (txd->tx_m != NULL) {
3737 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag,
3738 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
3739 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag,
3740 txd->tx_dmamap);
3741 m_freem(txd->tx_m);
3742 txd->tx_m = NULL;
3743 }
3744 }
3745
3746 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING|IFF_DRV_OACTIVE));
3747
3748 return;
3749 }
3750
3751 static int
3752 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3753 {
3754 int error, value;
3755
3756 if (!arg1)
3757 return (EINVAL);
3758 value = *(int *)arg1;
3759 error = sysctl_handle_int(oidp, &value, 0, req);
3760 if (error || !req->newptr)
3761 return (error);
3762 if (value < low || value > high)
3763 return (EINVAL);
3764 *(int *)arg1 = value;
3765 return (0);
3766 }
3767
3768 static int
3769 sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS)
3770 {
3771 return (sysctl_int_range(oidp, arg1, arg2, req, SK_IM_MIN, SK_IM_MAX));
3772 }
3773