1 /* $OpenBSD: if_rtwn.c,v 1.6 2015/08/28 00:03:53 deraadt Exp $ */
2
3 /*-
4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
5 * Copyright (c) 2015 Stefan Sperling <stsp@openbsd.org>
6 * Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org>
7 *
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 */
20
21 #include <sys/cdefs.h>
22 #include "opt_wlan.h"
23
24 #include <sys/param.h>
25 #include <sys/lock.h>
26 #include <sys/mutex.h>
27 #include <sys/mbuf.h>
28 #include <sys/kernel.h>
29 #include <sys/socket.h>
30 #include <sys/systm.h>
31 #include <sys/malloc.h>
32 #include <sys/queue.h>
33 #include <sys/taskqueue.h>
34 #include <sys/bus.h>
35 #include <sys/endian.h>
36 #include <sys/linker.h>
37
38 #include <machine/bus.h>
39 #include <machine/resource.h>
40 #include <sys/rman.h>
41
42 #include <net/if.h>
43 #include <net/ethernet.h>
44 #include <net/if_media.h>
45
46 #include <net80211/ieee80211_var.h>
47 #include <net80211/ieee80211_radiotap.h>
48
49 #include <dev/rtwn/if_rtwnvar.h>
50
51 #include <dev/rtwn/pci/rtwn_pci_var.h>
52
53 #include <dev/rtwn/rtl8192c/r92c_var.h>
54
55 #include <dev/rtwn/rtl8192c/pci/r92ce.h>
56 #include <dev/rtwn/rtl8192c/pci/r92ce_reg.h>
57
58 void
r92ce_init_intr(struct rtwn_softc * sc)59 r92ce_init_intr(struct rtwn_softc *sc)
60 {
61 /* Disable interrupts. */
62 rtwn_write_4(sc, R92C_HISR, 0x00000000);
63 rtwn_write_4(sc, R92C_HIMR, 0x00000000);
64 }
65
66 void
r92ce_init_edca(struct rtwn_softc * sc)67 r92ce_init_edca(struct rtwn_softc *sc)
68 {
69 /* SIFS */
70 rtwn_write_2(sc, R92C_SPEC_SIFS, 0x1010);
71 rtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x1010);
72 rtwn_write_2(sc, R92C_SIFS_CCK, 0x1010);
73 rtwn_write_2(sc, R92C_SIFS_OFDM, 0x0e0e);
74 /* TXOP */
75 rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b);
76 rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f);
77 rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4322);
78 rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3222);
79 }
80
81 void
r92ce_init_bb(struct rtwn_softc * sc)82 r92ce_init_bb(struct rtwn_softc *sc)
83 {
84
85 /* Enable BB and RF. */
86 rtwn_setbits_2(sc, R92C_SYS_FUNC_EN, 0,
87 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST |
88 R92C_SYS_FUNC_EN_DIO_RF);
89
90 rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83);
91
92 rtwn_write_1(sc, R92C_RF_CTRL,
93 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB);
94
95 rtwn_write_1(sc, R92C_SYS_FUNC_EN,
96 R92C_SYS_FUNC_EN_DIO_PCIE | R92C_SYS_FUNC_EN_PCIEA |
97 R92C_SYS_FUNC_EN_PPLL | R92C_SYS_FUNC_EN_BB_GLB_RST |
98 R92C_SYS_FUNC_EN_BBRSTB);
99
100 rtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80);
101
102 rtwn_setbits_4(sc, R92C_LEDCFG0, 0, 0x00800000);
103
104 r92c_init_bb_common(sc);
105 }
106
107 int
r92ce_power_on(struct rtwn_softc * sc)108 r92ce_power_on(struct rtwn_softc *sc)
109 {
110 struct r92c_softc *rs = sc->sc_priv;
111 uint32_t reg;
112 int ntries;
113
114 /* Wait for autoload done bit. */
115 for (ntries = 0; ntries < 1000; ntries++) {
116 if (rtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN)
117 break;
118 DELAY(5);
119 }
120 if (ntries == 1000) {
121 device_printf(sc->sc_dev,
122 "timeout waiting for chip autoload\n");
123 return (ETIMEDOUT);
124 }
125
126 /* Unlock ISO/CLK/Power control register. */
127 rtwn_write_1(sc, R92C_RSV_CTRL, 0);
128
129 if (rs->board_type != R92C_BOARD_TYPE_DONGLE) {
130 /* bt coex */
131 rtwn_setbits_4(sc, R92C_APS_FSMCO, 0,
132 R92C_APS_FSMCO_SOP_ABG |
133 R92C_APS_FSMCO_SOP_AMB |
134 R92C_APS_FSMCO_XOP_BTCK);
135 }
136
137 /* Move SPS into PWM mode. */
138 rtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b);
139
140 /* Set low byte to 0x0f, leave others unchanged. */
141 rtwn_write_1(sc, R92C_AFE_XTAL_CTRL, 0x0f);
142
143 /* TODO: check if we need this for 8188CE */
144 if (rs->board_type != R92C_BOARD_TYPE_DONGLE) {
145 /* bt coex */
146 /* XXX magic from linux */
147 rtwn_setbits_4(sc, R92C_AFE_XTAL_CTRL, 0x024800, 0);
148 }
149
150 rtwn_setbits_2(sc, R92C_SYS_ISO_CTRL, 0xff00,
151 R92C_SYS_ISO_CTRL_PWC_EV12V | R92C_SYS_ISO_CTRL_DIOR);
152
153 DELAY(200);
154
155 /* TODO: linux does additional btcoex stuff here */
156
157 /* Auto enable WLAN. */
158 rtwn_setbits_2(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_APFM_ONMAC);
159 for (ntries = 0; ntries < 1000; ntries++) {
160 if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
161 R92C_APS_FSMCO_APFM_ONMAC))
162 break;
163 DELAY(5);
164 }
165 if (ntries == 1000) {
166 device_printf(sc->sc_dev, "timeout waiting for MAC auto ON\n");
167 return (ETIMEDOUT);
168 }
169
170 /* Enable radio, GPIO and LED functions. */
171 rtwn_write_2(sc, R92C_APS_FSMCO,
172 R92C_APS_FSMCO_AFSM_PCIE |
173 R92C_APS_FSMCO_PDN_EN |
174 R92C_APS_FSMCO_PFM_ALDN);
175 /* Release RF digital isolation. */
176 rtwn_setbits_2(sc, R92C_SYS_ISO_CTRL, R92C_SYS_ISO_CTRL_DIOR, 0);
177
178 if (rs->chip & R92C_CHIP_92C)
179 rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x77);
180 else
181 rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x22);
182
183 rtwn_write_4(sc, R92C_INT_MIG, 0);
184
185 if (rs->board_type != R92C_BOARD_TYPE_DONGLE) {
186 /* bt coex */
187 /* XXX magic from linux */
188 rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL + 2, 0x02, 0);
189 }
190
191 rtwn_setbits_1(sc, R92C_GPIO_MUXCFG, R92C_GPIO_MUXCFG_RFKILL, 0);
192
193 reg = rtwn_read_1(sc, R92C_GPIO_IO_SEL);
194 if (!(reg & R92C_GPIO_IO_SEL_RFKILL)) {
195 device_printf(sc->sc_dev,
196 "radio is disabled by hardware switch\n");
197 /* XXX how driver will know when radio will be enabled? */
198 return (EPERM);
199 }
200
201 /* Initialize MAC. */
202 rtwn_setbits_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF, 0);
203 for (ntries = 0; ntries < 200; ntries++) {
204 if (!(rtwn_read_1(sc, R92C_APSD_CTRL) &
205 R92C_APSD_CTRL_OFF_STATUS))
206 break;
207 DELAY(500);
208 }
209 if (ntries == 200) {
210 device_printf(sc->sc_dev,
211 "timeout waiting for MAC initialization\n");
212 return (ETIMEDOUT);
213 }
214
215 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
216 rtwn_setbits_2(sc, R92C_CR, 0,
217 R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
218 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN |
219 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN |
220 ((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0));
221
222 rtwn_write_4(sc, R92C_MCUTST_1, 0x0);
223
224 return (0);
225 }
226
227 void
r92ce_power_off(struct rtwn_softc * sc)228 r92ce_power_off(struct rtwn_softc *sc)
229 {
230 #ifndef RTWN_WITHOUT_UCODE
231 struct r92c_softc *rs = sc->sc_priv;
232
233 /* Deinit C2H event handler. */
234 callout_stop(&rs->rs_c2h_report);
235 rs->rs_c2h_paused = 0;
236 rs->rs_c2h_pending = 0;
237 rs->rs_c2h_timeout = hz;
238 #endif
239
240 /* Stop hardware. */
241 /* Disable interrupts. */
242 rtwn_write_4(sc, R92C_HISR, 0);
243 rtwn_write_4(sc, R92C_HIMR, 0);
244
245 /* Stop hardware. */
246 rtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL);
247
248 /* Turn off RF. */
249 rtwn_write_1(sc, R92C_RF_CTRL, 0);
250
251 /* Reset BB state machine */
252 rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, 0, R92C_SYS_FUNC_EN_BB_GLB_RST);
253 rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BB_GLB_RST, 0);
254
255 /* Disable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
256 rtwn_setbits_2(sc, R92C_CR,
257 R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
258 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN |
259 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN |
260 R92C_CR_ENSEC,
261 0);
262
263 /* If firmware in ram code, do reset. */
264 #ifndef RTWN_WITHOUT_UCODE
265 if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL)
266 r92ce_fw_reset(sc, RTWN_FW_RESET_SHUTDOWN);
267 #endif
268
269 /* TODO: linux does additional btcoex stuff here */
270 rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0x80); /* linux magic number */
271 rtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); /* ditto */
272 rtwn_write_1(sc, R92C_AFE_XTAL_CTRL, 0x0e); /* different with btcoex */
273 rtwn_write_1(sc, R92C_RSV_CTRL, 0x0e);
274 rtwn_write_1(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_PDN_EN);
275 }
276
277 void
r92ce_init_ampdu(struct rtwn_softc * sc)278 r92ce_init_ampdu(struct rtwn_softc *sc)
279 {
280
281 /* Setup AMPDU aggregation. */
282 rtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */
283 rtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16);
284 }
285
286 void
r92ce_post_init(struct rtwn_softc * sc)287 r92ce_post_init(struct rtwn_softc *sc)
288 {
289 rtwn_write_2(sc, R92C_FWHW_TXQ_CTRL,
290 0x1f00 | R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW);
291
292 rtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff);
293
294 /* Perform LO and IQ calibrations. */
295 r92ce_iq_calib(sc);
296 /* Perform LC calibration. */
297 r92c_lc_calib(sc);
298
299 r92c_pa_bias_init(sc);
300
301 /* Fix for lower temperature. */
302 rtwn_write_1(sc, 0x15, 0xe9);
303
304 #ifndef RTWN_WITHOUT_UCODE
305 if (sc->sc_flags & RTWN_FW_LOADED) {
306 struct r92c_softc *rs = sc->sc_priv;
307
308 if (sc->sc_ratectl_sysctl == RTWN_RATECTL_FW) {
309 /* XXX TODO: fix (see comment in r92cu_init.c) */
310 sc->sc_ratectl = RTWN_RATECTL_NET80211;
311 } else
312 sc->sc_ratectl = sc->sc_ratectl_sysctl;
313
314 /* Start C2H event handling. */
315 callout_reset(&rs->rs_c2h_report, rs->rs_c2h_timeout,
316 r92c_handle_c2h_report, sc);
317 } else
318 #endif
319 sc->sc_ratectl = RTWN_RATECTL_NONE;
320 }
321