1 /* second CTRC functionality for GeForce cards */
2 /* Author:
3 Rudolf Cornelissen 11/2002-9/2009
4 */
5
6 #define MODULE_BIT 0x00020000
7
8 #include "nv_std.h"
9
10 /*
11 Enable/Disable interrupts. Just a wrapper around the
12 ioctl() to the kernel driver.
13 */
nv_crtc2_interrupt_enable(bool flag)14 status_t nv_crtc2_interrupt_enable(bool flag)
15 {
16 status_t result = B_OK;
17 nv_set_vblank_int svi;
18
19 if (si->ps.int_assigned)
20 {
21 /* set the magic number so the driver knows we're for real */
22 svi.magic = NV_PRIVATE_DATA_MAGIC;
23 svi.crtc = 1;
24 svi.do_it = flag;
25 /* contact driver and get a pointer to the registers and shared data */
26 result = ioctl(fd, NV_RUN_INTERRUPTS, &svi, sizeof(svi));
27 }
28
29 return result;
30 }
31
32 /* doing general fail-safe default setup here */
33 //fixme: this is a _very_ basic setup, and it's preliminary...
nv_crtc2_update_fifo()34 status_t nv_crtc2_update_fifo()
35 {
36 uint8 bytes_per_pixel = 1;
37 uint32 drain;
38
39 /* we are only using this on >>coldstarted<< cards which really need this */
40 //fixme: re-enable or remove after general user confirmation of behaviour...
41 if (/*(si->settings.usebios) ||*/ (si->ps.card_type != NV11)) return B_OK;
42
43 /* enable access to secondary head */
44 set_crtc_owner(1);
45
46 /* set CRTC FIFO low watermark according to memory drain */
47 switch(si->dm.space)
48 {
49 case B_CMAP8:
50 bytes_per_pixel = 1;
51 break;
52 case B_RGB15_LITTLE:
53 case B_RGB16_LITTLE:
54 bytes_per_pixel = 2;
55 break;
56 case B_RGB24_LITTLE:
57 bytes_per_pixel = 3;
58 break;
59 case B_RGB32_LITTLE:
60 bytes_per_pixel = 4;
61 break;
62 }
63 /* fixme:
64 * - I should probably include the refreshrate as well;
65 * - and the memory clocking speed, core clocking speed, RAM buswidth.. */
66 drain = si->dm.timing.h_display * si->dm.timing.v_display * bytes_per_pixel;
67
68 /* Doesn't work for other than 32bit space (yet?) */
69 if (si->dm.space != B_RGB32_LITTLE)
70 {
71 /* BIOS defaults */
72 CRTC2W(FIFO, 0x03);
73 CRTC2W(FIFO_LWM, 0x20);
74 LOG(4,("CRTC2: FIFO low-watermark set to $20, burst size 256 (BIOS defaults)\n"));
75 return B_OK;
76 }
77
78 if (drain > (((uint32)1280) * 1024 * 4))
79 {
80 /* set CRTC FIFO burst size for 'smaller' bursts */
81 CRTC2W(FIFO, 0x01);
82 /* Instruct CRTC to fetch new data 'earlier' */
83 CRTC2W(FIFO_LWM, 0x40);
84 LOG(4,("CRTC2: FIFO low-watermark set to $40, burst size 64\n"));
85 }
86 else
87 {
88 if (drain > (((uint32)1024) * 768 * 4))
89 {
90 /* BIOS default */
91 CRTC2W(FIFO, 0x02);
92 /* Instruct CRTC to fetch new data 'earlier' */
93 CRTC2W(FIFO_LWM, 0x40);
94 LOG(4,("CRTC2: FIFO low-watermark set to $40, burst size 128\n"));
95 }
96 else
97 {
98 /* BIOS defaults */
99 CRTC2W(FIFO, 0x03);
100 CRTC2W(FIFO_LWM, 0x20);
101 LOG(4,("CRTC2: FIFO low-watermark set to $20, burst size 256 (BIOS defaults)\n"));
102 }
103 }
104
105 return B_OK;
106 }
107
108 /* Adjust passed parameters to a valid mode line */
nv_crtc2_validate_timing(uint16 * hd_e,uint16 * hs_s,uint16 * hs_e,uint16 * ht,uint16 * vd_e,uint16 * vs_s,uint16 * vs_e,uint16 * vt)109 status_t nv_crtc2_validate_timing(
110 uint16 *hd_e,uint16 *hs_s,uint16 *hs_e,uint16 *ht,
111 uint16 *vd_e,uint16 *vs_s,uint16 *vs_e,uint16 *vt
112 )
113 {
114 /* horizontal */
115 /* make all parameters multiples of 8 */
116 *hd_e &= 0xfff8;
117 *hs_s &= 0xfff8;
118 *hs_e &= 0xfff8;
119 *ht &= 0xfff8;
120
121 /* confine to required number of bits, taking logic into account */
122 if (*hd_e > ((0x01ff - 2) << 3)) *hd_e = ((0x01ff - 2) << 3);
123 if (*hs_s > ((0x01ff - 1) << 3)) *hs_s = ((0x01ff - 1) << 3);
124 if (*hs_e > ( 0x01ff << 3)) *hs_e = ( 0x01ff << 3);
125 if (*ht > ((0x01ff + 5) << 3)) *ht = ((0x01ff + 5) << 3);
126
127 /* NOTE: keep horizontal timing at multiples of 8! */
128 /* confine to a reasonable width */
129 if (*hd_e < 640) *hd_e = 640;
130 if (*hd_e > 2048) *hd_e = 2048;
131
132 /* if hor. total does not leave room for a sensible sync pulse, increase it! */
133 if (*ht < (*hd_e + 80)) *ht = (*hd_e + 80);
134
135 /* if hor. total does not adhere to max. blanking pulse width, decrease it! */
136 if (*ht > (*hd_e + 0x3f8)) *ht = (*hd_e + 0x3f8);
137
138 /* make sure sync pulse is not during display */
139 if (*hs_e > (*ht - 8)) *hs_e = (*ht - 8);
140 if (*hs_s < (*hd_e + 8)) *hs_s = (*hd_e + 8);
141
142 /* correct sync pulse if it is too long:
143 * there are only 5 bits available to save this in the card registers! */
144 if (*hs_e > (*hs_s + 0xf8)) *hs_e = (*hs_s + 0xf8);
145
146 /*vertical*/
147 /* confine to required number of bits, taking logic into account */
148 //fixme if needed: on GeForce cards there are 12 instead of 11 bits...
149 if (*vd_e > (0x7ff - 2)) *vd_e = (0x7ff - 2);
150 if (*vs_s > (0x7ff - 1)) *vs_s = (0x7ff - 1);
151 if (*vs_e > 0x7ff ) *vs_e = 0x7ff ;
152 if (*vt > (0x7ff + 2)) *vt = (0x7ff + 2);
153
154 /* confine to a reasonable height */
155 if (*vd_e < 480) *vd_e = 480;
156 if (*vd_e > 1536) *vd_e = 1536;
157
158 /*if vertical total does not leave room for a sync pulse, increase it!*/
159 if (*vt < (*vd_e + 3)) *vt = (*vd_e + 3);
160
161 /* if vert. total does not adhere to max. blanking pulse width, decrease it! */
162 if (*vt > (*vd_e + 0xff)) *vt = (*vd_e + 0xff);
163
164 /* make sure sync pulse is not during display */
165 if (*vs_e > (*vt - 1)) *vs_e = (*vt - 1);
166 if (*vs_s < (*vd_e + 1)) *vs_s = (*vd_e + 1);
167
168 /* correct sync pulse if it is too long:
169 * there are only 4 bits available to save this in the card registers! */
170 if (*vs_e > (*vs_s + 0x0f)) *vs_e = (*vs_s + 0x0f);
171
172 return B_OK;
173 }
174
175 /*set a mode line - inputs are in pixels*/
nv_crtc2_set_timing(display_mode target)176 status_t nv_crtc2_set_timing(display_mode target)
177 {
178 uint8 temp;
179
180 uint32 htotal; /*total horizontal total VCLKs*/
181 uint32 hdisp_e; /*end of horizontal display (begins at 0)*/
182 uint32 hsync_s; /*begin of horizontal sync pulse*/
183 uint32 hsync_e; /*end of horizontal sync pulse*/
184 uint32 hblnk_s; /*begin horizontal blanking*/
185 uint32 hblnk_e; /*end horizontal blanking*/
186
187 uint32 vtotal; /*total vertical total scanlines*/
188 uint32 vdisp_e; /*end of vertical display*/
189 uint32 vsync_s; /*begin of vertical sync pulse*/
190 uint32 vsync_e; /*end of vertical sync pulse*/
191 uint32 vblnk_s; /*begin vertical blanking*/
192 uint32 vblnk_e; /*end vertical blanking*/
193
194 uint32 linecomp; /*split screen and vdisp_e interrupt*/
195
196 LOG(4,("CRTC2: setting timing\n"));
197
198 /* setup tuned internal modeline for flatpanel if connected and active */
199 /* notes:
200 * - the CRTC modeline must end earlier than the panel modeline to keep correct
201 * sync going;
202 * - if the CRTC modeline ends too soon, pixelnoise will occur in 8 (or so) pixel
203 * wide horizontal stripes. This can be observed earliest on fullscreen overlay,
204 * and if it gets worse, also normal desktop output will suffer. The stripes
205 * are mainly visible at the left of the screen, over the entire screen height. */
206 if (si->ps.monitors & CRTC2_TMDS)
207 {
208 LOG(2,("CRTC2: DFP active: tuning modeline\n"));
209
210 /* horizontal timing */
211 target.timing.h_sync_start =
212 ((uint16)((si->ps.p2_timing.h_sync_start / ((float)si->ps.p2_timing.h_display)) *
213 target.timing.h_display)) & 0xfff8;
214
215 target.timing.h_sync_end =
216 ((uint16)((si->ps.p2_timing.h_sync_end / ((float)si->ps.p2_timing.h_display)) *
217 target.timing.h_display)) & 0xfff8;
218
219 target.timing.h_total =
220 (((uint16)((si->ps.p2_timing.h_total / ((float)si->ps.p2_timing.h_display)) *
221 target.timing.h_display)) & 0xfff8) - 8;
222
223 /* in native mode the CRTC needs some extra time to keep synced correctly;
224 * OTOH the overlay unit distorts if we reserve too much time! */
225 if (target.timing.h_display == si->ps.p2_timing.h_display)
226 {
227 /* NV11 timing has different constraints than later cards */
228 if (si->ps.card_type == NV11)
229 target.timing.h_total -= 56;
230 else
231 /* confirmed NV34 with 1680x1050 panel */
232 target.timing.h_total -= 32;
233 }
234
235 /* assure sync pulse is at the correct timing position */
236 if (target.timing.h_sync_start == target.timing.h_display)
237 target.timing.h_sync_start += 8;
238 if (target.timing.h_sync_end == target.timing.h_total)
239 target.timing.h_sync_end -= 8;
240 /* assure we (still) have a sync pulse */
241 if (target.timing.h_sync_start == target.timing.h_sync_end) {
242 if (target.timing.h_sync_end < (target.timing.h_total - 8)) {
243 target.timing.h_sync_end += 8;
244 } else {
245 if (target.timing.h_sync_start > (target.timing.h_display + 8)) {
246 target.timing.h_sync_start -= 8;
247 } else {
248 LOG(2,("CRTC2: tuning modeline, not enough room for Hsync pulse, forcing it anyway..\n"));
249 target.timing.h_sync_start -= 8;
250 }
251 }
252 }
253
254 /* vertical timing */
255 target.timing.v_sync_start =
256 ((uint16)((si->ps.p2_timing.v_sync_start / ((float)si->ps.p2_timing.v_display)) *
257 target.timing.v_display));
258
259 target.timing.v_sync_end =
260 ((uint16)((si->ps.p2_timing.v_sync_end / ((float)si->ps.p2_timing.v_display)) *
261 target.timing.v_display));
262
263 target.timing.v_total =
264 ((uint16)((si->ps.p2_timing.v_total / ((float)si->ps.p2_timing.v_display)) *
265 target.timing.v_display)) - 1;
266
267 /* assure sync pulse is at the correct timing position */
268 if (target.timing.v_sync_start == target.timing.v_display)
269 target.timing.v_sync_start += 1;
270 if (target.timing.v_sync_end == target.timing.v_total)
271 target.timing.v_sync_end -= 1;
272 /* assure we (still) have a sync pulse */
273 if (target.timing.v_sync_start == target.timing.v_sync_end) {
274 if (target.timing.v_sync_end < (target.timing.v_total - 1)) {
275 target.timing.v_sync_end += 1;
276 } else {
277 if (target.timing.v_sync_start > (target.timing.v_display + 1)) {
278 target.timing.v_sync_start -= 1;
279 } else {
280 LOG(2,("CRTC2: tuning modeline, not enough room for Vsync pulse, forcing it anyway..\n"));
281 target.timing.v_sync_start -= 1;
282 }
283 }
284 }
285
286 /* disable GPU scaling testmode so automatic scaling will be done */
287 DAC2W(FP_DEBUG1, 0);
288 }
289
290 /* Modify parameters as required by standard VGA */
291 htotal = ((target.timing.h_total >> 3) - 5);
292 hdisp_e = ((target.timing.h_display >> 3) - 1);
293 hblnk_s = hdisp_e;
294 hblnk_e = (htotal + 4);
295 hsync_s = (target.timing.h_sync_start >> 3);
296 hsync_e = (target.timing.h_sync_end >> 3);
297
298 vtotal = target.timing.v_total - 2;
299 vdisp_e = target.timing.v_display - 1;
300 vblnk_s = vdisp_e;
301 vblnk_e = (vtotal + 1);
302 vsync_s = target.timing.v_sync_start;
303 vsync_e = target.timing.v_sync_end;
304
305 /* prevent memory adress counter from being reset (linecomp may not occur) */
306 linecomp = target.timing.v_display;
307
308 /* enable access to secondary head */
309 set_crtc_owner(1);
310
311 /* Note for laptop and DVI flatpanels:
312 * CRTC timing has a seperate set of registers from flatpanel timing.
313 * The flatpanel timing registers have scaling registers that are used to match
314 * these two modelines. */
315 {
316 LOG(4,("CRTC2: Setting full timing...\n"));
317
318 /* log the mode that will be set */
319 LOG(2,("CRTC2:\n\tHTOT:%x\n\tHDISPEND:%x\n\tHBLNKS:%x\n\tHBLNKE:%x\n\tHSYNCS:%x\n\tHSYNCE:%x\n\t",htotal,hdisp_e,hblnk_s,hblnk_e,hsync_s,hsync_e));
320 LOG(2,("VTOT:%x\n\tVDISPEND:%x\n\tVBLNKS:%x\n\tVBLNKE:%x\n\tVSYNCS:%x\n\tVSYNCE:%x\n",vtotal,vdisp_e,vblnk_s,vblnk_e,vsync_s,vsync_e));
321
322 /* actually program the card! */
323 /* unlock CRTC registers at index 0-7 */
324 CRTC2W(VSYNCE, (CRTC2R(VSYNCE) & 0x7f));
325 /* horizontal standard VGA regs */
326 CRTC2W(HTOTAL, (htotal & 0xff));
327 CRTC2W(HDISPE, (hdisp_e & 0xff));
328 CRTC2W(HBLANKS, (hblnk_s & 0xff));
329 /* also unlock vertical retrace registers in advance */
330 CRTC2W(HBLANKE, ((hblnk_e & 0x1f) | 0x80));
331 CRTC2W(HSYNCS, (hsync_s & 0xff));
332 CRTC2W(HSYNCE, ((hsync_e & 0x1f) | ((hblnk_e & 0x20) << 2)));
333
334 /* vertical standard VGA regs */
335 CRTC2W(VTOTAL, (vtotal & 0xff));
336 CRTC2W(OVERFLOW,
337 (
338 ((vtotal & 0x100) >> (8 - 0)) | ((vtotal & 0x200) >> (9 - 5)) |
339 ((vdisp_e & 0x100) >> (8 - 1)) | ((vdisp_e & 0x200) >> (9 - 6)) |
340 ((vsync_s & 0x100) >> (8 - 2)) | ((vsync_s & 0x200) >> (9 - 7)) |
341 ((vblnk_s & 0x100) >> (8 - 3)) | ((linecomp & 0x100) >> (8 - 4))
342 ));
343 CRTC2W(PRROWSCN, 0x00); /* not used */
344 CRTC2W(MAXSCLIN, (((vblnk_s & 0x200) >> (9 - 5)) | ((linecomp & 0x200) >> (9 - 6))));
345 CRTC2W(VSYNCS, (vsync_s & 0xff));
346 CRTC2W(VSYNCE, ((CRTC2R(VSYNCE) & 0xf0) | (vsync_e & 0x0f)));
347 CRTC2W(VDISPE, (vdisp_e & 0xff));
348 CRTC2W(VBLANKS, (vblnk_s & 0xff));
349 CRTC2W(VBLANKE, (vblnk_e & 0xff));
350 CRTC2W(LINECOMP, (linecomp & 0xff));
351
352 /* horizontal extended regs */
353 //fixme: we reset bit4. is this correct??
354 CRTC2W(HEB, (CRTC2R(HEB) & 0xe0) |
355 (
356 ((htotal & 0x100) >> (8 - 0)) |
357 ((hdisp_e & 0x100) >> (8 - 1)) |
358 ((hblnk_s & 0x100) >> (8 - 2)) |
359 ((hsync_s & 0x100) >> (8 - 3))
360 ));
361
362 /* (mostly) vertical extended regs */
363 CRTC2W(LSR,
364 (
365 ((vtotal & 0x400) >> (10 - 0)) |
366 ((vdisp_e & 0x400) >> (10 - 1)) |
367 ((vsync_s & 0x400) >> (10 - 2)) |
368 ((vblnk_s & 0x400) >> (10 - 3)) |
369 ((hblnk_e & 0x040) >> (6 - 4))
370 //fixme: we still miss one linecomp bit!?! is this it??
371 //| ((linecomp & 0x400) >> 3)
372 ));
373
374 /* more vertical extended regs */
375 CRTC2W(EXTRA,
376 (
377 ((vtotal & 0x800) >> (11 - 0)) |
378 ((vdisp_e & 0x800) >> (11 - 2)) |
379 ((vsync_s & 0x800) >> (11 - 4)) |
380 ((vblnk_s & 0x800) >> (11 - 6))
381 //fixme: do we miss another linecomp bit!?!
382 ));
383
384 /* setup 'large screen' mode */
385 if (target.timing.h_display >= 1280)
386 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0xfb));
387 else
388 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x04));
389
390 /* setup HSYNC & VSYNC polarity */
391 LOG(2,("CRTC2: sync polarity: "));
392 temp = NV_REG8(NV8_MISCR);
393 if (target.timing.flags & B_POSITIVE_HSYNC)
394 {
395 LOG(2,("H:pos "));
396 temp &= ~0x40;
397 }
398 else
399 {
400 LOG(2,("H:neg "));
401 temp |= 0x40;
402 }
403 if (target.timing.flags & B_POSITIVE_VSYNC)
404 {
405 LOG(2,("V:pos "));
406 temp &= ~0x80;
407 }
408 else
409 {
410 LOG(2,("V:neg "));
411 temp |= 0x80;
412 }
413 NV_REG8(NV8_MISCW) = temp;
414
415 LOG(2,(", MISC reg readback: $%02x\n", NV_REG8(NV8_MISCR)));
416 }
417
418 /* always disable interlaced operation */
419 /* (interlace is supported on upto and including NV10, NV15, and NV30 and up) */
420 CRTC2W(INTERLACE, 0xff);
421
422 /* disable CRTC slaved mode unless a panel is in use */
423 // fixme: this kills TVout when it was in use...
424 if (!(si->ps.monitors & CRTC2_TMDS)) CRTC2W(PIXEL, (CRTC2R(PIXEL) & 0x7f));
425
426 /* setup flatpanel if connected and active */
427 if (si->ps.monitors & CRTC2_TMDS)
428 {
429 uint32 iscale_x, iscale_y;
430
431 /* calculate inverse scaling factors used by hardware in 20.12 format */
432 iscale_x = (((1 << 12) * target.timing.h_display) / si->ps.p2_timing.h_display);
433 iscale_y = (((1 << 12) * target.timing.v_display) / si->ps.p2_timing.v_display);
434
435 /* unblock flatpanel timing programming (or something like that..) */
436 CRTC2W(FP_HTIMING, 0);
437 CRTC2W(FP_VTIMING, 0);
438 LOG(2,("CRTC2: FP_HTIMING reg readback: $%02x\n", CRTC2R(FP_HTIMING)));
439 LOG(2,("CRTC2: FP_VTIMING reg readback: $%02x\n", CRTC2R(FP_VTIMING)));
440
441 /* enable full width visibility on flatpanel */
442 DAC2W(FP_HVALID_S, 0);
443 DAC2W(FP_HVALID_E, (si->ps.p2_timing.h_display - 1));
444 /* enable full height visibility on flatpanel */
445 DAC2W(FP_VVALID_S, 0);
446 DAC2W(FP_VVALID_E, (si->ps.p2_timing.v_display - 1));
447
448 /* nVidia cards support upscaling except on ??? */
449 /* NV11 cards can upscale after all! */
450 if (0)//si->ps.card_type == NV11)
451 {
452 /* disable last fetched line limiting */
453 DAC2W(FP_DEBUG2, 0x00000000);
454 /* inform panel to scale if needed */
455 if ((iscale_x != (1 << 12)) || (iscale_y != (1 << 12)))
456 {
457 LOG(2,("CRTC2: DFP needs to do scaling\n"));
458 DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) | 0x00000100));
459 }
460 else
461 {
462 LOG(2,("CRTC2: no scaling for DFP needed\n"));
463 DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) & 0xfffffeff));
464 }
465 }
466 else
467 {
468 float dm_aspect;
469
470 LOG(2,("CRTC2: GPU scales for DFP if needed\n"));
471
472 /* calculate display mode aspect */
473 dm_aspect = (target.timing.h_display / ((float)target.timing.v_display));
474
475 /* limit last fetched line if vertical scaling is done */
476 if (iscale_y != (1 << 12))
477 DAC2W(FP_DEBUG2, ((1 << 28) | ((target.timing.v_display - 1) << 16)));
478 else
479 DAC2W(FP_DEBUG2, 0x00000000);
480
481 /* inform panel not to scale */
482 DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) & 0xfffffeff));
483
484 /* GPU scaling is automatically setup by hardware, so only modify this
485 * scalingfactor for non 4:3 (1.33) aspect panels;
486 * let's consider 1280x1024 1:33 aspect (it's 1.25 aspect actually!) */
487
488 /* correct for widescreen panels relative to mode...
489 * (so if panel is more widescreen than mode being set) */
490 /* BTW: known widescreen panels:
491 * 1280 x 800 (1.60),
492 * 1440 x 900 (1.60),
493 * 1680 x 1050 (1.60),
494 * 1920 x 1200 (1.60). */
495 /* known 4:3 aspect non-standard resolution panels:
496 * 1400 x 1050 (1.33). */
497 /* NOTE:
498 * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */
499 if ((iscale_x != (1 << 12)) && (si->ps.crtc2_screen.aspect > (dm_aspect + 0.10)))
500 {
501 uint16 diff;
502
503 LOG(2,("CRTC2: (relative) widescreen panel: tuning horizontal scaling\n"));
504
505 /* X-scaling should be the same as Y-scaling */
506 iscale_x = iscale_y;
507 /* enable testmode (b12) and program new X-scaling factor */
508 DAC2W(FP_DEBUG1, (((iscale_x >> 1) & 0x00000fff) | (1 << 12)));
509 /* center/cut-off left and right side of screen */
510 diff = ((si->ps.p2_timing.h_display -
511 ((target.timing.h_display * (1 << 12)) / iscale_x))
512 / 2);
513 DAC2W(FP_HVALID_S, diff);
514 DAC2W(FP_HVALID_E, ((si->ps.p2_timing.h_display - diff) - 1));
515 }
516 /* correct for portrait panels... */
517 /* NOTE:
518 * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */
519 if ((iscale_y != (1 << 12)) && (si->ps.crtc2_screen.aspect < (dm_aspect - 0.10)))
520 {
521 LOG(2,("CRTC2: (relative) portrait panel: should tune vertical scaling\n"));
522 /* fixme: implement if this kind of portrait panels exist on nVidia... */
523 }
524 }
525
526 /* do some logging.. */
527 LOG(2,("CRTC2: FP_HVALID_S reg readback: $%08x\n", DAC2R(FP_HVALID_S)));
528 LOG(2,("CRTC2: FP_HVALID_E reg readback: $%08x\n", DAC2R(FP_HVALID_E)));
529 LOG(2,("CRTC2: FP_VVALID_S reg readback: $%08x\n", DAC2R(FP_VVALID_S)));
530 LOG(2,("CRTC2: FP_VVALID_E reg readback: $%08x\n", DAC2R(FP_VVALID_E)));
531 LOG(2,("CRTC2: FP_DEBUG0 reg readback: $%08x\n", DAC2R(FP_DEBUG0)));
532 LOG(2,("CRTC2: FP_DEBUG1 reg readback: $%08x\n", DAC2R(FP_DEBUG1)));
533 LOG(2,("CRTC2: FP_DEBUG2 reg readback: $%08x\n", DAC2R(FP_DEBUG2)));
534 LOG(2,("CRTC2: FP_DEBUG3 reg readback: $%08x\n", DAC2R(FP_DEBUG3)));
535 LOG(2,("CRTC2: FP_TG_CTRL reg readback: $%08x\n", DAC2R(FP_TG_CTRL)));
536 }
537
538 return B_OK;
539 }
540
nv_crtc2_depth(int mode)541 status_t nv_crtc2_depth(int mode)
542 {
543 uint8 viddelay = 0;
544 uint32 genctrl = 0;
545
546 /* set VCLK scaling */
547 switch(mode)
548 {
549 case BPP8:
550 viddelay = 0x01;
551 /* genctrl b4 & b5 reset: 'direct mode' */
552 genctrl = 0x00101100;
553 break;
554 case BPP15:
555 viddelay = 0x02;
556 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */
557 genctrl = 0x00100130;
558 break;
559 case BPP16:
560 viddelay = 0x02;
561 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */
562 genctrl = 0x00101130;
563 break;
564 case BPP24:
565 viddelay = 0x03;
566 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */
567 genctrl = 0x00100130;
568 break;
569 case BPP32:
570 viddelay = 0x03;
571 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */
572 genctrl = 0x00101130;
573 break;
574 }
575 /* enable access to secondary head */
576 set_crtc_owner(1);
577
578 CRTC2W(PIXEL, ((CRTC2R(PIXEL) & 0xfc) | viddelay));
579 DAC2W(GENCTRL, genctrl);
580
581 return B_OK;
582 }
583
nv_crtc2_dpms(bool display,bool h,bool v,bool do_panel)584 status_t nv_crtc2_dpms(bool display, bool h, bool v, bool do_panel)
585 {
586 uint8 temp;
587 char msg[100];
588
589 strlcpy(msg, "CRTC2: setting DPMS: ", sizeof(msg));
590
591 /* enable access to secondary head */
592 set_crtc_owner(1);
593
594 /* start synchronous reset: required before turning screen off! */
595 SEQW(RESET, 0x01);
596
597 temp = SEQR(CLKMODE);
598 if (display)
599 {
600 /* turn screen on */
601 SEQW(CLKMODE, (temp & ~0x20));
602
603 /* end synchronous reset because display should be enabled */
604 SEQW(RESET, 0x03);
605
606 if (do_panel && (si->ps.monitors & CRTC2_TMDS))
607 {
608 if (!si->ps.laptop)
609 {
610 /* restore original panelsync and panel-enable */
611 uint32 panelsync = 0x00000000;
612 if(si->ps.p2_timing.flags & B_POSITIVE_VSYNC) panelsync |= 0x00000001;
613 if(si->ps.p2_timing.flags & B_POSITIVE_HSYNC) panelsync |= 0x00000010;
614 /* display enable polarity (not an official flag) */
615 if(si->ps.p2_timing.flags & B_BLANK_PEDESTAL) panelsync |= 0x10000000;
616 DAC2W(FP_TG_CTRL, ((DAC2R(FP_TG_CTRL) & 0xcfffffcc) | panelsync));
617
618 //fixme?: looks like we don't need this after all:
619 /* powerup both LVDS (laptop panellink) and TMDS (DVI panellink)
620 * internal transmitters... */
621 /* note:
622 * the powerbits in this register are hardwired to the DVI connectors,
623 * instead of to the DACs! (confirmed NV34) */
624 //fixme...
625 //DAC2W(FP_DEBUG0, (DAC2R(FP_DEBUG0) & 0xcfffffff));
626 /* ... and powerup external TMDS transmitter if it exists */
627 /* (confirmed OK on NV28 and NV34) */
628 //CRTC2W(0x59, (CRTC2R(0x59) | 0x01));
629
630 strlcat(msg, "(panel-)", sizeof(msg));
631 }
632 else
633 {
634 //fixme: see if LVDS head can be determined with two panels there...
635 if (!(si->ps.monitors & CRTC1_TMDS) && (si->ps.card_type != NV11))
636 {
637 /* b2 = 0 = enable laptop panel backlight */
638 /* note: this seems to be a write-only register. */
639 NV_REG32(NV32_LVDS_PWR) = 0x00000003;
640
641 strlcat(msg, "(panel-)", sizeof(msg));
642 }
643 }
644 }
645
646 strlcat(msg, "display on, ", sizeof(msg));
647 }
648 else
649 {
650 /* turn screen off */
651 SEQW(CLKMODE, (temp | 0x20));
652
653 if (do_panel && (si->ps.monitors & CRTC2_TMDS))
654 {
655 if (!si->ps.laptop)
656 {
657 /* shutoff panelsync and disable panel */
658 DAC2W(FP_TG_CTRL, ((DAC2R(FP_TG_CTRL) & 0xcfffffcc) | 0x20000022));
659
660 //fixme?: looks like we don't need this after all:
661 /* powerdown both LVDS (laptop panellink) and TMDS (DVI panellink)
662 * internal transmitters... */
663 /* note:
664 * the powerbits in this register are hardwired to the DVI connectors,
665 * instead of to the DACs! (confirmed NV34) */
666 //fixme...
667 //DAC2W(FP_DEBUG0, (DAC2R(FP_DEBUG0) | 0x30000000));
668 /* ... and powerdown external TMDS transmitter if it exists */
669 /* (confirmed OK on NV28 and NV34) */
670 //CRTC2W(0x59, (CRTC2R(0x59) & 0xfe));
671
672 strlcat(msg, "(panel-)", sizeof(msg));
673 }
674 else
675 {
676 //fixme: see if LVDS head can be determined with two panels there...
677 if (!(si->ps.monitors & CRTC1_TMDS) && (si->ps.card_type != NV11))
678 {
679 /* b2 = 1 = disable laptop panel backlight */
680 /* note: this seems to be a write-only register. */
681 NV_REG32(NV32_LVDS_PWR) = 0x00000007;
682
683 strlcat(msg, "(panel-)", sizeof(msg));
684 }
685 }
686 }
687
688 strlcat(msg, "display off, ", sizeof(msg));
689 }
690
691 if (h)
692 {
693 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0x7f));
694 strlcat(msg, "hsync enabled, ", sizeof(msg));
695 }
696 else
697 {
698 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x80));
699 strlcat(msg, "hsync disabled, ", sizeof(msg));
700 }
701 if (v)
702 {
703 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0xbf));
704 strlcat(msg, "vsync enabled\n", sizeof(msg));
705 }
706 else
707 {
708 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x40));
709 strlcat(msg, "vsync disabled\n", sizeof(msg));
710 }
711
712 LOG(4, (msg));
713
714 return B_OK;
715 }
716
nv_crtc2_set_display_pitch()717 status_t nv_crtc2_set_display_pitch()
718 {
719 uint32 offset;
720
721 LOG(4,("CRTC2: setting card pitch (offset between lines)\n"));
722
723 /* figure out offset value hardware needs */
724 offset = si->fbc.bytes_per_row / 8;
725
726 LOG(2,("CRTC2: offset register set to: $%04x\n", offset));
727
728 /* enable access to secondary head */
729 set_crtc_owner(1);
730
731 /* program the card */
732 CRTC2W(PITCHL, (offset & 0x00ff));
733 CRTC2W(REPAINT0, ((CRTC2R(REPAINT0) & 0x1f) | ((offset & 0x0700) >> 3)));
734
735 return B_OK;
736 }
737
nv_crtc2_set_display_start(uint32 startadd,uint8 bpp)738 status_t nv_crtc2_set_display_start(uint32 startadd,uint8 bpp)
739 {
740 uint32 timeout = 0;
741
742 LOG(4,("CRTC2: setting card RAM to be displayed bpp %d\n", bpp));
743
744 LOG(2,("CRTC2: startadd: $%08x\n", startadd));
745 LOG(2,("CRTC2: frameRAM: $%08x\n", si->framebuffer));
746 LOG(2,("CRTC2: framebuffer: $%08x\n", si->fbc.frame_buffer));
747
748 /* we might have no retraces during setmode! */
749 /* wait 25mS max. for retrace to occur (refresh > 40Hz) */
750 while (((NV_REG32(NV32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) &&
751 (timeout < (25000/10)))
752 {
753 /* don't snooze much longer or retrace might get missed! */
754 snooze(10);
755 timeout++;
756 }
757
758 /* enable access to secondary head */
759 set_crtc_owner(1);
760
761 /* upto 4Gb RAM adressing: must be used on NV10 and later! */
762 /* NOTE:
763 * While this register also exists on pre-NV10 cards, it will
764 * wrap-around at 16Mb boundaries!! */
765
766 /* 30bit adress in 32bit words */
767 NV_REG32(NV32_NV10FB2STADD32) = (startadd & 0xfffffffc);
768
769 /* set byte adress: (b0 - 1) */
770 ATB2W(HORPIXPAN, ((startadd & 0x00000003) << 1));
771
772 return B_OK;
773 }
774
nv_crtc2_cursor_init()775 status_t nv_crtc2_cursor_init()
776 {
777 int i;
778 vuint32 * fb;
779 /* cursor bitmap will be stored at the start of the framebuffer */
780 const uint32 curadd = 0;
781
782 /* enable access to secondary head */
783 set_crtc_owner(1);
784
785 /* set cursor bitmap adress ... */
786 if (si->ps.laptop)
787 {
788 /* must be used this way on pre-NV10 and on all 'Go' cards! */
789
790 /* cursorbitmap must start on 2Kbyte boundary: */
791 /* set adress bit11-16, and set 'no doublescan' (registerbit 1 = 0) */
792 CRTC2W(CURCTL0, ((curadd & 0x0001f800) >> 9));
793 /* set adress bit17-23, and set graphics mode cursor(?) (registerbit 7 = 1) */
794 CRTC2W(CURCTL1, (((curadd & 0x00fe0000) >> 17) | 0x80));
795 /* set adress bit24-31 */
796 CRTC2W(CURCTL2, ((curadd & 0xff000000) >> 24));
797 }
798 else
799 {
800 /* upto 4Gb RAM adressing:
801 * can be used on NV10 and later (except for 'Go' cards)! */
802 /* NOTE:
803 * This register does not exist on pre-NV10 and 'Go' cards. */
804
805 /* cursorbitmap must still start on 2Kbyte boundary: */
806 NV_REG32(NV32_NV10CUR2ADD32) = (curadd & 0xfffff800);
807 }
808
809 /* set cursor colour: not needed because of direct nature of cursor bitmap. */
810
811 /*clear cursor*/
812 fb = (vuint32 *) si->framebuffer + curadd;
813 for (i=0;i<(2048/4);i++)
814 {
815 fb[i]=0;
816 }
817
818 /* select 32x32 pixel, 16bit color cursorbitmap, no doublescan */
819 NV_REG32(NV32_2CURCONF) = 0x02000100;
820
821 /* activate hardware-sync between cursor updates and vertical retrace */
822 DAC2W(NV10_CURSYNC, (DAC2R(NV10_CURSYNC) | 0x02000000));
823
824 /* activate hardware cursor */
825 nv_crtc2_cursor_show();
826
827 return B_OK;
828 }
829
nv_crtc2_cursor_show()830 status_t nv_crtc2_cursor_show()
831 {
832 LOG(4,("CRTC2: enabling cursor\n"));
833
834 /* enable access to secondary head */
835 set_crtc_owner(1);
836
837 /* b0 = 1 enables cursor */
838 CRTC2W(CURCTL0, (CRTC2R(CURCTL0) | 0x01));
839
840 /* workaround for hardware bug confirmed existing on NV43:
841 * Cursor visibility is not updated without a position update if its hardware
842 * retrace sync is enabled. */
843 if (si->ps.card_arch == NV40A) DAC2W(CURPOS, (DAC2R(CURPOS)));
844
845 return B_OK;
846 }
847
nv_crtc2_cursor_hide()848 status_t nv_crtc2_cursor_hide()
849 {
850 LOG(4,("CRTC2: disabling cursor\n"));
851
852 /* enable access to secondary head */
853 set_crtc_owner(1);
854
855 /* b0 = 0 disables cursor */
856 CRTC2W(CURCTL0, (CRTC2R(CURCTL0) & 0xfe));
857
858 /* workaround for hardware bug confirmed existing on NV43:
859 * Cursor visibility is not updated without a position update if its hardware
860 * retrace sync is enabled. */
861 if (si->ps.card_arch == NV40A) DAC2W(CURPOS, (DAC2R(CURPOS)));
862
863 return B_OK;
864 }
865
866 /*set up cursor shape*/
nv_crtc2_cursor_define(uint8 * andMask,uint8 * xorMask)867 status_t nv_crtc2_cursor_define(uint8* andMask,uint8* xorMask)
868 {
869 int x, y;
870 uint8 b;
871 vuint16 *cursor;
872 uint16 pixel;
873
874 /* get a pointer to the cursor */
875 cursor = (vuint16*) si->framebuffer;
876
877 /* draw the cursor */
878 /* (Nvidia cards have a RGB15 direct color cursor bitmap, bit #16 is transparancy) */
879 for (y = 0; y < 16; y++)
880 {
881 b = 0x80;
882 for (x = 0; x < 8; x++)
883 {
884 /* preset transparant */
885 pixel = 0x0000;
886 /* set white if requested */
887 if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff;
888 /* set black if requested */
889 if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000;
890 /* set invert if requested */
891 if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff;
892 /* place the pixel in the bitmap */
893 cursor[x + (y * 32)] = pixel;
894 b >>= 1;
895 }
896 xorMask++;
897 andMask++;
898 b = 0x80;
899 for (; x < 16; x++)
900 {
901 /* preset transparant */
902 pixel = 0x0000;
903 /* set white if requested */
904 if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff;
905 /* set black if requested */
906 if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000;
907 /* set invert if requested */
908 if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff;
909 /* place the pixel in the bitmap */
910 cursor[x + (y * 32)] = pixel;
911 b >>= 1;
912 }
913 xorMask++;
914 andMask++;
915 }
916
917 return B_OK;
918 }
919
920 /* position the cursor */
nv_crtc2_cursor_position(uint16 x,uint16 y)921 status_t nv_crtc2_cursor_position(uint16 x, uint16 y)
922 {
923 /* the cursor position is updated during retrace by card hardware */
924
925 /* update cursorposition */
926 DAC2W(CURPOS, ((x & 0x0fff) | ((y & 0x0fff) << 16)));
927
928 return B_OK;
929 }
930
nv_crtc2_stop_tvout(void)931 status_t nv_crtc2_stop_tvout(void)
932 {
933 uint16 cnt;
934
935 LOG(4,("CRTC2: stopping TV output\n"));
936
937 /* enable access to secondary head */
938 set_crtc_owner(1);
939
940 /* just to be sure Vsync is _really_ enabled */
941 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0xbf));
942
943 /* wait for one image to be generated to make sure VGA has kicked in and is
944 * running OK before continuing...
945 * (Kicking in will fail often if we do not wait here) */
946 /* Note:
947 * The used CRTC's Vsync is required to be enabled here. The DPMS state
948 * programming in the driver makes sure this is the case.
949 * (except for driver startup: see nv_general.c.) */
950
951 /* make sure we are 'in' active VGA picture: wait with timeout! */
952 cnt = 1;
953 while ((NV_REG8(NV8_INSTAT1) & 0x08) && cnt)
954 {
955 snooze(1);
956 cnt++;
957 }
958 /* wait for next vertical retrace start on VGA: wait with timeout! */
959 cnt = 1;
960 while ((!(NV_REG8(NV8_INSTAT1) & 0x08)) && cnt)
961 {
962 snooze(1);
963 cnt++;
964 }
965 /* now wait until we are 'in' active VGA picture again: wait with timeout! */
966 cnt = 1;
967 while ((NV_REG8(NV8_INSTAT1) & 0x08) && cnt)
968 {
969 snooze(1);
970 cnt++;
971 }
972
973 /* set CRTC to master mode (b7 = 0) if it wasn't slaved for a panel before */
974 if (!(si->ps.slaved_tmds2)) CRTC2W(PIXEL, (CRTC2R(PIXEL) & 0x03));
975
976 /* CAUTION:
977 * On old cards, PLLSEL (and TV_SETUP?) cannot be read (sometimes?), but
978 * write actions do succeed ...
979 * This is confirmed for both ISA and PCI access, on NV04 and NV11. */
980
981 /* setup TVencoder connection */
982 /* b1-0 = %00: encoder type is SLAVE;
983 * b24 = 1: VIP datapos is b0-7 */
984 //fixme if needed: setup completely instead of relying on pre-init by BIOS..
985 //(it seems to work OK on NV04 and NV11 although read reg. doesn't seem to work)
986 DAC2W(TV_SETUP, ((DAC2R(TV_SETUP) & ~0x00000003) | 0x01000000));
987
988 /* tell GPU to use pixelclock from internal source instead of using TVencoder */
989 DACW(PLLSEL, 0x30000f00);
990
991 /* HTOTAL, VTOTAL and OVERFLOW return their default CRTC use, instead of
992 * H, V-low and V-high 'shadow' counters(?)(b0, 4 and 6 = 0) (b7 use = unknown) */
993 CRTC2W(TREG, 0x00);
994
995 /* select panel encoder, not TV encoder if needed (b0 = 1).
996 * Note:
997 * Both are devices (often) using the CRTC in slaved mode. */
998 if (si->ps.slaved_tmds2) CRTC2W(LCD, (CRTC2R(LCD) | 0x01));
999
1000 return B_OK;
1001 }
1002
nv_crtc2_start_tvout(void)1003 status_t nv_crtc2_start_tvout(void)
1004 {
1005 LOG(4,("CRTC2: starting TV output\n"));
1006
1007 /* switch TV encoder to CRTC2 */
1008 NV_REG32(NV32_FUNCSEL) &= ~0x00000100;
1009 NV_REG32(NV32_2FUNCSEL) |= 0x00000100;
1010
1011 /* enable access to secondary head */
1012 set_crtc_owner(1);
1013
1014 /* CAUTION:
1015 * On old cards, PLLSEL (and TV_SETUP?) cannot be read (sometimes?), but
1016 * write actions do succeed ...
1017 * This is confirmed for both ISA and PCI access, on NV04 and NV11. */
1018
1019 /* setup TVencoder connection */
1020 /* b1-0 = %01: encoder type is MASTER;
1021 * b24 = 1: VIP datapos is b0-7 */
1022 //fixme if needed: setup completely instead of relying on pre-init by BIOS..
1023 //(it seems to work OK on NV04 and NV11 although read reg. doesn't seem to work)
1024 DAC2W(TV_SETUP, ((DAC2R(TV_SETUP) & ~0x00000002) | 0x01000001));
1025
1026 /* tell GPU to use pixelclock from TVencoder instead of using internal source */
1027 /* (nessecary or display will 'shiver' on both TV and VGA.) */
1028 DACW(PLLSEL, 0x100c0f00);
1029
1030 /* Set overscan color to 'black' */
1031 /* note:
1032 * Change this instruction for a visible overscan color if you're trying to
1033 * center the output on TV. Use it as a guide-'line' then ;-) */
1034 ATB2W(OSCANCOLOR, 0x00);
1035
1036 /* set CRTC to slaved mode (b7 = 1) and clear TVadjust (b3-5 = %000) */
1037 CRTC2W(PIXEL, ((CRTC2R(PIXEL) & 0xc7) | 0x80));
1038 /* select TV encoder, not panel encoder (b0 = 0).
1039 * Note:
1040 * Both are devices (often) using the CRTC in slaved mode. */
1041 CRTC2W(LCD, (CRTC2R(LCD) & 0xfe));
1042
1043 /* HTOTAL, VTOTAL and OVERFLOW return their default CRTC use, instead of
1044 * H, V-low and V-high 'shadow' counters(?)(b0, 4 and 6 = 0) (b7 use = unknown) */
1045 CRTC2W(TREG, 0x80);
1046
1047 return B_OK;
1048 }
1049