1 /* 2 Copyright (c) 2002, Thomas Kurschel 3 4 5 Part of Radeon accelerant 6 7 Interface between kernel driver and accelerant 8 */ 9 10 11 #ifndef _RADEON_INTERFACE_H 12 #define _RADEON_INTERFACE_H 13 14 #include <Accelerant.h> 15 #include <Drivers.h> 16 #include <PCI.h> 17 #include <OS.h> 18 #include "video_overlay.h" 19 #include "benaphore.h" 20 #include "ddc.h" 21 22 // magic code for ioctls 23 // changed from TKRA to TKR1 for RADEON_WAITFORFIFO ioctl 24 // changed from TKRA to TKR2 for VIP FIFO ioctls 25 #define RADEON_PRIVATE_DATA_MAGIC 'TKR2' 26 27 #define MAX_RADEON_DEVICE_NAME_LENGTH MAXPATHLEN 28 29 // list ioctls 30 enum { 31 RADEON_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 32 33 RADEON_DEVICE_NAME, 34 RADEON_GET_LOG_SIZE, 35 RADEON_GET_LOG_DATA, 36 RADEON_ALLOC_MEM, 37 RADEON_FREE_MEM, 38 39 RADEON_WAITFORIDLE, 40 RADEON_WAITFORFIFO, 41 RADEON_RESETENGINE, 42 RADEON_VIPREAD, 43 RADEON_VIPWRITE, 44 RADEON_VIPFIFOREAD, 45 RADEON_VIPFIFOWRITE, 46 RADEON_FINDVIPDEVICE, 47 RADEON_VIPRESET, 48 49 RADEON_WAIT_FOR_CAP_IRQ, 50 RADEON_DMACOPY, 51 }; 52 53 54 // number of indirect buffers 55 // see CP.c for this magic number 56 #define NUM_INDIRECT_BUFFERS 253 57 // size of an indirect buffer in dwords; 58 // as hardware wants buffers to be 4k aligned and as we store all 59 // buffers in one chunk, the size per buffer in bytes must be a multiple of 4k 60 #define INDIRECT_BUFFER_SIZE (4096/4) 61 62 typedef struct { 63 uint32 loginfo; 64 uint32 logflow; 65 uint32 logerror; 66 bool switchhead; 67 bool force_lcd; 68 bool dynamic_clocks; // power saving / management for mobility chips 69 bool force_pci; 70 bool unhide_fastwrites; 71 bool force_acc_dma; // one or the other 72 bool force_acc_mmio; // one or the other 73 bool acc_writeback; 74 } radeon_settings; 75 76 // type of memory 77 typedef enum { 78 mt_local, // local graphics memory 79 mt_PCI, // PCI memory (read: fully cachable) 80 mt_AGP, // AGP memory (read: not cachable; currently not supported) 81 mt_nonlocal, // non-local graphics memory (alias to one of the 82 // previously defined types, see si->nonlocal_type) 83 84 mt_last = mt_nonlocal 85 } memory_type_e; 86 87 // list of multi-monitor modes 88 typedef enum { 89 mm_none, // use one display only 90 mm_combine, // combine displays to larger workspace 91 mm_clone, // clone workspace, all displays show the 92 // same but have independant timing 93 mm_mirror // mirror heads (as used by Laptop) - not implemented yet 94 } multi_mode_e; 95 96 97 // displays devices; 98 // this must be a bit field as multiple devices may be connected to one CRTC 99 typedef enum { 100 dd_none = 0, 101 dd_tv_crt = 1, // CRT on TV-DAC, i.e. on DVI port 102 dd_crt = 2, // CRT on CRT-DAC, i.e. VGA port 103 dd_lvds = 4, // laptop flap panel 104 dd_dvi = 8, // DVI on primary port (i.e. standard DVI connector) 105 dd_ctv = 16, // composite TV on TV-DAC 106 dd_stv = 32, // S-Video out on TV-DAC 107 108 // the following connectors/devices are not supported 109 dd_dvi_ext = 64 // external DVI (only provided by few models) 110 } display_device_e; 111 112 typedef enum 113 { 114 ddc_none_detected, 115 ddc_monid, 116 ddc_dvi, 117 ddc_vga, 118 ddc_crt2 119 } radeon_ddc_type; 120 121 typedef enum 122 { 123 mt_unknown = -1, 124 mt_none = 0, 125 mt_crt = 1, 126 mt_lcd = 2, 127 mt_dfp = 3, 128 mt_ctv = 4, 129 mt_stv = 5 130 } radeon_monitor_type; 131 132 typedef enum 133 { 134 connector_none, 135 connector_proprietary, 136 connector_crt, 137 connector_dvi_i, 138 connector_dvi_d, 139 connector_ctv, 140 connector_stv, 141 connector_unsupported, 142 143 connector_none_atom = 0, 144 connector_vga_atom, 145 connector_dvi_i_atom, 146 connector_dvi_d_atom, 147 connector_dvi_a_atom, 148 connector_stv_atom, 149 connector_ctv_atom, 150 connector_lvds_atom, 151 connector_digital_atom, 152 connector_unsupported_atom 153 } radeon_connector_type; 154 155 typedef enum 156 { 157 dac_unknown = -1, 158 dac_primary = 0, 159 dac_tvdac = 1 160 } radeon_dac_type; 161 162 typedef enum 163 { 164 tmds_unknown = -1, 165 tmds_int = 0, 166 tmds_ext = 1 167 } radeon_tmds_type; 168 169 typedef struct 170 { 171 radeon_ddc_type ddc_type; 172 radeon_dac_type dac_type; 173 radeon_tmds_type tmds_type; 174 radeon_connector_type connector_type; 175 radeon_monitor_type mon_type; 176 edid1_info edid; 177 bool edid_valid; 178 } radeon_connector; 179 180 typedef struct 181 { 182 bool has_secondary; 183 184 /* 185 * The next two are used to make sure CRTC2 is restored before CRTC_EXT, 186 * otherwise it could lead to blank screens. 187 */ 188 bool is_secondary_restored; 189 bool restore_primary; 190 191 int mon_type1; 192 int mon_type2; 193 194 bool reversed_DAC; /* TVDAC used as primary dac */ 195 bool reversed_TMDS; /* DDC_DVI is used for external TMDS */ 196 197 radeon_connector port_info[2]; 198 } disp_entity, *ptr_disp_entity; 199 200 201 // type of ASIC 202 typedef enum { 203 rt_r100, // original Radeon 204 rt_rv100, // original VE version 205 rt_rs100, // IGP 320M 206 rt_rv200, // Radeon 7500 207 rt_rs200, // IGP 330M/340M/350M 208 rt_r200, // Radeon 8500/9100 209 rt_rv250, // Radeon 9000 210 rt_rs300, // IGP rs300 211 rt_rv280, // Radeon 9200 212 // from here on, r300 and up must be located as ATI modified the 213 // PLL design and the PLL code only tests for >= rt_r300 214 rt_r300, // Radeon 9700 215 rt_r350, // Radeon 9800 216 rt_rv350, // Radeon 9600 217 rt_rv380, // X600 218 rt_r420 // X800 219 } radeon_type; 220 221 #define IS_RV100_VARIANT ( \ 222 (ai->si->asic == rt_rv100) || \ 223 (ai->si->asic == rt_rv200) || \ 224 (ai->si->asic == rt_rs100) || \ 225 (ai->si->asic == rt_rs200) || \ 226 (ai->si->asic == rt_rv250) || \ 227 (ai->si->asic == rt_rv280) || \ 228 (ai->si->asic == rt_rs300)) 229 230 #define IS_DI_R300_VARIANT ( \ 231 (di->asic == rt_r300) || \ 232 (di->asic == rt_r350) || \ 233 (di->asic == rt_rv350) || \ 234 (di->asic == rt_rv380) || \ 235 (di->asic == rt_r420)) 236 237 #define IS_R300_VARIANT ( \ 238 (ai->si->asic == rt_r300) || \ 239 (ai->si->asic == rt_r350) || \ 240 (ai->si->asic == rt_rv350) || \ 241 (ai->si->asic == rt_rv380) || \ 242 (ai->si->asic == rt_r420)) 243 244 // TV standard 245 typedef enum { 246 ts_off, 247 ts_ntsc, 248 ts_pal_bdghi, 249 ts_pal_m, 250 ts_pal_nc, 251 ts_scart_pal, 252 ts_pal_60, 253 ts_max = ts_pal_60 254 } tv_standard_e; 255 256 257 // type of TV-Chip 258 typedef enum { 259 tc_none, 260 tc_external_rt1, // external Rage Theatre 261 tc_internal_rt1, // internal version 1 262 tc_internal_rt2, // internal version 2 263 } tv_chip_type; 264 265 266 // info about cursor 267 typedef struct { 268 uint8* data; // pointer to framebuffer containing cursor image 269 uint16 hot_x; 270 uint16 hot_y; 271 uint16 x; 272 uint16 y; 273 uint16 width; 274 uint16 height; 275 uint32 mem_handle; // memory handle 276 uint32 fb_offset; // offset in frame buffer 277 bool is_visible; // official flag whether cursor is visible 278 } cursor_info; 279 280 281 // info about flat panel connected to LVDS or DVI port 282 typedef struct { 283 uint panel_pwr_delay; 284 uint panel_xres, panel_yres; 285 286 uint h_blank, h_over_plus, h_sync_width; 287 uint v_blank, v_over_plus, v_sync_width; 288 uint dot_clock; // in kHz (this is BeOS like, ATI uses 10 kHz steps!) 289 290 bool is_fp2; // true, if second flat panel 291 // display_type_e disp_type; 292 uint16 ref_div; 293 uint8 post_div; 294 uint8 feedback_div; 295 bool fixed_dividers; 296 297 uint64 h_ratio; // current stretch ratio, needed for overlays 298 uint64 v_ratio; // (mode_res/native_res; 32.32) 299 } fp_info; 300 301 302 // crtc info 303 typedef struct { 304 //bool is_crtc2; // true, if crtc2 305 int8 flatpanel_port; // linked flat panel port (-1 if none) 306 bool cursor_on_screen; // cursor is visible on this head 307 int crtc_idx; // index of CRTC 308 display_device_e active_displays; // currently driven displays 309 display_device_e chosen_displays; // displays to be driven after next mode switch 310 sem_id vblank; // vertical blank interrupt semaphore 311 uint32 rel_x, rel_y; // relative position in multi-monitor mode 312 display_mode mode; // display mode of this head 313 } crtc_info; 314 315 316 // info about PLLs on graphics card as retrieved from BIOS 317 // all values are in 10kHz 318 typedef struct { 319 uint32 max_pll_freq; // maximum PLL output frequency 320 uint32 min_pll_freq; // minimum PLL output frequency 321 uint32 xclk; // core frequency 322 uint32 ref_div; // default reference divider 323 uint32 ref_freq; // PLL reference frequency 324 } general_pll_info; 325 326 327 // mapping of pll divider code to actual divider value 328 typedef struct { 329 uint8 divider; // divider 330 uint8 code; // code as used in register 331 } pll_divider_map; 332 333 334 // info about a PLL 335 // all values are in 10 kHz 336 typedef struct { 337 pll_divider_map *post_divs; // list of possible post dividers 338 pll_divider_map *extra_post_divs; // list of possible extra post dividers 339 uint32 ref_freq; // reference frequency 340 uint32 vco_min, vco_max; // VCO frequency range 341 uint32 min_ref_div, max_ref_div; // reference divider range 342 uint32 pll_in_min, pll_in_max; // PLL input frequency range 343 uint32 extra_feedback_div; // hardwired divider before feedback divider 344 uint32 min_feedback_div, max_feedback_div; // feedback divider range 345 uint32 best_vco; // preferred VCO frequency (0 for don't care) 346 } pll_info; 347 348 // info for ext tmds pll 349 typedef struct { 350 uint32 freq; 351 uint32 value; 352 } tmds_pll_info; 353 354 // one overlay buffer 355 typedef struct overlay_buffer_node { 356 struct overlay_buffer_node *next, *prev; 357 uint32 mem_handle; 358 uint32 mem_offset; 359 uint ati_space; // colour space according to ATI 360 uint test_reg; // content of test reg 361 overlay_buffer buffer; 362 } overlay_buffer_node; 363 364 365 // info about active overlay 366 typedef struct { 367 overlay_token ot; 368 overlay_buffer ob; 369 overlay_window ow; 370 overlay_view ov; 371 uint16 h_display_start; 372 uint16 v_display_start; 373 374 overlay_buffer_node *on; // current buffer 375 overlay_buffer_node *prev_on; // previous buffer (for temporal deinterlace, currently unused) 376 int crtc_idx; // crtc where the overlay is shown on 377 uint32 rel_offset; // offset of overlay source due to clipping 378 } overlay_info; 379 380 381 // each accelerant gets one "virtual card", i.e. you 382 // can have independant accelerants for each head 383 // (this is an ongoing project ;) 384 typedef struct { 385 uint32 id; // identifier used to know which card the 2D accelerator 386 // is prepared for (we use area_id of this structure) 387 bool assigned_crtc[2]; // mask of heads assigned to virtual card 388 bool used_crtc[2]; // mask of heads assigned to virtual card 389 390 display_device_e controlled_displays; // displays devices controlled byvc 391 display_device_e connected_displays; // bit-field of connected displays 392 393 int8 independant_heads; // number of heads to be programmed independantly 394 int8 different_heads; // number of heads showing different parts of framebuffer 395 bool scroll; // scrolling in virtual area enabled 396 397 uint32 datatype; // Radeon code for pixel format 398 uint bpp; // bytes per pixel 399 uint32 pitch; // byte offset between two lines 400 401 uint32 eff_width, eff_height; // size of visible area (including both monitors) 402 uint32 fb_mem_handle; // memory handle 403 uint32 fb_offset; // offset of frame buffer in graphics mem 404 405 cursor_info cursor; 406 407 bool swap_displays; // true to swap monitors 408 bool use_laptop_panel; // true to always use laptop panel 409 tv_standard_e tv_standard; // standard to use for TV Out 410 bool enforce_mode_change; // set to make sure next display mode change 411 // is executed even if display mode seems to be 412 // still the same 413 414 frame_buffer_config fbc; // data for direct frame buffer access 415 416 display_mode mode; // offical mode with multi-monitor bits set 417 overlay_buffer_node *overlay_buffers; // list of allocated overlay buffers 418 419 //int8 whished_overlay_head; // head where users whishes the overlay to be 420 bool uses_overlay; // true if this virtual card owns overlay 421 422 int state_buffer_idx; 423 int state_buffer_size; 424 } virtual_card; 425 426 427 // status of overlay 428 typedef struct { 429 int32 inuse; // one, if someone allocated overlay head 430 // (this doesn't necessarily mean that an overlay is shown) 431 uintptr_t token; // arbitrarily chosen token to identify overlay owner 432 // (increased by 1 whenever there is a new owner) 433 uint32 auto_flip_reg; // content of auto_flip_reg 434 } overlay_mgr_info; 435 436 437 // info about indirect CP buffer 438 typedef struct { 439 int next; // next used/free buffer (-1 for EOL) 440 int32 send_tag; // tag assigned when buffer was submitted 441 } indirect_buffer; 442 443 444 // info about command processor (CP) state 445 typedef struct { 446 benaphore lock; // lock to be acquired when talking to CP or 447 // when accesing this structure 448 449 // ring buffer (in non-local memory) 450 struct { 451 uint32 mem_offset; // offset in non-local memory 452 uint32 vm_base; // base of ring buffer as seen by graphics card 453 uint32 tail, tail_mask; // next write position in dwords; mask for wrap-arounds 454 uint32 size; // size in dwords 455 //uint32 head_offset; // offset for automatically updates head in DMA buffer 456 457 //uint32 start_offset; 458 memory_type_e mem_type; 459 //uint32 *start; // pointer to ring buffer 460 //vuint32 *head; // pointer to automatically updated read position 461 462 uint32 space; // known space in ring buffer 463 uint32 mem_handle; // handle of memory of indirect buffers 464 } ring; 465 466 // feedback registers (in PCI memory) 467 struct { 468 //vuint32 *ptr; // pointer to scratch registers 469 uint32 scratch_mem_offset; // offset of scratch registers in feedback memory 470 uint32 head_mem_offset; // offset of head register in feedback memory 471 uint32 scratch_vm_start; // virtual address of scratch as seen by GC 472 uint32 head_vm_address; // virtual address of head as seen by GC 473 memory_type_e mem_type; // memory type of feedback memory 474 uint32 mem_handle; // handle of feedback memory 475 } feedback; 476 477 478 // indirect buffers (in non-local memory) 479 // for indeces: -1 means "none" 480 struct { 481 int free_list; // index of first empty buffer 482 int oldest, // oldest submitted buffer 483 newest; // newest submitted buffer 484 int active_state; // index of active state buffer 485 uint64 cur_tag; // tag of last submitted indirect buffer 486 487 memory_type_e mem_type; 488 uint32 mem_offset; // offset of indirect buffers in non-local memory 489 uint32 vm_start; // start of indirect buffers as seen by graphics card 490 491 indirect_buffer buffers[NUM_INDIRECT_BUFFERS]; // info about buffers 492 uint32 mem_handle; // handle of memory of indirect buffers 493 } buffers; 494 } CP_info; 495 496 497 // info about different graphics-related memory 498 // (see memory_type_e) 499 typedef struct { 500 area_id area; // area to memory 501 uint32 size; // usable size in bytes 502 uint32 virtual_addr_start; // virtual address (for graphics card!) 503 uint32 virtual_size; // reserved virtual address space in bytes 504 } memory_type_info; 505 506 507 // data published by kernel and shared by all accelerant/virtual cards 508 typedef struct { 509 // filled out by kernel 510 CP_info cp; // info concerning command processor 511 bool acc_dma; // prevent use of dma engine 512 513 // set by accelerant 514 struct { 515 uint64 count; // count of submitted CP commands 516 uint64 last_idle; // count when engine was idle last time 517 uint64 written; // last count passed to CP 518 benaphore lock; // engine lock 519 } engine; 520 521 uint16 vendor_id; // PCI vendor id 522 uint16 device_id; // PCI device id 523 uint8 revision; // PCI device revision 524 525 radeon_type asic; // ASIC version 526 bool is_mobility; // mobility version 527 bool is_igp; // might need to know if it's an integrated chip 528 bool is_atombios; 529 530 tv_chip_type tv_chip; // type of TV-Out encoder 531 bool new_pll; // r300 style PLL 532 bool has_no_i2c; // I2C is broken 533 uint16 panel_pwr_delay; // delay for LCD backlight to stabilise 534 uint8 theatre_channel; // VIP channel of Rage Theatre (if applicable) 535 536 general_pll_info pll; 537 tmds_pll_info tmds_pll[4]; 538 539 area_id regs_area; // area of memory mapped registers 540 area_id ROM_area; // area of ROM 541 void *framebuffer_pci; // physical address of frame buffer (aka local memory) 542 // this is a hack needed by BeOS 543 544 crtc_info crtc[2]; // info about each crtc 545 uint8 num_crtc; // number of physical heads 546 547 fp_info flatpanels[2]; // info about connected flat panels (if any) 548 disp_entity routing; // info if display connector routings eg DVI-I <- EXT TMDS <- DAC2 <- CRTC2 549 550 memory_type_info memory[mt_last]; // info about memory types 551 memory_type_e nonlocal_type; // default type of non-local memory 552 553 uint8 *local_mem; // address of local memory; 554 // this is a hack requested by BeOS 555 556 area_id mode_list_area; // area containing display mode list 557 uint mode_count; 558 559 uint32 active_vc; // currently selected virtual card in terms of 2D acceleration 560 561 uint32 dac_cntl2; // content of dac_cntl2 register 562 uint32 tmds_pll_cntl; // undocumented here be dragons 563 uint32 tmds_transmitter_cntl; // undocumented here be dragons 564 565 overlay_info pending_overlay; // overlay to be shown 566 overlay_info active_overlay; // overlay shown 567 overlay_mgr_info overlay_mgr; // status of overlay 568 569 // data needed for VBI emulation 570 // (currently not fully implemented - if the user disabled graphics card 571 // IRQ in the BIOS, it's his fault) 572 int refresh_period; // duration of one frame in ms 573 int blank_period; // vertical blank period of a frame in ms 574 int enable_virtual_irq; // true, to enable virtual interrupts 575 576 radeon_settings settings; // settings from radeon.settings file 577 578 struct log_info_t *log; // fast logger data 579 } shared_info; 580 581 582 // retrieve the area_id of the kernel/accelerant shared info 583 typedef struct { 584 uint32 magic; // magic number 585 area_id shared_info_area; 586 area_id virtual_card_area; 587 } radeon_get_private_data; 588 589 // get devie name (used to clone accelerant) 590 typedef struct { 591 uint32 magic; // magic number 592 char *name; // pointer to buffer containing name (in) 593 } radeon_device_name; 594 595 // alloc (non-)local memory 596 typedef struct { 597 uint32 magic; 598 memory_type_e memory_type;// type of memory 599 uint32 size; // size in bytes 600 uint32 offset; // offset in memory 601 uint32 handle; // handle (needed to free memory) 602 bool global; // set this to true if memory should persist even 603 // if client gets terminated 604 } radeon_alloc_mem; 605 606 // free (non-)local memory 607 typedef struct { 608 uint32 magic; 609 memory_type_e memory_type;// type of memory 610 uint32 handle; // memory handle 611 bool global; // must be same as on alloc_local_mem 612 } radeon_free_mem; 613 614 // wait for idle 615 typedef struct { 616 uint32 magic; 617 bool keep_lock; // keep lock after engine is idle 618 } radeon_wait_for_idle; 619 620 // wait for idle 621 typedef struct { 622 uint32 magic; 623 int entries; // keep lock after engine is idle 624 } radeon_wait_for_fifo; 625 626 // read VIP register 627 typedef struct { 628 uint32 magic; 629 uint channel; // channel, i.e. device 630 uint address; // address 631 uint32 data; // read data 632 bool lock; // true, if CP lock must be acquired 633 } radeon_vip_read; 634 635 // write VIP register 636 typedef struct { 637 uint32 magic; 638 uint channel; // channel, i.e. device 639 uint address; // address 640 uint32 data; // data to write 641 bool lock; // true, if CP lock must be acquired 642 } radeon_vip_write; 643 644 // read VIP fifo 645 typedef struct { 646 uint32 magic; 647 uint channel; // channel, i.e. device 648 uint address; // address 649 uint32 count; // size of buffer 650 uint8 *data; // read data 651 bool lock; // true, if CP lock must be acquired 652 } radeon_vip_fifo_read; 653 654 // write VIP fifo 655 typedef struct { 656 uint32 magic; 657 uint channel; // channel, i.e. device 658 uint address; // address 659 uint32 count; // size of buffer 660 uint8 *data; // data to write 661 bool lock; // true, if CP lock must be acquired 662 } radeon_vip_fifo_write; 663 664 // find channel of device with given ID 665 typedef struct { 666 uint32 magic; 667 uint32 device_id; // id of device 668 uint channel; // channel of device (-1 if not found) 669 } radeon_find_vip_device; 670 671 // reset / init VIP 672 typedef struct { 673 uint32 magic; 674 bool lock; 675 } radeon_vip_reset; 676 677 678 // wait for capture interrupt and get status about 679 typedef struct { 680 uint32 magic; 681 bigtime_t timeout; // timeout to wait for irq 682 bigtime_t timestamp; // timestamp when last capturing was finished 683 uint32 int_status; // content of RADEON_CAP_INT_STATUS 684 uint32 counter; // number of capture interrupts so far 685 } radeon_wait_for_cap_irq; 686 687 // copy data from frame buffer to some memory location 688 typedef struct { 689 uint32 magic; 690 uint32 src; // offset of source data in frame buffer 691 void *target; // target buffer 692 size_t size; // number of bytes to copy 693 bool lock_mem; // true, if target needs to be locked 694 bool contiguous; // true, if target is physically contiguous 695 } radeon_dma_copy; 696 697 // parameter for ioctl without further arguments 698 typedef struct { 699 uint32 magic; 700 } radeon_no_arg; 701 702 #endif 703