1 /*
2 Copyright 1999, Be Incorporated. All Rights Reserved.
3 This file may be used under the terms of the Be Sample Code License.
4
5 Other authors:
6 Mark Watson;
7 Rudolf Cornelissen 3/2002-11/2022.
8 */
9
10
11 #include "AGP.h"
12 #include "DriverInterface.h"
13 #include "nv_macros.h"
14
15 #include <graphic_driver.h>
16 #include <KernelExport.h>
17 #include <SupportDefs.h>
18 #include <ISA.h>
19 #include <PCI.h>
20 #include <OS.h>
21 #include <directories.h>
22 #include <driver_settings.h>
23
24 #include <stdlib.h>
25 #include <stdio.h>
26 #include <string.h>
27
28 #define TRACE(x...) dprintf("nvidia: " x)
29 #define CALLED(x...) TRACE("CALLED %s\n", __PRETTY_FUNCTION__)
30
31 #define get_pci(o, s) (*pci_bus->read_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s))
32 #define set_pci(o, s, v) (*pci_bus->write_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s), (v))
33
34 #define MAX_DEVICES 8
35
36 /* Tell the kernel what revision of the driver API we support */
37 int32 api_version = B_CUR_DRIVER_API_VERSION;
38
39 /* these structures are private to the kernel driver */
40 typedef struct device_info device_info;
41
42 typedef struct {
43 timer te; /* timer entry for add_timer() */
44 device_info *di; /* pointer to the owning device */
45 bigtime_t when_target; /* when we're supposed to wake up */
46 } timer_info;
47
48 struct device_info {
49 uint32 is_open; /* a count of how many times the devices has been opened */
50 area_id shared_area; /* the area shared between the driver and all of the accelerants */
51 shared_info *si; /* a pointer to the shared area, for convenience */
52 vuint32 *regs; /* kernel's pointer to memory mapped registers */
53 pci_info pcii; /* a convenience copy of the pci info for this device */
54 char name[B_OS_NAME_LENGTH]; /* where we keep the name of the device for publishing and comparing */
55 };
56
57 typedef struct {
58 uint32 count; /* number of devices actually found */
59 benaphore kernel; /* for serializing opens/closes */
60 char *device_names[MAX_DEVICES+1]; /* device name pointer storage */
61 device_info di[MAX_DEVICES]; /* device specific stuff */
62 } DeviceData;
63
64 /* prototypes for our private functions */
65 static status_t open_hook(const char* name, uint32 flags, void** cookie);
66 static status_t close_hook(void* dev);
67 static status_t free_hook(void* dev);
68 static status_t read_hook(void* dev, off_t pos, void* buf, size_t* len);
69 static status_t write_hook(void* dev, off_t pos, const void* buf, size_t* len);
70 static status_t control_hook(void* dev, uint32 msg, void *buf, size_t len);
71 static status_t map_device(device_info *di);
72 static void unmap_device(device_info *di);
73 static void probe_devices(void);
74 static int32 nv_interrupt(void *data);
75
76 static DeviceData *pd;
77 static isa_module_info *isa_bus = NULL;
78 static pci_module_info *pci_bus = NULL;
79 static agp_gart_module_info *agp_bus = NULL;
80 static device_hooks graphics_device_hooks = {
81 open_hook,
82 close_hook,
83 free_hook,
84 control_hook,
85 read_hook,
86 write_hook,
87 NULL,
88 NULL,
89 NULL,
90 NULL
91 };
92
93 #define VENDOR_ID_NVIDIA 0x10de /* Nvidia */
94 #define VENDOR_ID_ELSA 0x1048 /* Elsa GmbH */
95 #define VENDOR_ID_NVSTBSGS 0x12d2 /* Nvidia STB/SGS-Thompson */
96 #define VENDOR_ID_VARISYS 0x1888 /* Varisys Limited */
97
98 static uint16 nvidia_device_list[] = {
99 0x0020, /* Nvidia TNT1 */
100 0x0028, /* Nvidia TNT2 (pro) */
101 0x0029, /* Nvidia TNT2 Ultra */
102 0x002a, /* Nvidia TNT2 */
103 0x002b, /* Nvidia TNT2 */
104 0x002c, /* Nvidia Vanta (Lt) */
105 0x002d, /* Nvidia TNT2-M64 (Pro) */
106 0x002e, /* Nvidia NV06 Vanta */
107 0x002f, /* Nvidia NV06 Vanta */
108 0x0040, /* Nvidia Geforce FX 6800 Ultra */
109 0x0041, /* Nvidia Geforce FX 6800 */
110 0x0042, /* Nvidia Geforce FX 6800LE */
111 0x0043, /* Nvidia Geforce 6800 XE */
112 0x0045, /* Nvidia Geforce FX 6800 GT */
113 0x0046, /* Nvidia Geforce FX 6800 GT */
114 0x0047, /* Nvidia Geforce 6800 GS */
115 0x0048, /* Nvidia Geforce FX 6800 XT */
116 0x0049, /* Nvidia unknown FX */
117 0x004d, /* Nvidia Quadro FX 4400 */
118 0x004e, /* Nvidia Quadro FX 4000 */
119 0x0091, /* Nvidia Geforce 7800 GTX PCIe */
120 0x0092, /* Nvidia Geforce 7800 GT PCIe */
121 0x0098, /* Nvidia Geforce 7800 Go PCIe */
122 0x0099, /* Nvidia Geforce 7800 GTX Go PCIe */
123 0x009d, /* Nvidia Quadro FX 4500 */
124 0x00a0, /* Nvidia Aladdin TNT2 */
125 0x00c0, /* Nvidia Geforce 6800 GS */
126 0x00c1, /* Nvidia Geforce FX 6800 */
127 0x00c2, /* Nvidia Geforce FX 6800LE */
128 0x00c3, /* Nvidia Geforce FX 6800 XT */
129 0x00c8, /* Nvidia Geforce FX 6800 Go */
130 0x00c9, /* Nvidia Geforce FX 6800 Ultra Go */
131 0x00cc, /* Nvidia Quadro FX 1400 Go */
132 0x00cd, /* Nvidia Quadro FX 3450/4000 SDI */
133 0x00ce, /* Nvidia Quadro FX 1400 */
134 0x00f0, /* Nvidia Geforce FX 6800 (Ultra) AGP(?) */
135 0x00f1, /* Nvidia Geforce FX 6600 GT AGP */
136 0x00f2, /* Nvidia Geforce FX 6600 AGP */
137 0x00f3, /* Nvidia Geforce 6200 */
138 0x00f4, /* Nvidia Geforce 6600 LE */
139 0x00f5, /* Nvidia Geforce FX 7800 GS AGP */
140 0x00f6, /* Nvidia Geforce 6800 GS */
141 0x00f8, /* Nvidia Quadro FX 3400/4400 PCIe */
142 0x00f9, /* Nvidia Geforce PCX 6800 PCIe */
143 0x00fa, /* Nvidia Geforce PCX 5750 PCIe */
144 0x00fb, /* Nvidia Geforce PCX 5900 PCIe */
145 0x00fc, /* Nvidia Geforce PCX 5300 PCIe */
146 0x00fd, /* Nvidia Quadro PCX PCIe */
147 0x00fe, /* Nvidia Quadro FX 1300 PCIe(?) */
148 0x00ff, /* Nvidia Geforce PCX 4300 PCIe */
149 0x0100, /* Nvidia Geforce256 SDR */
150 0x0101, /* Nvidia Geforce256 DDR */
151 0x0102, /* Nvidia Geforce256 Ultra */
152 0x0103, /* Nvidia Quadro */
153 0x0110, /* Nvidia Geforce2 MX/MX400 */
154 0x0111, /* Nvidia Geforce2 MX100/MX200 DDR */
155 0x0112, /* Nvidia Geforce2 Go */
156 0x0113, /* Nvidia Quadro2 MXR/EX/Go */
157 0x0140, /* Nvidia Geforce FX 6600 GT */
158 0x0141, /* Nvidia Geforce FX 6600 */
159 0x0142, /* Nvidia Geforce FX 6600LE */
160 0x0143, /* Nvidia Geforce 6600 VE */
161 0x0144, /* Nvidia Geforce FX 6600 Go */
162 0x0145, /* Nvidia Geforce FX 6610 XL */
163 0x0146, /* Nvidia Geforce FX 6600 TE Go / 6200 TE Go */
164 0x0147, /* Nvidia Geforce FX 6700 XL */
165 0x0148, /* Nvidia Geforce FX 6600 Go */
166 0x0149, /* Nvidia Geforce FX 6600 GT Go */
167 0x014b, /* Nvidia unknown FX */
168 0x014c, /* Nvidia Quadro FX 540 MXM */
169 0x014d, /* Nvidia unknown FX */
170 0x014e, /* Nvidia Quadro FX 540 */
171 0x014f, /* Nvidia Geforce 6200 PCIe (128Mb) */
172 0x0150, /* Nvidia Geforce2 GTS/Pro */
173 0x0151, /* Nvidia Geforce2 Ti DDR */
174 0x0152, /* Nvidia Geforce2 Ultra */
175 0x0153, /* Nvidia Quadro2 Pro */
176 0x0160, /* Nvidia Geforce 6500 Go */
177 0x0161, /* Nvidia Geforce 6200 TurboCache */
178 0x0162, /* Nvidia Geforce 6200SE TurboCache */
179 0x0163, /* Nvidia Geforce 6200LE */
180 0x0164, /* Nvidia Geforce FX 6200 Go */
181 0x0165, /* Nvidia Quadro FX NVS 285 */
182 0x0166, /* Nvidia Geforce 6400 Go */
183 0x0167, /* Nvidia Geforce 6200 Go */
184 0x0168, /* Nvidia Geforce 6400 Go */
185 0x0169, /* Nvidia Geforce 6250 Go */
186 0x016a, /* Nvidia Geforce 7100 GS */
187 0x016b, /* Nvidia unknown FX Go */
188 0x016c, /* Nvidia unknown FX Go */
189 0x016d, /* Nvidia unknown FX Go */
190 0x016e, /* Nvidia unknown FX */
191 0x0170, /* Nvidia Geforce4 MX 460 */
192 0x0171, /* Nvidia Geforce4 MX 440 */
193 0x0172, /* Nvidia Geforce4 MX 420 */
194 0x0173, /* Nvidia Geforce4 MX 440SE */
195 0x0174, /* Nvidia Geforce4 440 Go */
196 0x0175, /* Nvidia Geforce4 420 Go */
197 0x0176, /* Nvidia Geforce4 420 Go 32M */
198 0x0177, /* Nvidia Geforce4 460 Go */
199 0x0178, /* Nvidia Quadro4 500 XGL/550 XGL */
200 0x0179, /* Nvidia Geforce4 440 Go 64M (PPC: Geforce4 MX) */
201 0x017a, /* Nvidia Quadro4 200 NVS/400 NVS */
202 0x017c, /* Nvidia Quadro4 500 GoGL */
203 0x017d, /* Nvidia Geforce4 410 Go 16M */
204 0x0181, /* Nvidia Geforce4 MX 440 AGP8X */
205 0x0182, /* Nvidia Geforce4 MX 440SE AGP8X */
206 0x0183, /* Nvidia Geforce4 MX 420 AGP8X */
207 0x0185, /* Nvidia Geforce4 MX 4000 AGP8X */
208 0x0186, /* Nvidia Geforce4 448 Go */
209 0x0187, /* Nvidia Geforce4 488 Go */
210 0x0188, /* Nvidia Quadro4 580 XGL */
211 0x0189, /* Nvidia Geforce4 MX AGP8X (PPC) */
212 0x018a, /* Nvidia Quadro4 280 NVS AGP8X */
213 0x018b, /* Nvidia Quadro4 380 XGL */
214 0x018c, /* Nvidia Quadro4 NVS 50 PCI */
215 0x018d, /* Nvidia Geforce4 448 Go */
216 0x01a0, /* Nvidia Geforce2 Integrated GPU */
217 0x01d1, /* Nvidia Geforce 7300 LE */
218 0x01d3, /* Nvidia Geforce 7300 SE */
219 0x01d7, /* Nvidia Quadro NVS 110M/Geforce 7300 Go */
220 0x01d8, /* Nvidia Geforce 7400 GO */
221 0x01da, /* Nvidia Quadro NVS 110M */
222 0x01dd, /* Nvidia Geforce 7500 LE */
223 0x01df, /* Nvidia Geforce 7300 GS */
224 0x01f0, /* Nvidia Geforce4 MX Integrated GPU */
225 0x0200, /* Nvidia Geforce3 */
226 0x0201, /* Nvidia Geforce3 Ti 200 */
227 0x0202, /* Nvidia Geforce3 Ti 500 */
228 0x0203, /* Nvidia Quadro DCC */
229 0x0211, /* Nvidia Geforce FX 6800 */
230 0x0212, /* Nvidia Geforce FX 6800LE */
231 0x0215, /* Nvidia Geforce FX 6800 GT */
232 0x0218, /* Nvidia Geforce 6800 XT */
233 0x0220, /* Nvidia unknown FX */
234 0x0221, /* Nvidia Geforce 6200 AGP (256Mb - 128bit) */
235 0x0222, /* Nvidia unknown FX */
236 0x0228, /* Nvidia unknown FX Go */
237 0x0240, /* Nvidia Geforce 6150 (NFORCE4 Integr.GPU) */
238 0x0241, /* Nvidia Geforce 6150 LE (NFORCE4 Integr.GPU) */
239 0x0242, /* Nvidia Geforce 6100 (NFORCE4 Integr.GPU) */
240 0x0244, /* Nvidia Geforce Go 6150 (NFORCE4 Integr.GPU) */
241 0x0245, /* Nvidia Quadro NVS 210S / Geforce 6150LE */
242 0x0247, /* Nvidia Geforce 6100 Go (NFORCE4 Integr.GPU) */
243 0x0250, /* Nvidia Geforce4 Ti 4600 */
244 0x0251, /* Nvidia Geforce4 Ti 4400 */
245 0x0252, /* Nvidia Geforce4 Ti 4600 */
246 0x0253, /* Nvidia Geforce4 Ti 4200 */
247 0x0258, /* Nvidia Quadro4 900 XGL */
248 0x0259, /* Nvidia Quadro4 750 XGL */
249 0x025b, /* Nvidia Quadro4 700 XGL */
250 0x0280, /* Nvidia Geforce4 Ti 4800 AGP8X */
251 0x0281, /* Nvidia Geforce4 Ti 4200 AGP8X */
252 0x0282, /* Nvidia Geforce4 Ti 4800SE */
253 0x0286, /* Nvidia Geforce4 4200 Go */
254 0x0288, /* Nvidia Quadro4 980 XGL */
255 0x0289, /* Nvidia Quadro4 780 XGL */
256 0x028c, /* Nvidia Quadro4 700 GoGL */
257 0x0290, /* Nvidia Geforce 7900 GTX */
258 0x0291, /* Nvidia Geforce 7900 GT */
259 0x0292, /* Nvidia Geforce 7900 GS */
260 0x0293, /* Nvidia Geforce 7900 GX2 */
261 0x0294, /* Nvidia Geforce 7950 GX2 */
262 0x0295, /* Nvidia Geforce 7950 GT */
263 0x0298, /* Nvidia Geforce Go 7900 GS */
264 0x0299, /* Nvidia Geforce Go 7900 GTX */
265 0x029c, /* Nvidia Quadro FX 5500 */
266 0x029f, /* Nvidia Quadro FX 4500 X2 */
267 0x02a0, /* Nvidia Geforce3 Integrated GPU */
268 0x02e0, /* Nvidia Geforce 7600 GT */
269 0x02e1, /* Nvidia Geforce 7600 GS */
270 0x02e2, /* Nvidia Geforce 7300 GT */
271 0x0301, /* Nvidia Geforce FX 5800 Ultra */
272 0x0302, /* Nvidia Geforce FX 5800 */
273 0x0308, /* Nvidia Quadro FX 2000 */
274 0x0309, /* Nvidia Quadro FX 1000 */
275 0x0311, /* Nvidia Geforce FX 5600 Ultra */
276 0x0312, /* Nvidia Geforce FX 5600 */
277 0x0313, /* Nvidia unknown FX */
278 0x0314, /* Nvidia Geforce FX 5600XT */
279 0x0316, /* Nvidia unknown FX Go */
280 0x0317, /* Nvidia unknown FX Go */
281 0x031a, /* Nvidia Geforce FX 5600 Go */
282 0x031b, /* Nvidia Geforce FX 5650 Go */
283 0x031c, /* Nvidia Quadro FX 700 Go */
284 0x031d, /* Nvidia unknown FX Go */
285 0x031e, /* Nvidia unknown FX Go */
286 0x031f, /* Nvidia unknown FX Go */
287 0x0320, /* Nvidia Geforce FX 5200 */
288 0x0321, /* Nvidia Geforce FX 5200 Ultra */
289 0x0322, /* Nvidia Geforce FX 5200 */
290 0x0323, /* Nvidia Geforce FX 5200LE */
291 0x0324, /* Nvidia Geforce FX 5200 Go */
292 0x0325, /* Nvidia Geforce FX 5250 Go */
293 0x0326, /* Nvidia Geforce FX 5500 */
294 0x0327, /* Nvidia Geforce FX 5100 */
295 0x0328, /* Nvidia Geforce FX 5200 Go 32M/64M */
296 0x0329, /* Nvidia Geforce FX 5200 (PPC) */
297 0x032a, /* Nvidia Quadro NVS 280 PCI */
298 0x032b, /* Nvidia Quadro FX 500/600 PCI */
299 0x032c, /* Nvidia Geforce FX 5300 Go */
300 0x032d, /* Nvidia Geforce FX 5100 Go */
301 0x032e, /* Nvidia unknown FX Go */
302 0x032f, /* Nvidia unknown FX Go */
303 0x0330, /* Nvidia Geforce FX 5900 Ultra */
304 0x0331, /* Nvidia Geforce FX 5900 */
305 0x0332, /* Nvidia Geforce FX 5900 XT */
306 0x0333, /* Nvidia Geforce FX 5950 Ultra */
307 0x0334, /* Nvidia Geforce FX 5900 ZT */
308 0x0338, /* Nvidia Quadro FX 3000 */
309 0x033f, /* Nvidia Quadro FX 700 */
310 0x0341, /* Nvidia Geforce FX 5700 Ultra */
311 0x0342, /* Nvidia Geforce FX 5700 */
312 0x0343, /* Nvidia Geforce FX 5700LE */
313 0x0344, /* Nvidia Geforce FX 5700VE */
314 0x0345, /* Nvidia unknown FX */
315 0x0347, /* Nvidia Geforce FX 5700 Go */
316 0x0348, /* Nvidia Geforce FX 5700 Go */
317 0x0349, /* Nvidia unknown FX Go */
318 0x034b, /* Nvidia unknown FX Go */
319 0x034c, /* Nvidia Quadro FX 1000 Go */
320 0x034e, /* Nvidia Quadro FX 1100 */
321 0x034f, /* Nvidia unknown FX */
322 0x0391, /* Nvidia Geforce 7600 GT */
323 0x0392, /* Nvidia Geforce 7600 GS */
324 0x0393, /* Nvidia Geforce 7300 GT */
325 0x0394, /* Nvidia Geforce 7600 LE */
326 0x0398, /* Nvidia Geforce 7600 GO */
327 0x03d0, /* Nvidia Geforce 6100 nForce 430 */
328 0x03d1, /* Nvidia Geforce 6100 nForce 405 */
329 0x03d2, /* Nvidia Geforce 6100 nForce 400 */
330 0x03d5, /* Nvidia Geforce 6100 nForce 420 */
331 0x03d6, /* Nvidia Geforce 7025 / nForce 630a */
332 0x06e4, /* Nvidia Geforce 8400 GS G98 */
333 0x06e8, /* Nvidia Geforce 9200M G98M */
334 0x07e1, /* Nvidia Geforce 7100 / nForce 630i */
335 0
336 };
337
338 static uint16 elsa_device_list[] = {
339 0x0c60, /* Elsa Gladiac Geforce2 MX */
340 0
341 };
342
343 static uint16 nvstbsgs_device_list[] = {
344 0x0020, /* Nvidia STB/SGS-Thompson TNT1 */
345 0x0028, /* Nvidia STB/SGS-Thompson TNT2 (pro) */
346 0x0029, /* Nvidia STB/SGS-Thompson TNT2 Ultra */
347 0x002a, /* Nvidia STB/SGS-Thompson TNT2 */
348 0x002b, /* Nvidia STB/SGS-Thompson TNT2 */
349 0x002c, /* Nvidia STB/SGS-Thompson Vanta (Lt) */
350 0x002d, /* Nvidia STB/SGS-Thompson TNT2-M64 (Pro) */
351 0x002e, /* Nvidia STB/SGS-Thompson NV06 Vanta */
352 0x002f, /* Nvidia STB/SGS-Thompson NV06 Vanta */
353 0x00a0, /* Nvidia STB/SGS-Thompson Aladdin TNT2 */
354 0
355 };
356
357 static uint16 varisys_device_list[] = {
358 0x3503, /* Varisys Geforce4 MX440 */
359 0x3505, /* Varisys Geforce4 Ti 4200 */
360 0
361 };
362
363 static struct {
364 uint16 vendor;
365 uint16 *devices;
366 } SupportedDevices[] = {
367 {VENDOR_ID_NVIDIA, nvidia_device_list},
368 {VENDOR_ID_ELSA, elsa_device_list},
369 {VENDOR_ID_NVSTBSGS, nvstbsgs_device_list},
370 {VENDOR_ID_VARISYS, varisys_device_list},
371 {0x0000, NULL}
372 };
373
374 static nv_settings sSettings = { // see comments in nvidia.settings
375 /* for driver */
376 DRIVER_PREFIX ".accelerant",
377 "none", // primary
378 false, // dumprom
379 /* for accelerant */
380 0x00000000, // logmask
381 0, // memory
382 0, // tv_output
383 true, // usebios
384 true, // hardcursor
385 false, // switchhead
386 false, // force_pci
387 false, // unhide_fw
388 false, // pgm_panel
389 true, // dma_acc
390 false, // vga_on_tv
391 false, // force_sync
392 false, // force_ws
393 false, // block_acc
394 0, // gpu_clk
395 0, // ram_clk
396 true, // check_edid
397 };
398
399
400 static void
dumprom(void * rom,uint32 size,pci_info pcii)401 dumprom(void *rom, uint32 size, pci_info pcii)
402 {
403 int fd;
404 uint32 cnt;
405 char fname[64];
406
407 CALLED();
408 /* determine the romfile name: we need split-up per card in the system */
409 sprintf (fname, kUserDirectory "//" DRIVER_PREFIX "." DEVICE_FORMAT ".rom",
410 pcii.vendor_id, pcii.device_id, pcii.bus, pcii.device, pcii.function);
411
412 fd = open (fname, O_WRONLY | O_CREAT, 0666);
413 if (fd < 0) return;
414
415 /* apparantly max. 32kb may be written at once;
416 * the ROM size is a multiple of that anyway. */
417 for (cnt = 0; (cnt < size); cnt += 32768)
418 write (fd, ((void *)(((uint8 *)rom) + cnt)), 32768);
419 close (fd);
420 }
421
422
423 /*! return 1 if vblank interrupt has occured */
424 static int
caused_vbi_crtc1(vuint32 * regs)425 caused_vbi_crtc1(vuint32 * regs)
426 {
427 return (NV_REG32(NV32_CRTC_INTS) & 0x00000001);
428 }
429
430
431 /*! clear the vblank interrupt */
432 static void
clear_vbi_crtc1(vuint32 * regs)433 clear_vbi_crtc1(vuint32 * regs)
434 {
435 NV_REG32(NV32_CRTC_INTS) = 0x00000001;
436 }
437
438
439 static void
enable_vbi_crtc1(vuint32 * regs)440 enable_vbi_crtc1(vuint32 * regs)
441 {
442 /* clear the vblank interrupt */
443 NV_REG32(NV32_CRTC_INTS) = 0x00000001;
444 /* enable nVidia interrupt source vblank */
445 NV_REG32(NV32_CRTC_INTE) |= 0x00000001;
446 /* enable nVidia interrupt system hardware (b0-1) */
447 NV_REG32(NV32_MAIN_INTE) = 0x00000001;
448 }
449
450
451 static void
disable_vbi_crtc1(vuint32 * regs)452 disable_vbi_crtc1(vuint32 * regs)
453 {
454 /* disable nVidia interrupt source vblank */
455 NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe;
456 /* clear the vblank interrupt */
457 NV_REG32(NV32_CRTC_INTS) = 0x00000001;
458 }
459
460
461 /*! return 1 if vblank interrupt has occured */
462 static int
caused_vbi_crtc2(vuint32 * regs)463 caused_vbi_crtc2(vuint32 * regs)
464 {
465 return (NV_REG32(NV32_CRTC2_INTS) & 0x00000001);
466 }
467
468
469 /*! clear the vblank interrupt */
470 static void
clear_vbi_crtc2(vuint32 * regs)471 clear_vbi_crtc2(vuint32 * regs)
472 {
473 NV_REG32(NV32_CRTC2_INTS) = 0x00000001;
474 }
475
476
477 static void
enable_vbi_crtc2(vuint32 * regs)478 enable_vbi_crtc2(vuint32 * regs)
479 {
480 /* clear the vblank interrupt */
481 NV_REG32(NV32_CRTC2_INTS) = 0x00000001;
482 /* enable nVidia interrupt source vblank */
483 NV_REG32(NV32_CRTC2_INTE) |= 0x00000001;
484 /* enable nVidia interrupt system hardware (b0-1) */
485 NV_REG32(NV32_MAIN_INTE) = 0x00000001;
486 }
487
488
489 static void
disable_vbi_crtc2(vuint32 * regs)490 disable_vbi_crtc2(vuint32 * regs)
491 {
492 /* disable nVidia interrupt source vblank */
493 NV_REG32(NV32_CRTC2_INTE) &= 0xfffffffe;
494 /* clear the vblank interrupt */
495 NV_REG32(NV32_CRTC2_INTS) = 0x00000001;
496 }
497
498
499 //fixme:
500 //dangerous code, on singlehead cards better not try accessing secondary head
501 //registers (card might react in unpredictable ways, though there's only a small
502 //chance we actually run into this).
503 //fix requires (some) card recognition code to be moved from accelerant to
504 //kerneldriver...
505 static void
disable_vbi_all(vuint32 * regs)506 disable_vbi_all(vuint32 * regs)
507 {
508 /* disable nVidia interrupt source vblank */
509 NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe;
510 /* clear the vblank interrupt */
511 NV_REG32(NV32_CRTC_INTS) = 0x00000001;
512
513 /* disable nVidia interrupt source vblank */
514 NV_REG32(NV32_CRTC2_INTE) &= 0xfffffffe;
515 /* clear the vblank interrupt */
516 NV_REG32(NV32_CRTC2_INTS) = 0x00000001;
517
518 /* disable nVidia interrupt system hardware (b0-1) */
519 NV_REG32(NV32_MAIN_INTE) = 0x00000000;
520 }
521
522
523 static status_t
map_device(device_info * di)524 map_device(device_info *di)
525 {
526 char buffer[B_OS_NAME_LENGTH]; /*memory for device name*/
527 shared_info *si = di->si;
528 uint32 tmpUlong, tmpROMshadow;
529 pci_info *pcii = &(di->pcii);
530 phys_addr_t physicalAddress;
531 system_info sysinfo;
532
533 CALLED();
534 /* variables for making copy of ROM */
535 uint8* rom_temp;
536 area_id rom_area = -1;
537
538 /* Nvidia cards have registers in [0] and framebuffer in [1] */
539 int registers = 0;
540 int frame_buffer = 1;
541
542 /* enable memory mapped IO, disable VGA I/O - this is defined in the PCI standard */
543 tmpUlong = get_pci(PCI_command, 2);
544 /* enable PCI access */
545 tmpUlong |= PCI_command_memory;
546 /* enable busmastering */
547 tmpUlong |= PCI_command_master;
548 /* disable ISA I/O access */
549 tmpUlong &= ~PCI_command_io;
550 set_pci(PCI_command, 2, tmpUlong);
551
552 /*work out which version of BeOS is running*/
553 get_system_info(&sysinfo);
554 if (0)//sysinfo.kernel_build_date[0]=='J')/*FIXME - better ID version*/
555 {
556 si->use_clone_bugfix = 1;
557 }
558 else
559 {
560 si->use_clone_bugfix = 0;
561 }
562
563 /* work out a name for the register mapping */
564 sprintf(buffer, DEVICE_FORMAT " regs",
565 di->pcii.vendor_id, di->pcii.device_id,
566 di->pcii.bus, di->pcii.device, di->pcii.function);
567
568 if ((di->pcii.u.h0.base_register_flags[registers] & PCI_address_type)
569 == PCI_address_type_64) {
570 TRACE("registers is 64 bit\n");
571 } else {
572 TRACE("registers is 32 bit\n");
573 }
574
575 /* get a virtual memory address for the registers*/
576 si->regs_area = map_physical_memory(
577 buffer,
578 /* WARNING: Nvidia needs to map regs as viewed from PCI space! */
579 di->pcii.u.h0.base_registers_pci[registers],
580 di->pcii.u.h0.base_register_sizes[registers],
581 B_ANY_KERNEL_ADDRESS,
582 B_CLONEABLE_AREA | B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA,
583 (void **)&(di->regs));
584 si->clone_bugfix_regs = (uint32 *) di->regs;
585
586 /* if mapping registers to vmem failed then pass on error */
587 if (si->regs_area < 0) return si->regs_area;
588
589 /* work out a name for the ROM mapping*/
590 sprintf(buffer, DEVICE_FORMAT " rom",
591 di->pcii.vendor_id, di->pcii.device_id,
592 di->pcii.bus, di->pcii.device, di->pcii.function);
593
594 /* preserve ROM shadowing setting, we need to restore the current state later on. */
595 /* warning:
596 * 'don't touch': (confirmed) NV04, NV05, NV05-M64, NV11 all shutoff otherwise.
597 * NV18, NV28 and NV34 keep working.
598 * confirmed NV28 and NV34 to use upper part of shadowed ROM for scratch purposes,
599 * however the actual ROM content (so the used part) is intact (confirmed). */
600 tmpROMshadow = get_pci(NVCFG_ROMSHADOW, 4);
601 /* temporary disable ROM shadowing, we want the guaranteed exact contents of the chip */
602 set_pci(NVCFG_ROMSHADOW, 4, 0);
603
604 /* get ROM memory mapped base adress - this is defined in the PCI standard */
605 tmpUlong = get_pci(PCI_rom_base, 4);
606 //fixme?: if (!tmpUlong) try to map the ROM ourselves. Confirmed a PCIe system not
607 //having the ROM mapped on PCI and PCIe cards. Falling back to fetching from ISA
608 //legacy space will get us into trouble if we aren't the primary graphics card!!
609 //(as legacy space always has the primary card's ROM 'mapped'!)
610 if (tmpUlong) {
611 /* ROM was assigned an adress, so enable ROM decoding - see PCI standard */
612 tmpUlong |= 0x00000001;
613 set_pci(PCI_rom_base, 4, tmpUlong);
614
615 rom_area = map_physical_memory(
616 buffer,
617 di->pcii.u.h0.rom_base_pci,
618 di->pcii.u.h0.rom_size,
619 B_ANY_KERNEL_ADDRESS,
620 B_KERNEL_READ_AREA,
621 (void **)&(rom_temp)
622 );
623
624 /* check if we got the BIOS and signature (might fail on laptops..) */
625 if (rom_area >= 0) {
626 if ((rom_temp[0] != 0x55) || (rom_temp[1] != 0xaa)) {
627 /* apparantly no ROM is mapped here */
628 delete_area(rom_area);
629 rom_area = -1;
630 /* force using ISA legacy map as fall-back */
631 tmpUlong = 0x00000000;
632 }
633 } else {
634 /* mapping failed: force using ISA legacy map as fall-back */
635 tmpUlong = 0x00000000;
636 }
637 }
638
639 if (!tmpUlong) {
640 /* ROM was not assigned an adress, fetch it from ISA legacy memory map! */
641 rom_area = map_physical_memory(buffer, 0x000c0000,
642 65536, B_ANY_KERNEL_ADDRESS, B_KERNEL_READ_AREA, (void **)&(rom_temp));
643 }
644
645 /* if mapping ROM to vmem failed then clean up and pass on error */
646 if (rom_area < 0) {
647 delete_area(si->regs_area);
648 si->regs_area = -1;
649 return rom_area;
650 }
651
652 /* dump ROM to file if selected in nvidia.settings
653 * (ROM always fits in 64Kb: checked TNT1 - FX5950) */
654 if (sSettings.dumprom)
655 dumprom(rom_temp, 65536, di->pcii);
656
657 /* make a copy of ROM for future reference */
658 memcpy(si->rom_mirror, rom_temp, 65536);
659
660 /* disable ROM decoding - this is defined in the PCI standard, and delete the area */
661 tmpUlong = get_pci(PCI_rom_base, 4);
662 tmpUlong &= 0xfffffffe;
663 set_pci(PCI_rom_base, 4, tmpUlong);
664 delete_area(rom_area);
665
666 /* restore original ROM shadowing setting to prevent trouble starting (some) cards */
667 set_pci(NVCFG_ROMSHADOW, 4, tmpROMshadow);
668
669 /* work out a name for the framebuffer mapping*/
670 sprintf(buffer, DEVICE_FORMAT " framebuffer",
671 di->pcii.vendor_id, di->pcii.device_id,
672 di->pcii.bus, di->pcii.device, di->pcii.function);
673
674 physicalAddress = di->pcii.u.h0.base_registers_pci[frame_buffer];
675 if ((di->pcii.u.h0.base_register_flags[frame_buffer] & PCI_address_type)
676 == PCI_address_type_64) {
677 TRACE("framebuffer is 64 bit\n");
678 physicalAddress
679 |= (uint64)di->pcii.u.h0.base_registers_pci[frame_buffer + 1] << 32;
680 } else {
681 TRACE("framebuffer is 32 bit\n");
682 }
683
684 /* map the framebuffer into vmem, using Write Combining*/
685 si->fb_area = map_physical_memory(buffer,
686 /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */
687 physicalAddress,
688 di->pcii.u.h0.base_register_sizes[frame_buffer],
689 B_ANY_KERNEL_BLOCK_ADDRESS | B_WRITE_COMBINING_MEMORY,
690 B_READ_AREA | B_WRITE_AREA | B_CLONEABLE_AREA,
691 &(si->framebuffer));
692
693 /*if failed with write combining try again without*/
694 if (si->fb_area < 0) {
695 si->fb_area = map_physical_memory(buffer,
696 /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */
697 physicalAddress,
698 di->pcii.u.h0.base_register_sizes[frame_buffer],
699 B_ANY_KERNEL_BLOCK_ADDRESS,
700 B_READ_AREA | B_WRITE_AREA | B_CLONEABLE_AREA,
701 &(si->framebuffer));
702 }
703
704 /* if there was an error, delete our other areas and pass on error*/
705 if (si->fb_area < 0) {
706 delete_area(si->regs_area);
707 si->regs_area = -1;
708 return si->fb_area;
709 }
710
711 //fixme: retest for card coldstart and PCI/virt_mem mapping!!
712 /* remember the DMA address of the frame buffer for BDirectWindow?? purposes */
713 si->framebuffer_pci = (void *) physicalAddress;
714
715 /* note the amount of memory mapped by the kerneldriver so we can make sure we
716 * don't attempt to adress more later on */
717 si->ps.memory_size = di->pcii.u.h0.base_register_sizes[frame_buffer];
718
719 // remember settings for use here and in accelerant
720 si->settings = sSettings;
721
722 if (si->fb_area >= 0) {
723 TRACE("framebuffer mapped OK\n");
724 } else {
725 TRACE("framebuffer mapping failed!\n");
726 }
727
728 /* in any case, return the result */
729 return si->fb_area;
730 }
731
732
733 static void
unmap_device(device_info * di)734 unmap_device(device_info *di)
735 {
736 shared_info *si = di->si;
737 uint32 tmpUlong;
738 pci_info *pcii = &(di->pcii);
739
740 CALLED();
741 /* disable memory mapped IO */
742 tmpUlong = get_pci(PCI_command, 4);
743 tmpUlong &= 0xfffffffc;
744 set_pci(PCI_command, 4, tmpUlong);
745 /* delete the areas */
746 if (si->regs_area >= 0)
747 delete_area(si->regs_area);
748 if (si->fb_area >= 0)
749 delete_area(si->fb_area);
750 si->regs_area = si->fb_area = -1;
751 si->framebuffer = NULL;
752 di->regs = NULL;
753 }
754
755
756 static void
probe_devices(void)757 probe_devices(void)
758 {
759 uint32 pci_index = 0;
760 uint32 count = 0;
761 device_info *di = pd->di;
762 char tmp_name[B_OS_NAME_LENGTH];
763
764 CALLED();
765 /* while there are more pci devices */
766 while (count < MAX_DEVICES
767 && (*pci_bus->get_nth_pci_info)(pci_index, &(di->pcii)) == B_OK) {
768 int vendor = 0;
769
770 /* if we match a supported vendor */
771 while (SupportedDevices[vendor].vendor) {
772 if (SupportedDevices[vendor].vendor == di->pcii.vendor_id) {
773 uint16 *devices = SupportedDevices[vendor].devices;
774 /* while there are more supported devices */
775 while (*devices) {
776 /* if we match a supported device */
777 if (*devices == di->pcii.device_id ) {
778 /* publish the device name */
779 sprintf(tmp_name, DEVICE_FORMAT,
780 di->pcii.vendor_id, di->pcii.device_id,
781 di->pcii.bus, di->pcii.device, di->pcii.function);
782 /* tweak the exported name to show first in the alphabetically ordered /dev/
783 * hierarchy folder, so the system will use it as primary adaptor if requested
784 * via nvidia.settings. */
785 if (strcmp(tmp_name, sSettings.primary) == 0)
786 sprintf(tmp_name, "-%s", sSettings.primary);
787 /* add /dev/ hierarchy path */
788 sprintf(di->name, "graphics/%s", tmp_name);
789 /* remember the name */
790 pd->device_names[count] = di->name;
791 /* mark the driver as available for R/W open */
792 di->is_open = 0;
793 /* mark areas as not yet created */
794 di->shared_area = -1;
795 /* mark pointer to shared data as invalid */
796 di->si = NULL;
797 /* inc pointer to device info */
798 di++;
799 /* inc count */
800 count++;
801 /* break out of these while loops */
802 goto next_device;
803 }
804 /* next supported device */
805 devices++;
806 }
807 }
808 vendor++;
809 }
810 next_device:
811 /* next pci_info struct, please */
812 pci_index++;
813 }
814 /* propagate count */
815 pd->count = count;
816 /* terminate list of device names with a null pointer */
817 pd->device_names[pd->count] = NULL;
818 }
819
820
821 static uint32
thread_interrupt_work(int32 * flags,vuint32 * regs,shared_info * si)822 thread_interrupt_work(int32 *flags, vuint32 *regs, shared_info *si)
823 {
824 uint32 handled = B_HANDLED_INTERRUPT;
825 /* release the vblank semaphore */
826 if (si->vblank >= 0) {
827 int32 blocked;
828 if ((get_sem_count(si->vblank, &blocked) == B_OK) && (blocked < 0)) {
829 release_sem_etc(si->vblank, -blocked, B_DO_NOT_RESCHEDULE);
830 handled = B_INVOKE_SCHEDULER;
831 }
832 }
833 return handled;
834 }
835
836
837 static int32
nv_interrupt(void * data)838 nv_interrupt(void *data)
839 {
840 int32 handled = B_UNHANDLED_INTERRUPT;
841 device_info *di = (device_info *)data;
842 shared_info *si = di->si;
843 int32 *flags = &(si->flags);
844 vuint32 *regs;
845
846 /* is someone already handling an interrupt for this device? */
847 if (atomic_or(flags, SKD_HANDLER_INSTALLED) & SKD_HANDLER_INSTALLED) goto exit0;
848
849 /* get regs */
850 regs = di->regs;
851
852 /* was it a VBI? */
853 /* note: si->ps.secondary_head was cleared by kerneldriver earlier! (at least) */
854 if (si->ps.secondary_head) {
855 //fixme:
856 //rewrite once we use one driver instance 'per head' (instead of 'per card')
857 if (caused_vbi_crtc1(regs) || caused_vbi_crtc2(regs)) {
858 /* clear the interrupt(s) */
859 clear_vbi_crtc1(regs);
860 clear_vbi_crtc2(regs);
861 /* release the semaphore */
862 handled = thread_interrupt_work(flags, regs, si);
863 }
864 } else {
865 if (caused_vbi_crtc1(regs)) {
866 /* clear the interrupt */
867 clear_vbi_crtc1(regs);
868 /* release the semaphore */
869 handled = thread_interrupt_work(flags, regs, si);
870 }
871 }
872
873 /* note that we're not in the handler any more */
874 atomic_and(flags, ~SKD_HANDLER_INSTALLED);
875
876 exit0:
877 return handled;
878 }
879
880
881 // #pragma mark - device hooks
882
883
884 static status_t
open_hook(const char * name,uint32 flags,void ** cookie)885 open_hook(const char* name, uint32 flags, void** cookie)
886 {
887 int32 index = 0;
888 device_info *di;
889 shared_info *si;
890 thread_id thid;
891 thread_info thinfo;
892 status_t result = B_OK;
893 char shared_name[B_OS_NAME_LENGTH];
894 physical_entry map[1];
895 size_t net_buf_size;
896 void *unaligned_dma_buffer;
897 uint32 mem_size;
898
899 CALLED();
900 /* find the device name in the list of devices */
901 /* we're never passed a name we didn't publish */
902 while (pd->device_names[index]
903 && (strcmp(name, pd->device_names[index]) != 0))
904 index++;
905
906 /* for convienience */
907 di = &(pd->di[index]);
908
909 /* make sure no one else has write access to the common data */
910 AQUIRE_BEN(pd->kernel);
911
912 /* if it's already open for writing */
913 if (di->is_open) {
914 /* mark it open another time */
915 goto mark_as_open;
916 }
917 /* create the shared_info area */
918 sprintf(shared_name, DEVICE_FORMAT " shared",
919 di->pcii.vendor_id, di->pcii.device_id,
920 di->pcii.bus, di->pcii.device, di->pcii.function);
921 di->shared_area = create_area(shared_name, (void **)&(di->si), B_ANY_KERNEL_ADDRESS,
922 ((sizeof(shared_info) + (B_PAGE_SIZE - 1)) & ~(B_PAGE_SIZE - 1)), B_FULL_LOCK,
923 B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA | B_CLONEABLE_AREA);
924 if (di->shared_area < 0) {
925 /* return the error */
926 result = di->shared_area;
927 goto done;
928 }
929
930 /* save a few dereferences */
931 si = di->si;
932
933 /* create the DMA command buffer area */
934 //fixme? for R4.5 a workaround for cloning would be needed!
935 /* we want to setup a 1Mb buffer (size must be multiple of B_PAGE_SIZE) */
936 net_buf_size = ((1 * 1024 * 1024) + (B_PAGE_SIZE-1)) & ~(B_PAGE_SIZE-1);
937 /* create the area that will hold the DMA command buffer */
938 si->unaligned_dma_area =
939 create_area("NV DMA cmd buffer",
940 (void **)&unaligned_dma_buffer,
941 B_ANY_KERNEL_ADDRESS,
942 2 * net_buf_size, /* take twice the net size so we can have MTRR-WC even on old systems */
943 B_32_BIT_CONTIGUOUS, /* GPU always needs access */
944 B_CLONEABLE_AREA | B_READ_AREA | B_WRITE_AREA);
945 // TODO: Physical aligning can be done without waste using the
946 // private create_area_etc().
947 /* on error, abort */
948 if (si->unaligned_dma_area < 0)
949 {
950 /* free the already created shared_info area, and return the error */
951 result = si->unaligned_dma_area;
952 goto free_shared;
953 }
954 /* we (also) need the physical adress our DMA buffer is at, as this needs to be
955 * fed into the GPU's engine later on. Get an aligned adress so we can use MTRR-WC
956 * even on older CPU's. */
957 get_memory_map(unaligned_dma_buffer, B_PAGE_SIZE, map, 1);
958 si->dma_buffer_pci = (void*)
959 ((map[0].address + net_buf_size - 1) & ~(net_buf_size - 1));
960
961 /* map the net DMA command buffer into vmem, using Write Combining */
962 si->dma_area = map_physical_memory(
963 "NV aligned DMA cmd buffer", (addr_t)si->dma_buffer_pci, net_buf_size,
964 B_ANY_KERNEL_BLOCK_ADDRESS | B_WRITE_COMBINING_MEMORY,
965 B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer));
966 /* if failed with write combining try again without */
967 if (si->dma_area < 0) {
968 si->dma_area = map_physical_memory("NV aligned DMA cmd buffer",
969 (addr_t)si->dma_buffer_pci, net_buf_size,
970 B_ANY_KERNEL_BLOCK_ADDRESS,
971 B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer));
972 }
973 /* if there was an error, delete our other areas and pass on error*/
974 if (si->dma_area < 0)
975 {
976 /* free the already created areas, and return the error */
977 result = si->dma_area;
978 goto free_shared_and_uadma;
979 }
980
981 /* save the vendor and device IDs */
982 si->vendor_id = di->pcii.vendor_id;
983 si->device_id = di->pcii.device_id;
984 si->revision = di->pcii.revision;
985 si->bus = di->pcii.bus;
986 si->device = di->pcii.device;
987 si->function = di->pcii.function;
988
989 /* ensure that the accelerant's INIT_ACCELERANT function can be executed */
990 si->accelerant_in_use = false;
991 /* preset singlehead card to prevent early INT routine calls (once installed) to
992 * wrongly identify the INT request coming from us! */
993 si->ps.secondary_head = false;
994
995 /* map the device */
996 result = map_device(di);
997 if (result < 0) goto free_shared_and_alldma;
998
999 /* we will be returning OK status for sure now */
1000 result = B_OK;
1001
1002 /* note the amount of system RAM the system BIOS assigned to the card if applicable:
1003 * unified memory architecture (UMA) */
1004 switch ((((uint32)(si->device_id)) << 16) | si->vendor_id)
1005 {
1006 case 0x01a010de: /* Nvidia Geforce2 Integrated GPU */
1007 /* device at bus #0, device #0, function #1 holds value at byte-index 0x7C */
1008 mem_size = 1024 * 1024 *
1009 (((((*pci_bus->read_pci_config)(0, 0, 1, 0x7c, 4)) & 0x000007c0) >> 6) + 1);
1010 /* don't attempt to adress memory not mapped by the kerneldriver */
1011 if (si->ps.memory_size > mem_size) si->ps.memory_size = mem_size;
1012 /* last 64kB RAM is used for the BIOS (or something else?) */
1013 si->ps.memory_size -= (64 * 1024);
1014 break;
1015 case 0x01f010de: /* Nvidia Geforce4 MX Integrated GPU */
1016 /* device at bus #0, device #0, function #1 holds value at byte-index 0x84 */
1017 mem_size = 1024 * 1024 *
1018 (((((*pci_bus->read_pci_config)(0, 0, 1, 0x84, 4)) & 0x000007f0) >> 4) + 1);
1019 /* don't attempt to adress memory not mapped by the kerneldriver */
1020 if (si->ps.memory_size > mem_size) si->ps.memory_size = mem_size;
1021 /* last 64kB RAM is used for the BIOS (or something else?) */
1022 si->ps.memory_size -= (64 * 1024);
1023 break;
1024 default:
1025 /* all other cards have own RAM: the amount of which is determined in the
1026 * accelerant. */
1027 break;
1028 }
1029
1030 /* disable and clear any pending interrupts */
1031 //fixme:
1032 //distinquish between crtc1/crtc2 once all heads get seperate driver instances!
1033 disable_vbi_all(di->regs);
1034
1035 /* preset we can't use INT related functions */
1036 si->ps.int_assigned = false;
1037
1038 /* create a semaphore for vertical blank management */
1039 si->vblank = create_sem(0, di->name);
1040 if (si->vblank < 0) goto mark_as_open;
1041
1042 /* change the owner of the semaphores to the opener's team */
1043 /* this is required because apps can't aquire kernel semaphores */
1044 thid = find_thread(NULL);
1045 get_thread_info(thid, &thinfo);
1046 set_sem_owner(si->vblank, thinfo.team);
1047
1048 /* If there is a valid interrupt line assigned then set up interrupts */
1049 if ((di->pcii.u.h0.interrupt_pin == 0x00) ||
1050 (di->pcii.u.h0.interrupt_line == 0xff) || /* no IRQ assigned */
1051 (di->pcii.u.h0.interrupt_line <= 0x02)) /* system IRQ assigned */
1052 {
1053 /* delete the semaphore as it won't be used */
1054 delete_sem(si->vblank);
1055 si->vblank = -1;
1056 }
1057 else
1058 {
1059 /* otherwise install our interrupt handler */
1060 result = install_io_interrupt_handler(di->pcii.u.h0.interrupt_line, nv_interrupt, (void *)di, 0);
1061 /* bail if we couldn't install the handler */
1062 if (result != B_OK)
1063 {
1064 /* delete the semaphore as it won't be used */
1065 delete_sem(si->vblank);
1066 si->vblank = -1;
1067 }
1068 else
1069 {
1070 /* inform accelerant(s) we can use INT related functions */
1071 si->ps.int_assigned = true;
1072 }
1073 }
1074
1075 mark_as_open:
1076 /* mark the device open */
1077 di->is_open++;
1078
1079 /* send the cookie to the opener */
1080 *cookie = di;
1081
1082 TRACE("open_hook: device is open\n");
1083 goto done;
1084
1085
1086 free_shared_and_alldma:
1087 /* clean up our aligned DMA area */
1088 delete_area(si->dma_area);
1089 si->dma_area = -1;
1090 si->dma_buffer = NULL;
1091
1092 free_shared_and_uadma:
1093 /* clean up our unaligned DMA area */
1094 delete_area(si->unaligned_dma_area);
1095 si->unaligned_dma_area = -1;
1096 si->dma_buffer_pci = NULL;
1097
1098 free_shared:
1099 /* clean up our shared area */
1100 delete_area(di->shared_area);
1101 di->shared_area = -1;
1102 di->si = NULL;
1103 TRACE("open_hook: device is freed\n");
1104
1105 done:
1106 /* end of critical section */
1107 RELEASE_BEN(pd->kernel);
1108
1109 /* all done, return the status */
1110 return result;
1111 }
1112
1113
1114 static status_t
read_hook(void * dev,off_t pos,void * buf,size_t * len)1115 read_hook(void* dev, off_t pos, void* buf, size_t* len)
1116 {
1117 *len = 0;
1118 return B_NOT_ALLOWED;
1119 }
1120
1121
1122 static status_t
write_hook(void * dev,off_t pos,const void * buf,size_t * len)1123 write_hook(void* dev, off_t pos, const void* buf, size_t* len)
1124 {
1125 *len = 0;
1126 return B_NOT_ALLOWED;
1127 }
1128
1129
1130 static status_t
close_hook(void * dev)1131 close_hook(void* dev)
1132 {
1133 CALLED();
1134 /* we don't do anything on close: there might be dup'd fd */
1135 return B_NO_ERROR;
1136 }
1137
1138
1139 static status_t
free_hook(void * dev)1140 free_hook(void* dev)
1141 {
1142 device_info *di = (device_info *)dev;
1143 shared_info *si = di->si;
1144 vuint32 *regs = di->regs;
1145
1146 CALLED();
1147 /* lock the driver */
1148 AQUIRE_BEN(pd->kernel);
1149
1150 /* if opened multiple times, decrement the open count and exit */
1151 if (di->is_open > 1)
1152 goto unlock_and_exit;
1153
1154 /* disable and clear any pending interrupts */
1155 //fixme:
1156 //distinquish between crtc1/crtc2 once all heads get seperate driver instances!
1157 disable_vbi_all(regs);
1158
1159 if (si->ps.int_assigned) {
1160 /* remove interrupt handler */
1161 remove_io_interrupt_handler(di->pcii.u.h0.interrupt_line, nv_interrupt, di);
1162
1163 /* delete the semaphores, ignoring any errors ('cause the owning
1164 team may have died on us) */
1165 delete_sem(si->vblank);
1166 si->vblank = -1;
1167 }
1168
1169 /* free regs and framebuffer areas */
1170 unmap_device(di);
1171
1172 /* clean up our aligned DMA area */
1173 delete_area(si->dma_area);
1174 si->dma_area = -1;
1175 si->dma_buffer = NULL;
1176
1177 /* clean up our unaligned DMA area */
1178 delete_area(si->unaligned_dma_area);
1179 si->unaligned_dma_area = -1;
1180 si->dma_buffer_pci = NULL;
1181
1182 /* clean up our shared area */
1183 delete_area(di->shared_area);
1184 di->shared_area = -1;
1185 di->si = NULL;
1186
1187 unlock_and_exit:
1188 /* mark the device available */
1189 di->is_open--;
1190 /* unlock the driver */
1191 RELEASE_BEN(pd->kernel);
1192 /* all done */
1193 return B_OK;
1194 }
1195
1196
1197 static status_t
control_hook(void * dev,uint32 msg,void * buf,size_t len)1198 control_hook(void* dev, uint32 msg, void *buf, size_t len)
1199 {
1200 device_info *di = (device_info *)dev;
1201 status_t result = B_DEV_INVALID_IOCTL;
1202 uint32 tmpUlong;
1203
1204 switch (msg) {
1205 /* the only PUBLIC ioctl */
1206 case B_GET_ACCELERANT_SIGNATURE: {
1207 TRACE("return signature\n");
1208 if (user_strlcpy((char* )buf, sSettings.accelerant, len) < B_OK)
1209 return B_BAD_ADDRESS;
1210 result = B_OK;
1211 break;
1212 }
1213
1214 /* PRIVATE ioctl from here on */
1215 case NV_GET_PRIVATE_DATA: {
1216 TRACE("return private data\n");
1217 nv_get_private_data gpd;
1218 if (user_memcpy(&gpd, buf, sizeof(nv_get_private_data)) < B_OK)
1219 return B_BAD_ADDRESS;
1220 if (gpd.magic == NV_PRIVATE_DATA_MAGIC) {
1221 gpd.shared_info_area = di->shared_area;
1222 result = user_memcpy(buf, &gpd, sizeof(nv_get_private_data));
1223 }
1224 break;
1225 }
1226 case NV_GET_PCI: {
1227 nv_get_set_pci gsp;
1228 if (user_memcpy(&gsp, buf, sizeof(nv_get_set_pci)) < B_OK)
1229 return B_BAD_ADDRESS;
1230 if (gsp.magic == NV_PRIVATE_DATA_MAGIC) {
1231 pci_info *pcii = &(di->pcii);
1232 gsp.value = get_pci(gsp.offset, gsp.size);
1233 result = user_memcpy(buf, &gsp, sizeof(nv_get_set_pci));
1234 }
1235 break;
1236 }
1237 case NV_SET_PCI: {
1238 nv_get_set_pci gsp;
1239 if (user_memcpy(&gsp, buf, sizeof(nv_get_set_pci)) < B_OK)
1240 return B_BAD_ADDRESS;
1241 if (gsp.magic == NV_PRIVATE_DATA_MAGIC) {
1242 pci_info *pcii = &(di->pcii);
1243 set_pci(gsp.offset, gsp.size, gsp.value);
1244 result = B_OK;
1245 }
1246 break;
1247 }
1248 case NV_DEVICE_NAME: {
1249 TRACE("return device name\n");
1250 nv_device_name dn;
1251 if (user_memcpy(&dn, buf, sizeof(nv_device_name)) < B_OK)
1252 return B_BAD_ADDRESS;
1253 if (dn.magic == NV_PRIVATE_DATA_MAGIC) {
1254 if (user_strlcpy(dn.name, di->name, B_OS_NAME_LENGTH) < B_OK)
1255 return B_BAD_ADDRESS;
1256 result = B_OK;
1257 }
1258 break;
1259 }
1260 case NV_RUN_INTERRUPTS: {
1261 nv_set_vblank_int vi;
1262 if (user_memcpy(&vi, buf, sizeof(nv_set_vblank_int)) < B_OK)
1263 return B_BAD_ADDRESS;
1264 if (vi.magic == NV_PRIVATE_DATA_MAGIC) {
1265 vuint32 *regs = di->regs;
1266 if (!(vi.crtc)) {
1267 if (vi.do_it) {
1268 enable_vbi_crtc1(regs);
1269 } else {
1270 disable_vbi_crtc1(regs);
1271 }
1272 } else {
1273 if (vi.do_it) {
1274 enable_vbi_crtc2(regs);
1275 } else {
1276 disable_vbi_crtc2(regs);
1277 }
1278 }
1279 result = B_OK;
1280 }
1281 break;
1282 }
1283 case NV_GET_NTH_AGP_INFO: {
1284 nv_nth_agp_info nai;
1285 if (user_memcpy(&nai, buf, sizeof(nv_nth_agp_info)) < B_OK)
1286 return B_BAD_ADDRESS;
1287 if (nai.magic == NV_PRIVATE_DATA_MAGIC) {
1288 nai.exist = false;
1289 nai.agp_bus = false;
1290 if (agp_bus) {
1291 nai.agp_bus = true;
1292 if ((*agp_bus->get_nth_agp_info)(nai.index, &(nai.agpi)) == B_NO_ERROR) {
1293 nai.exist = true;
1294 }
1295 }
1296 result = user_memcpy(buf, &nai, sizeof(nv_nth_agp_info));
1297 }
1298 break;
1299 }
1300 case NV_ENABLE_AGP: {
1301 nv_cmd_agp nca;
1302 if (user_memcpy(&nca, buf, sizeof(nv_cmd_agp)) < B_OK)
1303 return B_BAD_ADDRESS;
1304 if (nca.magic == NV_PRIVATE_DATA_MAGIC) {
1305 if (agp_bus) {
1306 nca.agp_bus = true;
1307 nca.cmd = agp_bus->set_agp_mode(nca.cmd);
1308 } else {
1309 nca.agp_bus = false;
1310 nca.cmd = 0;
1311 }
1312 result = user_memcpy(buf, &nca, sizeof(nv_cmd_agp));
1313 }
1314 break;
1315 }
1316 case NV_ISA_OUT: {
1317 nv_in_out_isa io_isa;
1318 if (user_memcpy(&io_isa, buf, sizeof(nv_in_out_isa)) < B_OK)
1319 return B_BAD_ADDRESS;
1320 if (io_isa.magic == NV_PRIVATE_DATA_MAGIC) {
1321 pci_info *pcii = &(di->pcii);
1322
1323 /* lock the driver:
1324 * no other graphics card may have ISA I/O enabled when we enter */
1325 AQUIRE_BEN(pd->kernel);
1326
1327 /* enable ISA I/O access */
1328 tmpUlong = get_pci(PCI_command, 2);
1329 tmpUlong |= PCI_command_io;
1330 set_pci(PCI_command, 2, tmpUlong);
1331
1332 if (io_isa.size == 1)
1333 isa_bus->write_io_8(io_isa.adress, (uint8)io_isa.data);
1334 else
1335 isa_bus->write_io_16(io_isa.adress, io_isa.data);
1336 result = B_OK;
1337
1338 /* disable ISA I/O access */
1339 tmpUlong = get_pci(PCI_command, 2);
1340 tmpUlong &= ~PCI_command_io;
1341 set_pci(PCI_command, 2, tmpUlong);
1342
1343 /* end of critical section */
1344 RELEASE_BEN(pd->kernel);
1345 }
1346 break;
1347 }
1348 case NV_ISA_IN: {
1349 nv_in_out_isa io_isa;
1350 if (user_memcpy(&io_isa, buf, sizeof(nv_in_out_isa)) < B_OK)
1351 return B_BAD_ADDRESS;
1352 if (io_isa.magic == NV_PRIVATE_DATA_MAGIC) {
1353 pci_info *pcii = &(di->pcii);
1354
1355 /* lock the driver:
1356 * no other graphics card may have ISA I/O enabled when we enter */
1357 AQUIRE_BEN(pd->kernel);
1358
1359 /* enable ISA I/O access */
1360 tmpUlong = get_pci(PCI_command, 2);
1361 tmpUlong |= PCI_command_io;
1362 set_pci(PCI_command, 2, tmpUlong);
1363
1364 if (io_isa.size == 1)
1365 io_isa.data = isa_bus->read_io_8(io_isa.adress);
1366 else
1367 io_isa.data = isa_bus->read_io_16(io_isa.adress);
1368 result = user_memcpy(buf, &io_isa, sizeof(nv_in_out_isa));
1369
1370 /* disable ISA I/O access */
1371 tmpUlong = get_pci(PCI_command, 2);
1372 tmpUlong &= ~PCI_command_io;
1373 set_pci(PCI_command, 2, tmpUlong);
1374
1375 /* end of critical section */
1376 RELEASE_BEN(pd->kernel);
1377 }
1378 break;
1379 }
1380 }
1381
1382 return result;
1383 }
1384
1385
1386 // #pragma mark - driver API
1387
1388
1389 status_t
init_hardware(void)1390 init_hardware(void)
1391 {
1392 long index = 0;
1393 pci_info pcii;
1394 bool found = false;
1395
1396 CALLED();
1397 /* choke if we can't find the PCI bus */
1398 if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK)
1399 return B_ERROR;
1400
1401 /* choke if we can't find the ISA bus */
1402 if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK)
1403 {
1404 put_module(B_PCI_MODULE_NAME);
1405 return B_ERROR;
1406 }
1407
1408 /* while there are more pci devices */
1409 while ((*pci_bus->get_nth_pci_info)(index, &pcii) == B_NO_ERROR) {
1410 int vendor = 0;
1411
1412 /* if we match a supported vendor */
1413 while (SupportedDevices[vendor].vendor) {
1414 if (SupportedDevices[vendor].vendor == pcii.vendor_id) {
1415 uint16 *devices = SupportedDevices[vendor].devices;
1416 /* while there are more supported devices */
1417 while (*devices) {
1418 /* if we match a supported device */
1419 if (*devices == pcii.device_id ) {
1420
1421 found = true;
1422 goto done;
1423 }
1424 /* next supported device */
1425 devices++;
1426 }
1427 }
1428 vendor++;
1429 }
1430 /* next pci_info struct, please */
1431 index++;
1432 }
1433
1434 done:
1435 if (found) {
1436 TRACE ("init_hardware: found device\n");
1437 } else {
1438 TRACE ("init_hardware: no supported device found\n");
1439 }
1440
1441 /* put away the module manager */
1442 put_module(B_PCI_MODULE_NAME);
1443 return found ? B_OK : B_ERROR;
1444 }
1445
1446
1447 status_t
init_driver(void)1448 init_driver(void)
1449 {
1450 void *settings;
1451
1452 CALLED();
1453 // get driver/accelerant settings
1454 settings = load_driver_settings(DRIVER_PREFIX ".settings");
1455 if (settings != NULL) {
1456 const char *item;
1457 char *end;
1458 uint32 value;
1459
1460 TRACE("init_driver: nvidia.settings loaded\n");
1461 // for driver
1462 item = get_driver_parameter(settings, "accelerant", "", "");
1463 if (item[0] && strlen(item) < sizeof(sSettings.accelerant) - 1)
1464 strcpy (sSettings.accelerant, item);
1465
1466 item = get_driver_parameter(settings, "primary", "", "");
1467 if (item[0] && strlen(item) < sizeof(sSettings.primary) - 1)
1468 strcpy(sSettings.primary, item);
1469
1470 sSettings.dumprom = get_driver_boolean_parameter(settings,
1471 "dumprom", false, false);
1472
1473 if (sSettings.dumprom) {
1474 TRACE("dumprom requested\n");
1475 } else {
1476 TRACE("no dumprom requested\n");
1477 }
1478
1479 // for accelerant
1480 item = get_driver_parameter(settings, "logmask",
1481 "0x00000000", "0x00000000");
1482 value = strtoul(item, &end, 0);
1483 if (*end == '\0')
1484 sSettings.logmask = value;
1485
1486 item = get_driver_parameter(settings, "memory", "0", "0");
1487 value = strtoul(item, &end, 0);
1488 if (*end == '\0')
1489 sSettings.memory = value;
1490
1491 item = get_driver_parameter(settings, "tv_output", "0", "0");
1492 value = strtoul(item, &end, 0);
1493 if (*end == '\0')
1494 sSettings.tv_output = value;
1495
1496 sSettings.hardcursor = get_driver_boolean_parameter(settings,
1497 "hardcursor", true, true);
1498 sSettings.usebios = get_driver_boolean_parameter(settings,
1499 "usebios", true, true);
1500 sSettings.switchhead = get_driver_boolean_parameter(settings,
1501 "switchhead", false, false);
1502 sSettings.force_pci = get_driver_boolean_parameter(settings,
1503 "force_pci", false, false);
1504 sSettings.unhide_fw = get_driver_boolean_parameter(settings,
1505 "unhide_fw", false, false);
1506 sSettings.pgm_panel = get_driver_boolean_parameter(settings,
1507 "pgm_panel", false, false);
1508 sSettings.dma_acc = get_driver_boolean_parameter(settings,
1509 "dma_acc", true, true);
1510 sSettings.vga_on_tv = get_driver_boolean_parameter(settings,
1511 "vga_on_tv", false, false);
1512 sSettings.force_sync = get_driver_boolean_parameter(settings,
1513 "force_sync", false, false);
1514 sSettings.force_ws = get_driver_boolean_parameter(settings,
1515 "force_ws", false, false);
1516 sSettings.block_acc = get_driver_boolean_parameter(settings,
1517 "block_acc", false, false);
1518 sSettings.check_edid = get_driver_boolean_parameter(settings,
1519 "check_edid", true, true);
1520
1521 item = get_driver_parameter(settings, "gpu_clk", "0", "0");
1522 value = strtoul(item, &end, 0);
1523 if (*end == '\0')
1524 sSettings.gpu_clk = value;
1525
1526 item = get_driver_parameter(settings, "ram_clk", "0", "0");
1527 value = strtoul(item, &end, 0);
1528 if (*end == '\0')
1529 sSettings.ram_clk = value;
1530
1531 unload_driver_settings(settings);
1532 }
1533
1534 /* get a handle for the pci bus */
1535 if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK)
1536 return B_ERROR;
1537
1538 /* get a handle for the isa bus */
1539 if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK) {
1540 put_module(B_PCI_MODULE_NAME);
1541 return B_ERROR;
1542 }
1543
1544 /* get a handle for the agp bus if it exists */
1545 get_module(B_AGP_GART_MODULE_NAME, (module_info **)&agp_bus);
1546
1547 /* driver private data */
1548 pd = (DeviceData *)calloc(1, sizeof(DeviceData));
1549 if (!pd) {
1550 put_module(B_PCI_MODULE_NAME);
1551 return B_ERROR;
1552 }
1553 /* initialize the benaphore */
1554 INIT_BEN(pd->kernel);
1555 /* find all of our supported devices */
1556 probe_devices();
1557
1558 TRACE("init_driver: completed OK\n");
1559 return B_OK;
1560 }
1561
1562
1563 const char **
publish_devices(void)1564 publish_devices(void)
1565 {
1566 CALLED();
1567 /* return the list of supported devices */
1568 return (const char **)pd->device_names;
1569 }
1570
1571
1572 device_hooks *
find_device(const char * name)1573 find_device(const char *name)
1574 {
1575 int index = 0;
1576 while (pd->device_names[index]) {
1577 if (strcmp(name, pd->device_names[index]) == 0)
1578 return &graphics_device_hooks;
1579 index++;
1580 }
1581 return NULL;
1582
1583 }
1584
1585
1586 void
uninit_driver(void)1587 uninit_driver(void)
1588 {
1589 CALLED();
1590 /* free the driver data */
1591 DELETE_BEN(pd->kernel);
1592 free(pd);
1593 pd = NULL;
1594
1595 /* put the pci module away */
1596 put_module(B_PCI_MODULE_NAME);
1597 put_module(B_ISA_MODULE_NAME);
1598
1599 /* put the agp module away if it's there */
1600 if (agp_bus)
1601 put_module(B_AGP_GART_MODULE_NAME);
1602 }
1603
1604