1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright (c) 2007 The DragonFly Project. All rights reserved.
5 *
6 * This code is derived from software contributed to The DragonFly Project
7 * by Sepherosa Ziehau <sepherosa@gmail.com>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 *
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in
17 * the documentation and/or other materials provided with the
18 * distribution.
19 * 3. Neither the name of The DragonFly Project nor the names of its
20 * contributors may be used to endorse or promote products derived
21 * from this software without specific, prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
25 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
26 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
27 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
28 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
29 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
31 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
33 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 *
36 * $DragonFly: src/sys/dev/netif/bwi/if_bwi.c,v 1.19 2008/02/15 11:15:38 sephe Exp $
37 */
38
39 #include <sys/cdefs.h>
40 #include "opt_inet.h"
41 #include "opt_bwi.h"
42 #include "opt_wlan.h"
43
44 #include <sys/param.h>
45 #include <sys/endian.h>
46 #include <sys/kernel.h>
47 #include <sys/bus.h>
48 #include <sys/malloc.h>
49 #include <sys/proc.h>
50 #include <sys/rman.h>
51 #include <sys/socket.h>
52 #include <sys/sockio.h>
53 #include <sys/sysctl.h>
54 #include <sys/systm.h>
55 #include <sys/taskqueue.h>
56
57 #include <net/if.h>
58 #include <net/if_var.h>
59 #include <net/if_dl.h>
60 #include <net/if_media.h>
61 #include <net/if_types.h>
62 #include <net/if_arp.h>
63 #include <net/ethernet.h>
64 #include <net/if_llc.h>
65
66 #include <net80211/ieee80211_var.h>
67 #include <net80211/ieee80211_radiotap.h>
68 #include <net80211/ieee80211_regdomain.h>
69 #include <net80211/ieee80211_phy.h>
70 #include <net80211/ieee80211_ratectl.h>
71
72 #include <net/bpf.h>
73
74 #ifdef INET
75 #include <netinet/in.h>
76 #include <netinet/if_ether.h>
77 #endif
78
79 #include <machine/bus.h>
80
81 #include <dev/pci/pcivar.h>
82 #include <dev/pci/pcireg.h>
83
84 #include <dev/bwi/bitops.h>
85 #include <dev/bwi/if_bwireg.h>
86 #include <dev/bwi/if_bwivar.h>
87 #include <dev/bwi/bwimac.h>
88 #include <dev/bwi/bwirf.h>
89
90 struct bwi_clock_freq {
91 u_int clkfreq_min;
92 u_int clkfreq_max;
93 };
94
95 struct bwi_myaddr_bssid {
96 uint8_t myaddr[IEEE80211_ADDR_LEN];
97 uint8_t bssid[IEEE80211_ADDR_LEN];
98 } __packed;
99
100 static struct ieee80211vap *bwi_vap_create(struct ieee80211com *,
101 const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
102 const uint8_t [IEEE80211_ADDR_LEN],
103 const uint8_t [IEEE80211_ADDR_LEN]);
104 static void bwi_vap_delete(struct ieee80211vap *);
105 static void bwi_init(struct bwi_softc *);
106 static void bwi_parent(struct ieee80211com *);
107 static int bwi_transmit(struct ieee80211com *, struct mbuf *);
108 static void bwi_start_locked(struct bwi_softc *);
109 static int bwi_raw_xmit(struct ieee80211_node *, struct mbuf *,
110 const struct ieee80211_bpf_params *);
111 static void bwi_watchdog(void *);
112 static void bwi_scan_start(struct ieee80211com *);
113 static void bwi_getradiocaps(struct ieee80211com *, int, int *,
114 struct ieee80211_channel[]);
115 static void bwi_set_channel(struct ieee80211com *);
116 static void bwi_scan_end(struct ieee80211com *);
117 static int bwi_newstate(struct ieee80211vap *, enum ieee80211_state, int);
118 static void bwi_updateslot(struct ieee80211com *);
119
120 static void bwi_calibrate(void *);
121
122 static int bwi_calc_rssi(struct bwi_softc *, const struct bwi_rxbuf_hdr *);
123 static int bwi_calc_noise(struct bwi_softc *);
124 static __inline uint8_t bwi_plcp2rate(uint32_t, enum ieee80211_phytype);
125 static void bwi_rx_radiotap(struct bwi_softc *, struct mbuf *,
126 struct bwi_rxbuf_hdr *, const void *, int, int, int);
127
128 static void bwi_restart(void *, int);
129 static void bwi_init_statechg(struct bwi_softc *, int);
130 static void bwi_stop(struct bwi_softc *, int);
131 static void bwi_stop_locked(struct bwi_softc *, int);
132 static int bwi_newbuf(struct bwi_softc *, int, int);
133 static int bwi_encap(struct bwi_softc *, int, struct mbuf *,
134 struct ieee80211_node *);
135 static int bwi_encap_raw(struct bwi_softc *, int, struct mbuf *,
136 struct ieee80211_node *,
137 const struct ieee80211_bpf_params *);
138
139 static void bwi_init_rxdesc_ring32(struct bwi_softc *, uint32_t,
140 bus_addr_t, int, int);
141 static void bwi_reset_rx_ring32(struct bwi_softc *, uint32_t);
142
143 static int bwi_init_tx_ring32(struct bwi_softc *, int);
144 static int bwi_init_rx_ring32(struct bwi_softc *);
145 static int bwi_init_txstats32(struct bwi_softc *);
146 static void bwi_free_tx_ring32(struct bwi_softc *, int);
147 static void bwi_free_rx_ring32(struct bwi_softc *);
148 static void bwi_free_txstats32(struct bwi_softc *);
149 static void bwi_setup_rx_desc32(struct bwi_softc *, int, bus_addr_t, int);
150 static void bwi_setup_tx_desc32(struct bwi_softc *, struct bwi_ring_data *,
151 int, bus_addr_t, int);
152 static int bwi_rxeof32(struct bwi_softc *);
153 static void bwi_start_tx32(struct bwi_softc *, uint32_t, int);
154 static void bwi_txeof_status32(struct bwi_softc *);
155
156 static int bwi_init_tx_ring64(struct bwi_softc *, int);
157 static int bwi_init_rx_ring64(struct bwi_softc *);
158 static int bwi_init_txstats64(struct bwi_softc *);
159 static void bwi_free_tx_ring64(struct bwi_softc *, int);
160 static void bwi_free_rx_ring64(struct bwi_softc *);
161 static void bwi_free_txstats64(struct bwi_softc *);
162 static void bwi_setup_rx_desc64(struct bwi_softc *, int, bus_addr_t, int);
163 static void bwi_setup_tx_desc64(struct bwi_softc *, struct bwi_ring_data *,
164 int, bus_addr_t, int);
165 static int bwi_rxeof64(struct bwi_softc *);
166 static void bwi_start_tx64(struct bwi_softc *, uint32_t, int);
167 static void bwi_txeof_status64(struct bwi_softc *);
168
169 static int bwi_rxeof(struct bwi_softc *, int);
170 static void _bwi_txeof(struct bwi_softc *, uint16_t, int, int);
171 static void bwi_txeof(struct bwi_softc *);
172 static void bwi_txeof_status(struct bwi_softc *, int);
173 static void bwi_enable_intrs(struct bwi_softc *, uint32_t);
174 static void bwi_disable_intrs(struct bwi_softc *, uint32_t);
175
176 static int bwi_dma_alloc(struct bwi_softc *);
177 static void bwi_dma_free(struct bwi_softc *);
178 static int bwi_dma_ring_alloc(struct bwi_softc *, bus_dma_tag_t,
179 struct bwi_ring_data *, bus_size_t,
180 uint32_t);
181 static int bwi_dma_mbuf_create(struct bwi_softc *);
182 static void bwi_dma_mbuf_destroy(struct bwi_softc *, int, int);
183 static int bwi_dma_txstats_alloc(struct bwi_softc *, uint32_t, bus_size_t);
184 static void bwi_dma_txstats_free(struct bwi_softc *);
185 static void bwi_dma_ring_addr(void *, bus_dma_segment_t *, int, int);
186 static void bwi_dma_buf_addr(void *, bus_dma_segment_t *, int,
187 bus_size_t, int);
188
189 static void bwi_power_on(struct bwi_softc *, int);
190 static int bwi_power_off(struct bwi_softc *, int);
191 static int bwi_set_clock_mode(struct bwi_softc *, enum bwi_clock_mode);
192 static int bwi_set_clock_delay(struct bwi_softc *);
193 static void bwi_get_clock_freq(struct bwi_softc *, struct bwi_clock_freq *);
194 static int bwi_get_pwron_delay(struct bwi_softc *sc);
195 static void bwi_set_addr_filter(struct bwi_softc *, uint16_t,
196 const uint8_t *);
197 static void bwi_set_bssid(struct bwi_softc *, const uint8_t *);
198
199 static void bwi_get_card_flags(struct bwi_softc *);
200 static void bwi_get_eaddr(struct bwi_softc *, uint16_t, uint8_t *);
201
202 static int bwi_bus_attach(struct bwi_softc *);
203 static int bwi_bbp_attach(struct bwi_softc *);
204 static int bwi_bbp_power_on(struct bwi_softc *, enum bwi_clock_mode);
205 static void bwi_bbp_power_off(struct bwi_softc *);
206
207 static const char *bwi_regwin_name(const struct bwi_regwin *);
208 static uint32_t bwi_regwin_disable_bits(struct bwi_softc *);
209 static void bwi_regwin_info(struct bwi_softc *, uint16_t *, uint8_t *);
210 static int bwi_regwin_select(struct bwi_softc *, int);
211
212 static void bwi_led_attach(struct bwi_softc *);
213 static void bwi_led_newstate(struct bwi_softc *, enum ieee80211_state);
214 static void bwi_led_event(struct bwi_softc *, int);
215 static void bwi_led_blink_start(struct bwi_softc *, int, int);
216 static void bwi_led_blink_next(void *);
217 static void bwi_led_blink_end(void *);
218
219 static const struct {
220 uint16_t did_min;
221 uint16_t did_max;
222 uint16_t bbp_id;
223 } bwi_bbpid_map[] = {
224 { 0x4301, 0x4301, 0x4301 },
225 { 0x4305, 0x4307, 0x4307 },
226 { 0x4402, 0x4403, 0x4402 },
227 { 0x4610, 0x4615, 0x4610 },
228 { 0x4710, 0x4715, 0x4710 },
229 { 0x4720, 0x4725, 0x4309 }
230 };
231
232 static const struct {
233 uint16_t bbp_id;
234 int nregwin;
235 } bwi_regwin_count[] = {
236 { 0x4301, 5 },
237 { 0x4306, 6 },
238 { 0x4307, 5 },
239 { 0x4310, 8 },
240 { 0x4401, 3 },
241 { 0x4402, 3 },
242 { 0x4610, 9 },
243 { 0x4704, 9 },
244 { 0x4710, 9 },
245 { 0x5365, 7 }
246 };
247
248 #define CLKSRC(src) \
249 [BWI_CLKSRC_ ## src] = { \
250 .freq_min = BWI_CLKSRC_ ##src## _FMIN, \
251 .freq_max = BWI_CLKSRC_ ##src## _FMAX \
252 }
253
254 static const struct {
255 u_int freq_min;
256 u_int freq_max;
257 } bwi_clkfreq[BWI_CLKSRC_MAX] = {
258 CLKSRC(LP_OSC),
259 CLKSRC(CS_OSC),
260 CLKSRC(PCI)
261 };
262
263 #undef CLKSRC
264
265 #define VENDOR_LED_ACT(vendor) \
266 { \
267 .vid = PCI_VENDOR_##vendor, \
268 .led_act = { BWI_VENDOR_LED_ACT_##vendor } \
269 }
270
271 static const struct {
272 #define PCI_VENDOR_COMPAQ 0x0e11
273 #define PCI_VENDOR_LINKSYS 0x1737
274 uint16_t vid;
275 uint8_t led_act[BWI_LED_MAX];
276 } bwi_vendor_led_act[] = {
277 VENDOR_LED_ACT(COMPAQ),
278 VENDOR_LED_ACT(LINKSYS)
279 #undef PCI_VENDOR_LINKSYS
280 #undef PCI_VENDOR_COMPAQ
281 };
282
283 static const uint8_t bwi_default_led_act[BWI_LED_MAX] =
284 { BWI_VENDOR_LED_ACT_DEFAULT };
285
286 #undef VENDOR_LED_ACT
287
288 static const struct {
289 int on_dur;
290 int off_dur;
291 } bwi_led_duration[109] = {
292 [0] = { 400, 100 },
293 [2] = { 150, 75 },
294 [4] = { 90, 45 },
295 [11] = { 66, 34 },
296 [12] = { 53, 26 },
297 [18] = { 42, 21 },
298 [22] = { 35, 17 },
299 [24] = { 32, 16 },
300 [36] = { 21, 10 },
301 [48] = { 16, 8 },
302 [72] = { 11, 5 },
303 [96] = { 9, 4 },
304 [108] = { 7, 3 }
305 };
306
307 #ifdef BWI_DEBUG
308 #ifdef BWI_DEBUG_VERBOSE
309 static uint32_t bwi_debug = BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_TXPOWER;
310 #else
311 static uint32_t bwi_debug;
312 #endif
313 TUNABLE_INT("hw.bwi.debug", (int *)&bwi_debug);
314 #endif /* BWI_DEBUG */
315
316 static const uint8_t bwi_zero_addr[IEEE80211_ADDR_LEN];
317
318 uint16_t
bwi_read_sprom(struct bwi_softc * sc,uint16_t ofs)319 bwi_read_sprom(struct bwi_softc *sc, uint16_t ofs)
320 {
321 return CSR_READ_2(sc, ofs + BWI_SPROM_START);
322 }
323
324 static __inline void
bwi_setup_desc32(struct bwi_softc * sc,struct bwi_desc32 * desc_array,int ndesc,int desc_idx,bus_addr_t paddr,int buf_len,int tx)325 bwi_setup_desc32(struct bwi_softc *sc, struct bwi_desc32 *desc_array,
326 int ndesc, int desc_idx, bus_addr_t paddr, int buf_len,
327 int tx)
328 {
329 struct bwi_desc32 *desc = &desc_array[desc_idx];
330 uint32_t ctrl, addr, addr_hi, addr_lo;
331
332 addr_lo = __SHIFTOUT(paddr, BWI_DESC32_A_ADDR_MASK);
333 addr_hi = __SHIFTOUT(paddr, BWI_DESC32_A_FUNC_MASK);
334
335 addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) |
336 __SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK);
337
338 ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) |
339 __SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK);
340 if (desc_idx == ndesc - 1)
341 ctrl |= BWI_DESC32_C_EOR;
342 if (tx) {
343 /* XXX */
344 ctrl |= BWI_DESC32_C_FRAME_START |
345 BWI_DESC32_C_FRAME_END |
346 BWI_DESC32_C_INTR;
347 }
348
349 desc->addr = htole32(addr);
350 desc->ctrl = htole32(ctrl);
351 }
352
353 int
bwi_attach(struct bwi_softc * sc)354 bwi_attach(struct bwi_softc *sc)
355 {
356 struct ieee80211com *ic = &sc->sc_ic;
357 device_t dev = sc->sc_dev;
358 struct bwi_mac *mac;
359 struct bwi_phy *phy;
360 int i, error;
361
362 BWI_LOCK_INIT(sc);
363
364 /*
365 * Initialize taskq and various tasks
366 */
367 sc->sc_tq = taskqueue_create("bwi_taskq", M_NOWAIT | M_ZERO,
368 taskqueue_thread_enqueue, &sc->sc_tq);
369 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq",
370 device_get_nameunit(dev));
371 TASK_INIT(&sc->sc_restart_task, 0, bwi_restart, sc);
372 callout_init_mtx(&sc->sc_calib_ch, &sc->sc_mtx, 0);
373 mbufq_init(&sc->sc_snd, ifqmaxlen);
374
375 /*
376 * Initialize sysctl variables
377 */
378 sc->sc_fw_version = BWI_FW_VERSION3;
379 sc->sc_led_idle = (2350 * hz) / 1000;
380 sc->sc_led_ticks = ticks - sc->sc_led_idle;
381 sc->sc_led_blink = 1;
382 sc->sc_txpwr_calib = 1;
383 #ifdef BWI_DEBUG
384 sc->sc_debug = bwi_debug;
385 #endif
386 bwi_power_on(sc, 1);
387
388 error = bwi_bbp_attach(sc);
389 if (error)
390 goto fail;
391
392 error = bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
393 if (error)
394 goto fail;
395
396 if (BWI_REGWIN_EXIST(&sc->sc_com_regwin)) {
397 error = bwi_set_clock_delay(sc);
398 if (error)
399 goto fail;
400
401 error = bwi_set_clock_mode(sc, BWI_CLOCK_MODE_FAST);
402 if (error)
403 goto fail;
404
405 error = bwi_get_pwron_delay(sc);
406 if (error)
407 goto fail;
408 }
409
410 error = bwi_bus_attach(sc);
411 if (error)
412 goto fail;
413
414 bwi_get_card_flags(sc);
415
416 bwi_led_attach(sc);
417
418 for (i = 0; i < sc->sc_nmac; ++i) {
419 struct bwi_regwin *old;
420
421 mac = &sc->sc_mac[i];
422 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old);
423 if (error)
424 goto fail;
425
426 error = bwi_mac_lateattach(mac);
427 if (error)
428 goto fail;
429
430 error = bwi_regwin_switch(sc, old, NULL);
431 if (error)
432 goto fail;
433 }
434
435 /*
436 * XXX First MAC is known to exist
437 * TODO2
438 */
439 mac = &sc->sc_mac[0];
440 phy = &mac->mac_phy;
441
442 bwi_bbp_power_off(sc);
443
444 error = bwi_dma_alloc(sc);
445 if (error)
446 goto fail;
447
448 error = bwi_mac_fw_alloc(mac);
449 if (error)
450 goto fail;
451
452 callout_init_mtx(&sc->sc_watchdog_timer, &sc->sc_mtx, 0);
453
454 /*
455 * Setup ratesets, phytype, channels and get MAC address
456 */
457 if (phy->phy_mode == IEEE80211_MODE_11B ||
458 phy->phy_mode == IEEE80211_MODE_11G) {
459 if (phy->phy_mode == IEEE80211_MODE_11B) {
460 ic->ic_phytype = IEEE80211_T_DS;
461 } else {
462 ic->ic_phytype = IEEE80211_T_OFDM;
463 }
464
465 bwi_get_eaddr(sc, BWI_SPROM_11BG_EADDR, ic->ic_macaddr);
466 if (IEEE80211_IS_MULTICAST(ic->ic_macaddr)) {
467 bwi_get_eaddr(sc, BWI_SPROM_11A_EADDR, ic->ic_macaddr);
468 if (IEEE80211_IS_MULTICAST(ic->ic_macaddr)) {
469 device_printf(dev,
470 "invalid MAC address: %6D\n",
471 ic->ic_macaddr, ":");
472 }
473 }
474 } else if (phy->phy_mode == IEEE80211_MODE_11A) {
475 /* TODO:11A */
476 error = ENXIO;
477 goto fail;
478 } else {
479 panic("unknown phymode %d\n", phy->phy_mode);
480 }
481
482 /* Get locale */
483 sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO),
484 BWI_SPROM_CARD_INFO_LOCALE);
485 DPRINTF(sc, BWI_DBG_ATTACH, "locale: %d\n", sc->sc_locale);
486 /* XXX use locale */
487
488 ic->ic_softc = sc;
489
490 bwi_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans,
491 ic->ic_channels);
492
493 ic->ic_name = device_get_nameunit(dev);
494 ic->ic_caps = IEEE80211_C_STA |
495 IEEE80211_C_SHSLOT |
496 IEEE80211_C_SHPREAMBLE |
497 IEEE80211_C_WPA |
498 IEEE80211_C_BGSCAN |
499 IEEE80211_C_MONITOR;
500 ic->ic_opmode = IEEE80211_M_STA;
501 ieee80211_ifattach(ic);
502
503 ic->ic_headroom = sizeof(struct bwi_txbuf_hdr);
504
505 /* override default methods */
506 ic->ic_vap_create = bwi_vap_create;
507 ic->ic_vap_delete = bwi_vap_delete;
508 ic->ic_raw_xmit = bwi_raw_xmit;
509 ic->ic_updateslot = bwi_updateslot;
510 ic->ic_scan_start = bwi_scan_start;
511 ic->ic_scan_end = bwi_scan_end;
512 ic->ic_getradiocaps = bwi_getradiocaps;
513 ic->ic_set_channel = bwi_set_channel;
514 ic->ic_transmit = bwi_transmit;
515 ic->ic_parent = bwi_parent;
516
517 sc->sc_rates = ieee80211_get_ratetable(ic->ic_curchan);
518
519 ieee80211_radiotap_attach(ic,
520 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th),
521 BWI_TX_RADIOTAP_PRESENT,
522 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th),
523 BWI_RX_RADIOTAP_PRESENT);
524
525 /*
526 * Add sysctl nodes
527 */
528 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
529 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
530 "fw_version", CTLFLAG_RD, &sc->sc_fw_version, 0,
531 "Firmware version");
532 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
533 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
534 "led_idle", CTLFLAG_RW, &sc->sc_led_idle, 0,
535 "# ticks before LED enters idle state");
536 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
537 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
538 "led_blink", CTLFLAG_RW, &sc->sc_led_blink, 0,
539 "Allow LED to blink");
540 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
541 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
542 "txpwr_calib", CTLFLAG_RW, &sc->sc_txpwr_calib, 0,
543 "Enable software TX power calibration");
544 #ifdef BWI_DEBUG
545 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
546 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
547 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags");
548 #endif
549 if (bootverbose)
550 ieee80211_announce(ic);
551
552 return (0);
553 fail:
554 BWI_LOCK_DESTROY(sc);
555 return (error);
556 }
557
558 int
bwi_detach(struct bwi_softc * sc)559 bwi_detach(struct bwi_softc *sc)
560 {
561 struct ieee80211com *ic = &sc->sc_ic;
562 int i;
563
564 bwi_stop(sc, 1);
565 callout_drain(&sc->sc_led_blink_ch);
566 callout_drain(&sc->sc_calib_ch);
567 callout_drain(&sc->sc_watchdog_timer);
568 ieee80211_ifdetach(ic);
569
570 for (i = 0; i < sc->sc_nmac; ++i)
571 bwi_mac_detach(&sc->sc_mac[i]);
572 bwi_dma_free(sc);
573 taskqueue_free(sc->sc_tq);
574 mbufq_drain(&sc->sc_snd);
575
576 BWI_LOCK_DESTROY(sc);
577
578 return (0);
579 }
580
581 static struct ieee80211vap *
bwi_vap_create(struct ieee80211com * ic,const char name[IFNAMSIZ],int unit,enum ieee80211_opmode opmode,int flags,const uint8_t bssid[IEEE80211_ADDR_LEN],const uint8_t mac[IEEE80211_ADDR_LEN])582 bwi_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
583 enum ieee80211_opmode opmode, int flags,
584 const uint8_t bssid[IEEE80211_ADDR_LEN],
585 const uint8_t mac[IEEE80211_ADDR_LEN])
586 {
587 struct bwi_vap *bvp;
588 struct ieee80211vap *vap;
589
590 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */
591 return NULL;
592 bvp = malloc(sizeof(struct bwi_vap), M_80211_VAP, M_WAITOK | M_ZERO);
593 vap = &bvp->bv_vap;
594 /* enable s/w bmiss handling for sta mode */
595 ieee80211_vap_setup(ic, vap, name, unit, opmode,
596 flags | IEEE80211_CLONE_NOBEACONS, bssid);
597
598 /* override default methods */
599 bvp->bv_newstate = vap->iv_newstate;
600 vap->iv_newstate = bwi_newstate;
601 #if 0
602 vap->iv_update_beacon = bwi_beacon_update;
603 #endif
604 ieee80211_ratectl_init(vap);
605
606 /* complete setup */
607 ieee80211_vap_attach(vap, ieee80211_media_change,
608 ieee80211_media_status, mac);
609 ic->ic_opmode = opmode;
610 return vap;
611 }
612
613 static void
bwi_vap_delete(struct ieee80211vap * vap)614 bwi_vap_delete(struct ieee80211vap *vap)
615 {
616 struct bwi_vap *bvp = BWI_VAP(vap);
617
618 ieee80211_ratectl_deinit(vap);
619 ieee80211_vap_detach(vap);
620 free(bvp, M_80211_VAP);
621 }
622
623 void
bwi_suspend(struct bwi_softc * sc)624 bwi_suspend(struct bwi_softc *sc)
625 {
626 bwi_stop(sc, 1);
627 }
628
629 void
bwi_resume(struct bwi_softc * sc)630 bwi_resume(struct bwi_softc *sc)
631 {
632
633 if (sc->sc_ic.ic_nrunning > 0)
634 bwi_init(sc);
635 }
636
637 int
bwi_shutdown(struct bwi_softc * sc)638 bwi_shutdown(struct bwi_softc *sc)
639 {
640 bwi_stop(sc, 1);
641 return 0;
642 }
643
644 static void
bwi_power_on(struct bwi_softc * sc,int with_pll)645 bwi_power_on(struct bwi_softc *sc, int with_pll)
646 {
647 uint32_t gpio_in, gpio_out, gpio_en;
648 uint16_t status;
649
650 gpio_in = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4);
651 if (gpio_in & BWI_PCIM_GPIO_PWR_ON)
652 goto back;
653
654 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
655 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
656
657 gpio_out |= BWI_PCIM_GPIO_PWR_ON;
658 gpio_en |= BWI_PCIM_GPIO_PWR_ON;
659 if (with_pll) {
660 /* Turn off PLL first */
661 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
662 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
663 }
664
665 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
666 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
667 DELAY(1000);
668
669 if (with_pll) {
670 /* Turn on PLL */
671 gpio_out &= ~BWI_PCIM_GPIO_PLL_PWR_OFF;
672 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
673 DELAY(5000);
674 }
675
676 back:
677 /* Clear "Signaled Target Abort" */
678 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2);
679 status &= ~PCIM_STATUS_STABORT;
680 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2);
681 }
682
683 static int
bwi_power_off(struct bwi_softc * sc,int with_pll)684 bwi_power_off(struct bwi_softc *sc, int with_pll)
685 {
686 uint32_t gpio_out, gpio_en;
687
688 pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); /* dummy read */
689 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
690 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
691
692 gpio_out &= ~BWI_PCIM_GPIO_PWR_ON;
693 gpio_en |= BWI_PCIM_GPIO_PWR_ON;
694 if (with_pll) {
695 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
696 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
697 }
698
699 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
700 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
701 return 0;
702 }
703
704 int
bwi_regwin_switch(struct bwi_softc * sc,struct bwi_regwin * rw,struct bwi_regwin ** old_rw)705 bwi_regwin_switch(struct bwi_softc *sc, struct bwi_regwin *rw,
706 struct bwi_regwin **old_rw)
707 {
708 int error;
709
710 if (old_rw != NULL)
711 *old_rw = NULL;
712
713 if (!BWI_REGWIN_EXIST(rw))
714 return EINVAL;
715
716 if (sc->sc_cur_regwin != rw) {
717 error = bwi_regwin_select(sc, rw->rw_id);
718 if (error) {
719 device_printf(sc->sc_dev, "can't select regwin %d\n",
720 rw->rw_id);
721 return error;
722 }
723 }
724
725 if (old_rw != NULL)
726 *old_rw = sc->sc_cur_regwin;
727 sc->sc_cur_regwin = rw;
728 return 0;
729 }
730
731 static int
bwi_regwin_select(struct bwi_softc * sc,int id)732 bwi_regwin_select(struct bwi_softc *sc, int id)
733 {
734 uint32_t win = BWI_PCIM_REGWIN(id);
735 int i;
736
737 #define RETRY_MAX 50
738 for (i = 0; i < RETRY_MAX; ++i) {
739 pci_write_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, win, 4);
740 if (pci_read_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, 4) == win)
741 return 0;
742 DELAY(10);
743 }
744 #undef RETRY_MAX
745
746 return ENXIO;
747 }
748
749 static void
bwi_regwin_info(struct bwi_softc * sc,uint16_t * type,uint8_t * rev)750 bwi_regwin_info(struct bwi_softc *sc, uint16_t *type, uint8_t *rev)
751 {
752 uint32_t val;
753
754 val = CSR_READ_4(sc, BWI_ID_HI);
755 *type = BWI_ID_HI_REGWIN_TYPE(val);
756 *rev = BWI_ID_HI_REGWIN_REV(val);
757
758 DPRINTF(sc, BWI_DBG_ATTACH, "regwin: type 0x%03x, rev %d, "
759 "vendor 0x%04x\n", *type, *rev,
760 __SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK));
761 }
762
763 static int
bwi_bbp_attach(struct bwi_softc * sc)764 bwi_bbp_attach(struct bwi_softc *sc)
765 {
766 uint16_t bbp_id, rw_type;
767 uint8_t rw_rev;
768 uint32_t info;
769 int error, nregwin, i;
770
771 /*
772 * Get 0th regwin information
773 * NOTE: 0th regwin should exist
774 */
775 error = bwi_regwin_select(sc, 0);
776 if (error) {
777 device_printf(sc->sc_dev, "can't select regwin 0\n");
778 return error;
779 }
780 bwi_regwin_info(sc, &rw_type, &rw_rev);
781
782 /*
783 * Find out BBP id
784 */
785 bbp_id = 0;
786 info = 0;
787 if (rw_type == BWI_REGWIN_T_COM) {
788 info = CSR_READ_4(sc, BWI_INFO);
789 bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK);
790
791 BWI_CREATE_REGWIN(&sc->sc_com_regwin, 0, rw_type, rw_rev);
792
793 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY);
794 } else {
795 for (i = 0; i < nitems(bwi_bbpid_map); ++i) {
796 if (sc->sc_pci_did >= bwi_bbpid_map[i].did_min &&
797 sc->sc_pci_did <= bwi_bbpid_map[i].did_max) {
798 bbp_id = bwi_bbpid_map[i].bbp_id;
799 break;
800 }
801 }
802 if (bbp_id == 0) {
803 device_printf(sc->sc_dev, "no BBP id for device id "
804 "0x%04x\n", sc->sc_pci_did);
805 return ENXIO;
806 }
807
808 info = __SHIFTIN(sc->sc_pci_revid, BWI_INFO_BBPREV_MASK) |
809 __SHIFTIN(0, BWI_INFO_BBPPKG_MASK);
810 }
811
812 /*
813 * Find out number of regwins
814 */
815 nregwin = 0;
816 if (rw_type == BWI_REGWIN_T_COM && rw_rev >= 4) {
817 nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK);
818 } else {
819 for (i = 0; i < nitems(bwi_regwin_count); ++i) {
820 if (bwi_regwin_count[i].bbp_id == bbp_id) {
821 nregwin = bwi_regwin_count[i].nregwin;
822 break;
823 }
824 }
825 if (nregwin == 0) {
826 device_printf(sc->sc_dev, "no number of win for "
827 "BBP id 0x%04x\n", bbp_id);
828 return ENXIO;
829 }
830 }
831
832 /* Record BBP id/rev for later using */
833 sc->sc_bbp_id = bbp_id;
834 sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK);
835 sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK);
836 device_printf(sc->sc_dev, "BBP: id 0x%04x, rev 0x%x, pkg %d\n",
837 sc->sc_bbp_id, sc->sc_bbp_rev, sc->sc_bbp_pkg);
838
839 DPRINTF(sc, BWI_DBG_ATTACH, "nregwin %d, cap 0x%08x\n",
840 nregwin, sc->sc_cap);
841
842 /*
843 * Create rest of the regwins
844 */
845
846 /* Don't re-create common regwin, if it is already created */
847 i = BWI_REGWIN_EXIST(&sc->sc_com_regwin) ? 1 : 0;
848
849 for (; i < nregwin; ++i) {
850 /*
851 * Get regwin information
852 */
853 error = bwi_regwin_select(sc, i);
854 if (error) {
855 device_printf(sc->sc_dev,
856 "can't select regwin %d\n", i);
857 return error;
858 }
859 bwi_regwin_info(sc, &rw_type, &rw_rev);
860
861 /*
862 * Try attach:
863 * 1) Bus (PCI/PCIE) regwin
864 * 2) MAC regwin
865 * Ignore rest types of regwin
866 */
867 if (rw_type == BWI_REGWIN_T_BUSPCI ||
868 rw_type == BWI_REGWIN_T_BUSPCIE) {
869 if (BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
870 device_printf(sc->sc_dev,
871 "bus regwin already exists\n");
872 } else {
873 BWI_CREATE_REGWIN(&sc->sc_bus_regwin, i,
874 rw_type, rw_rev);
875 }
876 } else if (rw_type == BWI_REGWIN_T_MAC) {
877 /* XXX ignore return value */
878 bwi_mac_attach(sc, i, rw_rev);
879 }
880 }
881
882 /* At least one MAC shold exist */
883 if (!BWI_REGWIN_EXIST(&sc->sc_mac[0].mac_regwin)) {
884 device_printf(sc->sc_dev, "no MAC was found\n");
885 return ENXIO;
886 }
887 KASSERT(sc->sc_nmac > 0, ("no mac's"));
888
889 /* Bus regwin must exist */
890 if (!BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
891 device_printf(sc->sc_dev, "no bus regwin was found\n");
892 return ENXIO;
893 }
894
895 /* Start with first MAC */
896 error = bwi_regwin_switch(sc, &sc->sc_mac[0].mac_regwin, NULL);
897 if (error)
898 return error;
899
900 return 0;
901 }
902
903 int
bwi_bus_init(struct bwi_softc * sc,struct bwi_mac * mac)904 bwi_bus_init(struct bwi_softc *sc, struct bwi_mac *mac)
905 {
906 struct bwi_regwin *old, *bus;
907 uint32_t val;
908 int error;
909
910 bus = &sc->sc_bus_regwin;
911 KASSERT(sc->sc_cur_regwin == &mac->mac_regwin, ("not cur regwin"));
912
913 /*
914 * Tell bus to generate requested interrupts
915 */
916 if (bus->rw_rev < 6 && bus->rw_type == BWI_REGWIN_T_BUSPCI) {
917 /*
918 * NOTE: Read BWI_FLAGS from MAC regwin
919 */
920 val = CSR_READ_4(sc, BWI_FLAGS);
921
922 error = bwi_regwin_switch(sc, bus, &old);
923 if (error)
924 return error;
925
926 CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK));
927 } else {
928 uint32_t mac_mask;
929
930 mac_mask = 1 << mac->mac_id;
931
932 error = bwi_regwin_switch(sc, bus, &old);
933 if (error)
934 return error;
935
936 val = pci_read_config(sc->sc_dev, BWI_PCIR_INTCTL, 4);
937 val |= mac_mask << 8;
938 pci_write_config(sc->sc_dev, BWI_PCIR_INTCTL, val, 4);
939 }
940
941 if (sc->sc_flags & BWI_F_BUS_INITED)
942 goto back;
943
944 if (bus->rw_type == BWI_REGWIN_T_BUSPCI) {
945 /*
946 * Enable prefetch and burst
947 */
948 CSR_SETBITS_4(sc, BWI_BUS_CONFIG,
949 BWI_BUS_CONFIG_PREFETCH | BWI_BUS_CONFIG_BURST);
950
951 if (bus->rw_rev < 5) {
952 struct bwi_regwin *com = &sc->sc_com_regwin;
953
954 /*
955 * Configure timeouts for bus operation
956 */
957
958 /*
959 * Set service timeout and request timeout
960 */
961 CSR_SETBITS_4(sc, BWI_CONF_LO,
962 __SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) |
963 __SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK));
964
965 /*
966 * If there is common regwin, we switch to that regwin
967 * and switch back to bus regwin once we have done.
968 */
969 if (BWI_REGWIN_EXIST(com)) {
970 error = bwi_regwin_switch(sc, com, NULL);
971 if (error)
972 return error;
973 }
974
975 /* Let bus know what we have changed */
976 CSR_WRITE_4(sc, BWI_BUS_ADDR, BWI_BUS_ADDR_MAGIC);
977 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */
978 CSR_WRITE_4(sc, BWI_BUS_DATA, 0);
979 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */
980
981 if (BWI_REGWIN_EXIST(com)) {
982 error = bwi_regwin_switch(sc, bus, NULL);
983 if (error)
984 return error;
985 }
986 } else if (bus->rw_rev >= 11) {
987 /*
988 * Enable memory read multiple
989 */
990 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, BWI_BUS_CONFIG_MRM);
991 }
992 } else {
993 /* TODO:PCIE */
994 }
995
996 sc->sc_flags |= BWI_F_BUS_INITED;
997 back:
998 return bwi_regwin_switch(sc, old, NULL);
999 }
1000
1001 static void
bwi_get_card_flags(struct bwi_softc * sc)1002 bwi_get_card_flags(struct bwi_softc *sc)
1003 {
1004 #define PCI_VENDOR_APPLE 0x106b
1005 #define PCI_VENDOR_DELL 0x1028
1006 sc->sc_card_flags = bwi_read_sprom(sc, BWI_SPROM_CARD_FLAGS);
1007 if (sc->sc_card_flags == 0xffff)
1008 sc->sc_card_flags = 0;
1009
1010 if (sc->sc_pci_subvid == PCI_VENDOR_DELL &&
1011 sc->sc_bbp_id == BWI_BBPID_BCM4301 &&
1012 sc->sc_pci_revid == 0x74)
1013 sc->sc_card_flags |= BWI_CARD_F_BT_COEXIST;
1014
1015 if (sc->sc_pci_subvid == PCI_VENDOR_APPLE &&
1016 sc->sc_pci_subdid == 0x4e && /* XXX */
1017 sc->sc_pci_revid > 0x40)
1018 sc->sc_card_flags |= BWI_CARD_F_PA_GPIO9;
1019
1020 DPRINTF(sc, BWI_DBG_ATTACH, "card flags 0x%04x\n", sc->sc_card_flags);
1021 #undef PCI_VENDOR_DELL
1022 #undef PCI_VENDOR_APPLE
1023 }
1024
1025 static void
bwi_get_eaddr(struct bwi_softc * sc,uint16_t eaddr_ofs,uint8_t * eaddr)1026 bwi_get_eaddr(struct bwi_softc *sc, uint16_t eaddr_ofs, uint8_t *eaddr)
1027 {
1028 int i;
1029
1030 for (i = 0; i < 3; ++i) {
1031 *((uint16_t *)eaddr + i) =
1032 htobe16(bwi_read_sprom(sc, eaddr_ofs + 2 * i));
1033 }
1034 }
1035
1036 static void
bwi_get_clock_freq(struct bwi_softc * sc,struct bwi_clock_freq * freq)1037 bwi_get_clock_freq(struct bwi_softc *sc, struct bwi_clock_freq *freq)
1038 {
1039 struct bwi_regwin *com;
1040 uint32_t val;
1041 u_int div;
1042 int src;
1043
1044 bzero(freq, sizeof(*freq));
1045 com = &sc->sc_com_regwin;
1046
1047 KASSERT(BWI_REGWIN_EXIST(com), ("regwin does not exist"));
1048 KASSERT(sc->sc_cur_regwin == com, ("wrong regwin"));
1049 KASSERT(sc->sc_cap & BWI_CAP_CLKMODE, ("wrong clock mode"));
1050
1051 /*
1052 * Calculate clock frequency
1053 */
1054 src = -1;
1055 div = 0;
1056 if (com->rw_rev < 6) {
1057 val = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
1058 if (val & BWI_PCIM_GPIO_OUT_CLKSRC) {
1059 src = BWI_CLKSRC_PCI;
1060 div = 64;
1061 } else {
1062 src = BWI_CLKSRC_CS_OSC;
1063 div = 32;
1064 }
1065 } else if (com->rw_rev < 10) {
1066 val = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1067
1068 src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC);
1069 if (src == BWI_CLKSRC_LP_OSC) {
1070 div = 1;
1071 } else {
1072 div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2;
1073
1074 /* Unknown source */
1075 if (src >= BWI_CLKSRC_MAX)
1076 src = BWI_CLKSRC_CS_OSC;
1077 }
1078 } else {
1079 val = CSR_READ_4(sc, BWI_CLOCK_INFO);
1080
1081 src = BWI_CLKSRC_CS_OSC;
1082 div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2;
1083 }
1084
1085 KASSERT(src >= 0 && src < BWI_CLKSRC_MAX, ("bad src %d", src));
1086 KASSERT(div != 0, ("div zero"));
1087
1088 DPRINTF(sc, BWI_DBG_ATTACH, "clksrc %s\n",
1089 src == BWI_CLKSRC_PCI ? "PCI" :
1090 (src == BWI_CLKSRC_LP_OSC ? "LP_OSC" : "CS_OSC"));
1091
1092 freq->clkfreq_min = bwi_clkfreq[src].freq_min / div;
1093 freq->clkfreq_max = bwi_clkfreq[src].freq_max / div;
1094
1095 DPRINTF(sc, BWI_DBG_ATTACH, "clkfreq min %u, max %u\n",
1096 freq->clkfreq_min, freq->clkfreq_max);
1097 }
1098
1099 static int
bwi_set_clock_mode(struct bwi_softc * sc,enum bwi_clock_mode clk_mode)1100 bwi_set_clock_mode(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
1101 {
1102 struct bwi_regwin *old, *com;
1103 uint32_t clk_ctrl, clk_src;
1104 int error, pwr_off = 0;
1105
1106 com = &sc->sc_com_regwin;
1107 if (!BWI_REGWIN_EXIST(com))
1108 return 0;
1109
1110 if (com->rw_rev >= 10 || com->rw_rev < 6)
1111 return 0;
1112
1113 /*
1114 * For common regwin whose rev is [6, 10), the chip
1115 * must be capable to change clock mode.
1116 */
1117 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
1118 return 0;
1119
1120 error = bwi_regwin_switch(sc, com, &old);
1121 if (error)
1122 return error;
1123
1124 if (clk_mode == BWI_CLOCK_MODE_FAST)
1125 bwi_power_on(sc, 0); /* Don't turn on PLL */
1126
1127 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1128 clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC);
1129
1130 switch (clk_mode) {
1131 case BWI_CLOCK_MODE_FAST:
1132 clk_ctrl &= ~BWI_CLOCK_CTRL_SLOW;
1133 clk_ctrl |= BWI_CLOCK_CTRL_IGNPLL;
1134 break;
1135 case BWI_CLOCK_MODE_SLOW:
1136 clk_ctrl |= BWI_CLOCK_CTRL_SLOW;
1137 break;
1138 case BWI_CLOCK_MODE_DYN:
1139 clk_ctrl &= ~(BWI_CLOCK_CTRL_SLOW |
1140 BWI_CLOCK_CTRL_IGNPLL |
1141 BWI_CLOCK_CTRL_NODYN);
1142 if (clk_src != BWI_CLKSRC_CS_OSC) {
1143 clk_ctrl |= BWI_CLOCK_CTRL_NODYN;
1144 pwr_off = 1;
1145 }
1146 break;
1147 }
1148 CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl);
1149
1150 if (pwr_off)
1151 bwi_power_off(sc, 0); /* Leave PLL as it is */
1152
1153 return bwi_regwin_switch(sc, old, NULL);
1154 }
1155
1156 static int
bwi_set_clock_delay(struct bwi_softc * sc)1157 bwi_set_clock_delay(struct bwi_softc *sc)
1158 {
1159 struct bwi_regwin *old, *com;
1160 int error;
1161
1162 com = &sc->sc_com_regwin;
1163 if (!BWI_REGWIN_EXIST(com))
1164 return 0;
1165
1166 error = bwi_regwin_switch(sc, com, &old);
1167 if (error)
1168 return error;
1169
1170 if (sc->sc_bbp_id == BWI_BBPID_BCM4321) {
1171 if (sc->sc_bbp_rev == 0)
1172 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC0);
1173 else if (sc->sc_bbp_rev == 1)
1174 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC1);
1175 }
1176
1177 if (sc->sc_cap & BWI_CAP_CLKMODE) {
1178 if (com->rw_rev >= 10) {
1179 CSR_FILT_SETBITS_4(sc, BWI_CLOCK_INFO, 0xffff, 0x40000);
1180 } else {
1181 struct bwi_clock_freq freq;
1182
1183 bwi_get_clock_freq(sc, &freq);
1184 CSR_WRITE_4(sc, BWI_PLL_ON_DELAY,
1185 howmany(freq.clkfreq_max * 150, 1000000));
1186 CSR_WRITE_4(sc, BWI_FREQ_SEL_DELAY,
1187 howmany(freq.clkfreq_max * 15, 1000000));
1188 }
1189 }
1190
1191 return bwi_regwin_switch(sc, old, NULL);
1192 }
1193
1194 static void
bwi_init(struct bwi_softc * sc)1195 bwi_init(struct bwi_softc *sc)
1196 {
1197 struct ieee80211com *ic = &sc->sc_ic;
1198
1199 BWI_LOCK(sc);
1200 bwi_init_statechg(sc, 1);
1201 BWI_UNLOCK(sc);
1202
1203 if (sc->sc_flags & BWI_F_RUNNING)
1204 ieee80211_start_all(ic); /* start all vap's */
1205 }
1206
1207 static void
bwi_init_statechg(struct bwi_softc * sc,int statechg)1208 bwi_init_statechg(struct bwi_softc *sc, int statechg)
1209 {
1210 struct bwi_mac *mac;
1211 int error;
1212
1213 BWI_ASSERT_LOCKED(sc);
1214
1215 bwi_stop_locked(sc, statechg);
1216
1217 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
1218
1219 /* TODO: 2 MAC */
1220
1221 mac = &sc->sc_mac[0];
1222 error = bwi_regwin_switch(sc, &mac->mac_regwin, NULL);
1223 if (error) {
1224 device_printf(sc->sc_dev, "%s: error %d on regwin switch\n",
1225 __func__, error);
1226 goto bad;
1227 }
1228 error = bwi_mac_init(mac);
1229 if (error) {
1230 device_printf(sc->sc_dev, "%s: error %d on MAC init\n",
1231 __func__, error);
1232 goto bad;
1233 }
1234
1235 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_DYN);
1236
1237 bwi_set_bssid(sc, bwi_zero_addr); /* Clear BSSID */
1238 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_MYADDR, sc->sc_ic.ic_macaddr);
1239
1240 bwi_mac_reset_hwkeys(mac);
1241
1242 if ((mac->mac_flags & BWI_MAC_F_HAS_TXSTATS) == 0) {
1243 int i;
1244
1245 #define NRETRY 1000
1246 /*
1247 * Drain any possible pending TX status
1248 */
1249 for (i = 0; i < NRETRY; ++i) {
1250 if ((CSR_READ_4(sc, BWI_TXSTATUS0) &
1251 BWI_TXSTATUS0_VALID) == 0)
1252 break;
1253 CSR_READ_4(sc, BWI_TXSTATUS1);
1254 }
1255 if (i == NRETRY)
1256 device_printf(sc->sc_dev,
1257 "%s: can't drain TX status\n", __func__);
1258 #undef NRETRY
1259 }
1260
1261 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11G)
1262 bwi_mac_updateslot(mac, 1);
1263
1264 /* Start MAC */
1265 error = bwi_mac_start(mac);
1266 if (error) {
1267 device_printf(sc->sc_dev, "%s: error %d starting MAC\n",
1268 __func__, error);
1269 goto bad;
1270 }
1271
1272 /* Clear stop flag before enabling interrupt */
1273 sc->sc_flags &= ~BWI_F_STOP;
1274 sc->sc_flags |= BWI_F_RUNNING;
1275 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc);
1276
1277 /* Enable intrs */
1278 bwi_enable_intrs(sc, BWI_INIT_INTRS);
1279 return;
1280 bad:
1281 bwi_stop_locked(sc, 1);
1282 }
1283
1284 static void
bwi_parent(struct ieee80211com * ic)1285 bwi_parent(struct ieee80211com *ic)
1286 {
1287 struct bwi_softc *sc = ic->ic_softc;
1288 int startall = 0;
1289
1290 BWI_LOCK(sc);
1291 if (ic->ic_nrunning > 0) {
1292 struct bwi_mac *mac;
1293 int promisc = -1;
1294
1295 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1296 ("current regwin type %d",
1297 sc->sc_cur_regwin->rw_type));
1298 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1299
1300 if (ic->ic_promisc > 0 && (sc->sc_flags & BWI_F_PROMISC) == 0) {
1301 promisc = 1;
1302 sc->sc_flags |= BWI_F_PROMISC;
1303 } else if (ic->ic_promisc == 0 &&
1304 (sc->sc_flags & BWI_F_PROMISC) != 0) {
1305 promisc = 0;
1306 sc->sc_flags &= ~BWI_F_PROMISC;
1307 }
1308
1309 if (promisc >= 0)
1310 bwi_mac_set_promisc(mac, promisc);
1311 }
1312 if (ic->ic_nrunning > 0) {
1313 if ((sc->sc_flags & BWI_F_RUNNING) == 0) {
1314 bwi_init_statechg(sc, 1);
1315 startall = 1;
1316 }
1317 } else if (sc->sc_flags & BWI_F_RUNNING)
1318 bwi_stop_locked(sc, 1);
1319 BWI_UNLOCK(sc);
1320 if (startall)
1321 ieee80211_start_all(ic);
1322 }
1323
1324 static int
bwi_transmit(struct ieee80211com * ic,struct mbuf * m)1325 bwi_transmit(struct ieee80211com *ic, struct mbuf *m)
1326 {
1327 struct bwi_softc *sc = ic->ic_softc;
1328 int error;
1329
1330 BWI_LOCK(sc);
1331 if ((sc->sc_flags & BWI_F_RUNNING) == 0) {
1332 BWI_UNLOCK(sc);
1333 return (ENXIO);
1334 }
1335 error = mbufq_enqueue(&sc->sc_snd, m);
1336 if (error) {
1337 BWI_UNLOCK(sc);
1338 return (error);
1339 }
1340 bwi_start_locked(sc);
1341 BWI_UNLOCK(sc);
1342 return (0);
1343 }
1344
1345 static void
bwi_start_locked(struct bwi_softc * sc)1346 bwi_start_locked(struct bwi_softc *sc)
1347 {
1348 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
1349 struct ieee80211_frame *wh;
1350 struct ieee80211_node *ni;
1351 struct mbuf *m;
1352 int trans, idx;
1353
1354 BWI_ASSERT_LOCKED(sc);
1355
1356 trans = 0;
1357 idx = tbd->tbd_idx;
1358
1359 while (tbd->tbd_buf[idx].tb_mbuf == NULL &&
1360 tbd->tbd_used + BWI_TX_NSPRDESC < BWI_TX_NDESC &&
1361 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) {
1362 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
1363 wh = mtod(m, struct ieee80211_frame *);
1364 if ((wh->i_fc[1] & IEEE80211_FC1_PROTECTED) != 0 &&
1365 ieee80211_crypto_encap(ni, m) == NULL) {
1366 if_inc_counter(ni->ni_vap->iv_ifp,
1367 IFCOUNTER_OERRORS, 1);
1368 ieee80211_free_node(ni);
1369 m_freem(m);
1370 continue;
1371 }
1372 if (bwi_encap(sc, idx, m, ni) != 0) {
1373 /* 'm' is freed in bwi_encap() if we reach here */
1374 if (ni != NULL) {
1375 if_inc_counter(ni->ni_vap->iv_ifp,
1376 IFCOUNTER_OERRORS, 1);
1377 ieee80211_free_node(ni);
1378 } else
1379 counter_u64_add(sc->sc_ic.ic_oerrors, 1);
1380 continue;
1381 }
1382 trans = 1;
1383 tbd->tbd_used++;
1384 idx = (idx + 1) % BWI_TX_NDESC;
1385 }
1386
1387 tbd->tbd_idx = idx;
1388 if (trans)
1389 sc->sc_tx_timer = 5;
1390 }
1391
1392 static int
bwi_raw_xmit(struct ieee80211_node * ni,struct mbuf * m,const struct ieee80211_bpf_params * params)1393 bwi_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
1394 const struct ieee80211_bpf_params *params)
1395 {
1396 struct ieee80211com *ic = ni->ni_ic;
1397 struct bwi_softc *sc = ic->ic_softc;
1398 /* XXX wme? */
1399 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
1400 int idx, error;
1401
1402 if ((sc->sc_flags & BWI_F_RUNNING) == 0) {
1403 m_freem(m);
1404 return ENETDOWN;
1405 }
1406
1407 BWI_LOCK(sc);
1408 idx = tbd->tbd_idx;
1409 KASSERT(tbd->tbd_buf[idx].tb_mbuf == NULL, ("slot %d not empty", idx));
1410 if (params == NULL) {
1411 /*
1412 * Legacy path; interpret frame contents to decide
1413 * precisely how to send the frame.
1414 */
1415 error = bwi_encap(sc, idx, m, ni);
1416 } else {
1417 /*
1418 * Caller supplied explicit parameters to use in
1419 * sending the frame.
1420 */
1421 error = bwi_encap_raw(sc, idx, m, ni, params);
1422 }
1423 if (error == 0) {
1424 tbd->tbd_used++;
1425 tbd->tbd_idx = (idx + 1) % BWI_TX_NDESC;
1426 sc->sc_tx_timer = 5;
1427 }
1428 BWI_UNLOCK(sc);
1429 return error;
1430 }
1431
1432 static void
bwi_watchdog(void * arg)1433 bwi_watchdog(void *arg)
1434 {
1435 struct bwi_softc *sc;
1436
1437 sc = arg;
1438 BWI_ASSERT_LOCKED(sc);
1439 if (sc->sc_tx_timer != 0 && --sc->sc_tx_timer == 0) {
1440 device_printf(sc->sc_dev, "watchdog timeout\n");
1441 counter_u64_add(sc->sc_ic.ic_oerrors, 1);
1442 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task);
1443 }
1444 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc);
1445 }
1446
1447 static void
bwi_stop(struct bwi_softc * sc,int statechg)1448 bwi_stop(struct bwi_softc *sc, int statechg)
1449 {
1450 BWI_LOCK(sc);
1451 bwi_stop_locked(sc, statechg);
1452 BWI_UNLOCK(sc);
1453 }
1454
1455 static void
bwi_stop_locked(struct bwi_softc * sc,int statechg)1456 bwi_stop_locked(struct bwi_softc *sc, int statechg)
1457 {
1458 struct bwi_mac *mac;
1459 int i, error, pwr_off = 0;
1460
1461 BWI_ASSERT_LOCKED(sc);
1462
1463 callout_stop(&sc->sc_calib_ch);
1464 callout_stop(&sc->sc_led_blink_ch);
1465 sc->sc_led_blinking = 0;
1466 sc->sc_flags |= BWI_F_STOP;
1467
1468 if (sc->sc_flags & BWI_F_RUNNING) {
1469 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1470 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
1471 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1472
1473 bwi_disable_intrs(sc, BWI_ALL_INTRS);
1474 CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1475 bwi_mac_stop(mac);
1476 }
1477
1478 for (i = 0; i < sc->sc_nmac; ++i) {
1479 struct bwi_regwin *old_rw;
1480
1481 mac = &sc->sc_mac[i];
1482 if ((mac->mac_flags & BWI_MAC_F_INITED) == 0)
1483 continue;
1484
1485 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old_rw);
1486 if (error)
1487 continue;
1488
1489 bwi_mac_shutdown(mac);
1490 pwr_off = 1;
1491
1492 bwi_regwin_switch(sc, old_rw, NULL);
1493 }
1494
1495 if (pwr_off)
1496 bwi_bbp_power_off(sc);
1497
1498 sc->sc_tx_timer = 0;
1499 callout_stop(&sc->sc_watchdog_timer);
1500 sc->sc_flags &= ~BWI_F_RUNNING;
1501 }
1502
1503 void
bwi_intr(void * xsc)1504 bwi_intr(void *xsc)
1505 {
1506 struct bwi_softc *sc = xsc;
1507 struct bwi_mac *mac;
1508 uint32_t intr_status;
1509 uint32_t txrx_intr_status[BWI_TXRX_NRING];
1510 int i, txrx_error, tx = 0, rx_data = -1;
1511
1512 BWI_LOCK(sc);
1513
1514 #ifndef __HAIKU__
1515 if ((sc->sc_flags & BWI_F_RUNNING) == 0 ||
1516 (sc->sc_flags & BWI_F_STOP)) {
1517 BWI_UNLOCK(sc);
1518 return;
1519 }
1520 /*
1521 * Get interrupt status
1522 */
1523 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS);
1524 if (intr_status == 0xffffffff) { /* Not for us */
1525 BWI_UNLOCK(sc);
1526 return;
1527 }
1528
1529 DPRINTF(sc, BWI_DBG_INTR, "intr status 0x%08x\n", intr_status);
1530
1531 intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1532 if (intr_status == 0) { /* Nothing is interesting */
1533 BWI_UNLOCK(sc);
1534 return;
1535 }
1536 #else
1537 intr_status = atomic_get((int32 *)&sc->sc_intr_status);
1538 #endif
1539
1540 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1541 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
1542 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1543
1544 txrx_error = 0;
1545 DPRINTF(sc, BWI_DBG_INTR, "%s\n", "TX/RX intr");
1546 for (i = 0; i < BWI_TXRX_NRING; ++i) {
1547 uint32_t mask;
1548
1549 if (BWI_TXRX_IS_RX(i))
1550 mask = BWI_TXRX_RX_INTRS;
1551 else
1552 mask = BWI_TXRX_TX_INTRS;
1553
1554 txrx_intr_status[i] =
1555 CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask;
1556
1557 _DPRINTF(sc, BWI_DBG_INTR, ", %d 0x%08x",
1558 i, txrx_intr_status[i]);
1559
1560 if (txrx_intr_status[i] & BWI_TXRX_INTR_ERROR) {
1561 device_printf(sc->sc_dev,
1562 "%s: intr fatal TX/RX (%d) error 0x%08x\n",
1563 __func__, i, txrx_intr_status[i]);
1564 txrx_error = 1;
1565 }
1566 }
1567 _DPRINTF(sc, BWI_DBG_INTR, "%s\n", "");
1568
1569 /*
1570 * Acknowledge interrupt
1571 */
1572 CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status);
1573
1574 for (i = 0; i < BWI_TXRX_NRING; ++i)
1575 CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i), txrx_intr_status[i]);
1576
1577 #if !defined(__HAIKU__)
1578 /* Disable all interrupts */
1579 bwi_disable_intrs(sc, BWI_ALL_INTRS);
1580 #endif
1581
1582 /*
1583 * http://bcm-specs.sipsolutions.net/Interrupts
1584 * Says for this bit (0x800):
1585 * "Fatal Error
1586 *
1587 * We got this one while testing things when by accident the
1588 * template ram wasn't set to big endian when it should have
1589 * been after writing the initial values. It keeps on being
1590 * triggered, the only way to stop it seems to shut down the
1591 * chip."
1592 *
1593 * Suggesting that we should never get it and if we do we're not
1594 * feeding TX packets into the MAC correctly if we do... Apparently,
1595 * it is valid only on mac version 5 and higher, but I couldn't
1596 * find a reference for that... Since I see them from time to time
1597 * on my card, this suggests an error in the tx path still...
1598 */
1599 if (intr_status & BWI_INTR_PHY_TXERR) {
1600 if (mac->mac_flags & BWI_MAC_F_PHYE_RESET) {
1601 device_printf(sc->sc_dev, "%s: intr PHY TX error\n",
1602 __func__);
1603 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task);
1604 BWI_UNLOCK(sc);
1605 return;
1606 }
1607 }
1608
1609 if (txrx_error) {
1610 /* TODO: reset device */
1611 }
1612
1613 if (intr_status & BWI_INTR_TBTT)
1614 bwi_mac_config_ps(mac);
1615
1616 if (intr_status & BWI_INTR_EO_ATIM)
1617 device_printf(sc->sc_dev, "EO_ATIM\n");
1618
1619 if (intr_status & BWI_INTR_PMQ) {
1620 for (;;) {
1621 if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0)
1622 break;
1623 }
1624 CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2);
1625 }
1626
1627 if (intr_status & BWI_INTR_NOISE)
1628 device_printf(sc->sc_dev, "intr noise\n");
1629
1630 if (txrx_intr_status[0] & BWI_TXRX_INTR_RX) {
1631 rx_data = sc->sc_rxeof(sc);
1632 if (sc->sc_flags & BWI_F_STOP) {
1633 BWI_UNLOCK(sc);
1634 return;
1635 }
1636 }
1637
1638 if (txrx_intr_status[3] & BWI_TXRX_INTR_RX) {
1639 sc->sc_txeof_status(sc);
1640 tx = 1;
1641 }
1642
1643 if (intr_status & BWI_INTR_TX_DONE) {
1644 bwi_txeof(sc);
1645 tx = 1;
1646 }
1647
1648 /* Re-enable interrupts */
1649 bwi_enable_intrs(sc, BWI_INIT_INTRS);
1650
1651 if (sc->sc_blink_led != NULL && sc->sc_led_blink) {
1652 int evt = BWI_LED_EVENT_NONE;
1653
1654 if (tx && rx_data > 0) {
1655 if (sc->sc_rx_rate > sc->sc_tx_rate)
1656 evt = BWI_LED_EVENT_RX;
1657 else
1658 evt = BWI_LED_EVENT_TX;
1659 } else if (tx) {
1660 evt = BWI_LED_EVENT_TX;
1661 } else if (rx_data > 0) {
1662 evt = BWI_LED_EVENT_RX;
1663 } else if (rx_data == 0) {
1664 evt = BWI_LED_EVENT_POLL;
1665 }
1666
1667 if (evt != BWI_LED_EVENT_NONE)
1668 bwi_led_event(sc, evt);
1669 }
1670
1671 BWI_UNLOCK(sc);
1672 }
1673
1674 static void
bwi_scan_start(struct ieee80211com * ic)1675 bwi_scan_start(struct ieee80211com *ic)
1676 {
1677 struct bwi_softc *sc = ic->ic_softc;
1678
1679 BWI_LOCK(sc);
1680 /* Enable MAC beacon promiscuity */
1681 CSR_SETBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN);
1682 BWI_UNLOCK(sc);
1683 }
1684
1685 static void
bwi_getradiocaps(struct ieee80211com * ic,int maxchans,int * nchans,struct ieee80211_channel chans[])1686 bwi_getradiocaps(struct ieee80211com *ic,
1687 int maxchans, int *nchans, struct ieee80211_channel chans[])
1688 {
1689 struct bwi_softc *sc = ic->ic_softc;
1690 struct bwi_mac *mac;
1691 struct bwi_phy *phy;
1692 uint8_t bands[IEEE80211_MODE_BYTES];
1693
1694 /*
1695 * XXX First MAC is known to exist
1696 * TODO2
1697 */
1698 mac = &sc->sc_mac[0];
1699 phy = &mac->mac_phy;
1700
1701 memset(bands, 0, sizeof(bands));
1702 switch (phy->phy_mode) {
1703 case IEEE80211_MODE_11G:
1704 setbit(bands, IEEE80211_MODE_11G);
1705 /* FALLTHROUGH */
1706 case IEEE80211_MODE_11B:
1707 setbit(bands, IEEE80211_MODE_11B);
1708 break;
1709 case IEEE80211_MODE_11A:
1710 /* TODO:11A */
1711 setbit(bands, IEEE80211_MODE_11A);
1712 device_printf(sc->sc_dev, "no 11a support\n");
1713 return;
1714 default:
1715 panic("unknown phymode %d\n", phy->phy_mode);
1716 }
1717
1718 ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, 0);
1719 }
1720
1721 static void
bwi_set_channel(struct ieee80211com * ic)1722 bwi_set_channel(struct ieee80211com *ic)
1723 {
1724 struct bwi_softc *sc = ic->ic_softc;
1725 struct ieee80211_channel *c = ic->ic_curchan;
1726 struct bwi_mac *mac;
1727
1728 BWI_LOCK(sc);
1729 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1730 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
1731 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1732 bwi_rf_set_chan(mac, ieee80211_chan2ieee(ic, c), 0);
1733
1734 sc->sc_rates = ieee80211_get_ratetable(c);
1735 BWI_UNLOCK(sc);
1736 }
1737
1738 static void
bwi_scan_end(struct ieee80211com * ic)1739 bwi_scan_end(struct ieee80211com *ic)
1740 {
1741 struct bwi_softc *sc = ic->ic_softc;
1742
1743 BWI_LOCK(sc);
1744 CSR_CLRBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN);
1745 BWI_UNLOCK(sc);
1746 }
1747
1748 static int
bwi_newstate(struct ieee80211vap * vap,enum ieee80211_state nstate,int arg)1749 bwi_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
1750 {
1751 struct bwi_vap *bvp = BWI_VAP(vap);
1752 struct ieee80211com *ic= vap->iv_ic;
1753 struct bwi_softc *sc = ic->ic_softc;
1754 enum ieee80211_state ostate = vap->iv_state;
1755 struct bwi_mac *mac;
1756 int error;
1757
1758 BWI_LOCK(sc);
1759
1760 callout_stop(&sc->sc_calib_ch);
1761
1762 if (nstate == IEEE80211_S_INIT)
1763 sc->sc_txpwrcb_type = BWI_TXPWR_INIT;
1764
1765 bwi_led_newstate(sc, nstate);
1766
1767 error = bvp->bv_newstate(vap, nstate, arg);
1768 if (error != 0)
1769 goto back;
1770
1771 /*
1772 * Clear the BSSID when we stop a STA
1773 */
1774 if (vap->iv_opmode == IEEE80211_M_STA) {
1775 if (ostate == IEEE80211_S_RUN && nstate != IEEE80211_S_RUN) {
1776 /*
1777 * Clear out the BSSID. If we reassociate to
1778 * the same AP, this will reinialize things
1779 * correctly...
1780 */
1781 if (ic->ic_opmode == IEEE80211_M_STA &&
1782 !(sc->sc_flags & BWI_F_STOP))
1783 bwi_set_bssid(sc, bwi_zero_addr);
1784 }
1785 }
1786
1787 if (vap->iv_opmode == IEEE80211_M_MONITOR) {
1788 /* Nothing to do */
1789 } else if (nstate == IEEE80211_S_RUN) {
1790 bwi_set_bssid(sc, vap->iv_bss->ni_bssid);
1791
1792 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1793 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
1794 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1795
1796 /* Initial TX power calibration */
1797 bwi_mac_calibrate_txpower(mac, BWI_TXPWR_INIT);
1798 #ifdef notyet
1799 sc->sc_txpwrcb_type = BWI_TXPWR_FORCE;
1800 #else
1801 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB;
1802 #endif
1803
1804 callout_reset(&sc->sc_calib_ch, hz, bwi_calibrate, sc);
1805 }
1806 back:
1807 BWI_UNLOCK(sc);
1808
1809 return error;
1810 }
1811
1812 static int
bwi_dma_alloc(struct bwi_softc * sc)1813 bwi_dma_alloc(struct bwi_softc *sc)
1814 {
1815 int error, i, has_txstats;
1816 bus_addr_t lowaddr = 0;
1817 bus_size_t tx_ring_sz, rx_ring_sz, desc_sz = 0;
1818 uint32_t txrx_ctrl_step = 0;
1819
1820 has_txstats = 0;
1821 for (i = 0; i < sc->sc_nmac; ++i) {
1822 if (sc->sc_mac[i].mac_flags & BWI_MAC_F_HAS_TXSTATS) {
1823 has_txstats = 1;
1824 break;
1825 }
1826 }
1827
1828 switch (sc->sc_bus_space) {
1829 case BWI_BUS_SPACE_30BIT:
1830 case BWI_BUS_SPACE_32BIT:
1831 if (sc->sc_bus_space == BWI_BUS_SPACE_30BIT)
1832 lowaddr = BWI_BUS_SPACE_MAXADDR;
1833 else
1834 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1835 desc_sz = sizeof(struct bwi_desc32);
1836 txrx_ctrl_step = 0x20;
1837
1838 sc->sc_init_tx_ring = bwi_init_tx_ring32;
1839 sc->sc_free_tx_ring = bwi_free_tx_ring32;
1840 sc->sc_init_rx_ring = bwi_init_rx_ring32;
1841 sc->sc_free_rx_ring = bwi_free_rx_ring32;
1842 sc->sc_setup_rxdesc = bwi_setup_rx_desc32;
1843 sc->sc_setup_txdesc = bwi_setup_tx_desc32;
1844 sc->sc_rxeof = bwi_rxeof32;
1845 sc->sc_start_tx = bwi_start_tx32;
1846 if (has_txstats) {
1847 sc->sc_init_txstats = bwi_init_txstats32;
1848 sc->sc_free_txstats = bwi_free_txstats32;
1849 sc->sc_txeof_status = bwi_txeof_status32;
1850 }
1851 break;
1852
1853 case BWI_BUS_SPACE_64BIT:
1854 lowaddr = BUS_SPACE_MAXADDR; /* XXX */
1855 desc_sz = sizeof(struct bwi_desc64);
1856 txrx_ctrl_step = 0x40;
1857
1858 sc->sc_init_tx_ring = bwi_init_tx_ring64;
1859 sc->sc_free_tx_ring = bwi_free_tx_ring64;
1860 sc->sc_init_rx_ring = bwi_init_rx_ring64;
1861 sc->sc_free_rx_ring = bwi_free_rx_ring64;
1862 sc->sc_setup_rxdesc = bwi_setup_rx_desc64;
1863 sc->sc_setup_txdesc = bwi_setup_tx_desc64;
1864 sc->sc_rxeof = bwi_rxeof64;
1865 sc->sc_start_tx = bwi_start_tx64;
1866 if (has_txstats) {
1867 sc->sc_init_txstats = bwi_init_txstats64;
1868 sc->sc_free_txstats = bwi_free_txstats64;
1869 sc->sc_txeof_status = bwi_txeof_status64;
1870 }
1871 break;
1872 }
1873
1874 KASSERT(lowaddr != 0, ("lowaddr zero"));
1875 KASSERT(desc_sz != 0, ("desc_sz zero"));
1876 KASSERT(txrx_ctrl_step != 0, ("txrx_ctrl_step zero"));
1877
1878 tx_ring_sz = roundup(desc_sz * BWI_TX_NDESC, BWI_RING_ALIGN);
1879 rx_ring_sz = roundup(desc_sz * BWI_RX_NDESC, BWI_RING_ALIGN);
1880
1881 /*
1882 * Create top level DMA tag
1883 */
1884 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */
1885 BWI_ALIGN, 0, /* alignment, bounds */
1886 lowaddr, /* lowaddr */
1887 BUS_SPACE_MAXADDR, /* highaddr */
1888 NULL, NULL, /* filter, filterarg */
1889 BUS_SPACE_MAXSIZE, /* maxsize */
1890 BUS_SPACE_UNRESTRICTED, /* nsegments */
1891 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1892 0, /* flags */
1893 NULL, NULL, /* lockfunc, lockarg */
1894 &sc->sc_parent_dtag);
1895 if (error) {
1896 device_printf(sc->sc_dev, "can't create parent DMA tag\n");
1897 return error;
1898 }
1899
1900 #define TXRX_CTRL(idx) (BWI_TXRX_CTRL_BASE + (idx) * txrx_ctrl_step)
1901
1902 /*
1903 * Create TX ring DMA stuffs
1904 */
1905 error = bus_dma_tag_create(sc->sc_parent_dtag,
1906 BWI_RING_ALIGN, 0,
1907 BUS_SPACE_MAXADDR,
1908 BUS_SPACE_MAXADDR,
1909 NULL, NULL,
1910 tx_ring_sz,
1911 1,
1912 tx_ring_sz,
1913 0,
1914 NULL, NULL,
1915 &sc->sc_txring_dtag);
1916 if (error) {
1917 device_printf(sc->sc_dev, "can't create TX ring DMA tag\n");
1918 return error;
1919 }
1920
1921 for (i = 0; i < BWI_TX_NRING; ++i) {
1922 error = bwi_dma_ring_alloc(sc, sc->sc_txring_dtag,
1923 &sc->sc_tx_rdata[i], tx_ring_sz,
1924 TXRX_CTRL(i));
1925 if (error) {
1926 device_printf(sc->sc_dev, "%dth TX ring "
1927 "DMA alloc failed\n", i);
1928 return error;
1929 }
1930 }
1931
1932 /*
1933 * Create RX ring DMA stuffs
1934 */
1935 error = bus_dma_tag_create(sc->sc_parent_dtag,
1936 BWI_RING_ALIGN, 0,
1937 BUS_SPACE_MAXADDR,
1938 BUS_SPACE_MAXADDR,
1939 NULL, NULL,
1940 rx_ring_sz,
1941 1,
1942 rx_ring_sz,
1943 0,
1944 NULL, NULL,
1945 &sc->sc_rxring_dtag);
1946 if (error) {
1947 device_printf(sc->sc_dev, "can't create RX ring DMA tag\n");
1948 return error;
1949 }
1950
1951 error = bwi_dma_ring_alloc(sc, sc->sc_rxring_dtag, &sc->sc_rx_rdata,
1952 rx_ring_sz, TXRX_CTRL(0));
1953 if (error) {
1954 device_printf(sc->sc_dev, "RX ring DMA alloc failed\n");
1955 return error;
1956 }
1957
1958 if (has_txstats) {
1959 error = bwi_dma_txstats_alloc(sc, TXRX_CTRL(3), desc_sz);
1960 if (error) {
1961 device_printf(sc->sc_dev,
1962 "TX stats DMA alloc failed\n");
1963 return error;
1964 }
1965 }
1966
1967 #undef TXRX_CTRL
1968
1969 return bwi_dma_mbuf_create(sc);
1970 }
1971
1972 static void
bwi_dma_free(struct bwi_softc * sc)1973 bwi_dma_free(struct bwi_softc *sc)
1974 {
1975 if (sc->sc_txring_dtag != NULL) {
1976 int i;
1977
1978 for (i = 0; i < BWI_TX_NRING; ++i) {
1979 struct bwi_ring_data *rd = &sc->sc_tx_rdata[i];
1980
1981 if (rd->rdata_desc != NULL) {
1982 bus_dmamap_unload(sc->sc_txring_dtag,
1983 rd->rdata_dmap);
1984 bus_dmamem_free(sc->sc_txring_dtag,
1985 rd->rdata_desc,
1986 rd->rdata_dmap);
1987 }
1988 }
1989 bus_dma_tag_destroy(sc->sc_txring_dtag);
1990 }
1991
1992 if (sc->sc_rxring_dtag != NULL) {
1993 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
1994
1995 if (rd->rdata_desc != NULL) {
1996 bus_dmamap_unload(sc->sc_rxring_dtag, rd->rdata_dmap);
1997 bus_dmamem_free(sc->sc_rxring_dtag, rd->rdata_desc,
1998 rd->rdata_dmap);
1999 }
2000 bus_dma_tag_destroy(sc->sc_rxring_dtag);
2001 }
2002
2003 bwi_dma_txstats_free(sc);
2004 bwi_dma_mbuf_destroy(sc, BWI_TX_NRING, 1);
2005
2006 if (sc->sc_parent_dtag != NULL)
2007 bus_dma_tag_destroy(sc->sc_parent_dtag);
2008 }
2009
2010 static int
bwi_dma_ring_alloc(struct bwi_softc * sc,bus_dma_tag_t dtag,struct bwi_ring_data * rd,bus_size_t size,uint32_t txrx_ctrl)2011 bwi_dma_ring_alloc(struct bwi_softc *sc, bus_dma_tag_t dtag,
2012 struct bwi_ring_data *rd, bus_size_t size,
2013 uint32_t txrx_ctrl)
2014 {
2015 int error;
2016
2017 error = bus_dmamem_alloc(dtag, &rd->rdata_desc,
2018 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2019 &rd->rdata_dmap);
2020 if (error) {
2021 device_printf(sc->sc_dev, "can't allocate DMA mem\n");
2022 return error;
2023 }
2024
2025 error = bus_dmamap_load(dtag, rd->rdata_dmap, rd->rdata_desc, size,
2026 bwi_dma_ring_addr, &rd->rdata_paddr,
2027 BUS_DMA_NOWAIT);
2028 if (error) {
2029 device_printf(sc->sc_dev, "can't load DMA mem\n");
2030 bus_dmamem_free(dtag, rd->rdata_desc, rd->rdata_dmap);
2031 rd->rdata_desc = NULL;
2032 return error;
2033 }
2034
2035 rd->rdata_txrx_ctrl = txrx_ctrl;
2036 return 0;
2037 }
2038
2039 static int
bwi_dma_txstats_alloc(struct bwi_softc * sc,uint32_t ctrl_base,bus_size_t desc_sz)2040 bwi_dma_txstats_alloc(struct bwi_softc *sc, uint32_t ctrl_base,
2041 bus_size_t desc_sz)
2042 {
2043 struct bwi_txstats_data *st;
2044 bus_size_t dma_size;
2045 int error;
2046
2047 st = malloc(sizeof(*st), M_DEVBUF, M_NOWAIT | M_ZERO);
2048 if (st == NULL) {
2049 device_printf(sc->sc_dev, "can't allocate txstats data\n");
2050 return ENOMEM;
2051 }
2052 sc->sc_txstats = st;
2053
2054 /*
2055 * Create TX stats descriptor DMA stuffs
2056 */
2057 dma_size = roundup(desc_sz * BWI_TXSTATS_NDESC, BWI_RING_ALIGN);
2058
2059 error = bus_dma_tag_create(sc->sc_parent_dtag,
2060 BWI_RING_ALIGN,
2061 0,
2062 BUS_SPACE_MAXADDR,
2063 BUS_SPACE_MAXADDR,
2064 NULL, NULL,
2065 dma_size,
2066 1,
2067 dma_size,
2068 0,
2069 NULL, NULL,
2070 &st->stats_ring_dtag);
2071 if (error) {
2072 device_printf(sc->sc_dev, "can't create txstats ring "
2073 "DMA tag\n");
2074 return error;
2075 }
2076
2077 error = bus_dmamem_alloc(st->stats_ring_dtag, &st->stats_ring,
2078 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2079 &st->stats_ring_dmap);
2080 if (error) {
2081 device_printf(sc->sc_dev, "can't allocate txstats ring "
2082 "DMA mem\n");
2083 bus_dma_tag_destroy(st->stats_ring_dtag);
2084 st->stats_ring_dtag = NULL;
2085 return error;
2086 }
2087
2088 error = bus_dmamap_load(st->stats_ring_dtag, st->stats_ring_dmap,
2089 st->stats_ring, dma_size,
2090 bwi_dma_ring_addr, &st->stats_ring_paddr,
2091 BUS_DMA_NOWAIT);
2092 if (error) {
2093 device_printf(sc->sc_dev, "can't load txstats ring DMA mem\n");
2094 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring,
2095 st->stats_ring_dmap);
2096 bus_dma_tag_destroy(st->stats_ring_dtag);
2097 st->stats_ring_dtag = NULL;
2098 return error;
2099 }
2100
2101 /*
2102 * Create TX stats DMA stuffs
2103 */
2104 dma_size = roundup(sizeof(struct bwi_txstats) * BWI_TXSTATS_NDESC,
2105 BWI_ALIGN);
2106
2107 error = bus_dma_tag_create(sc->sc_parent_dtag,
2108 BWI_ALIGN,
2109 0,
2110 BUS_SPACE_MAXADDR,
2111 BUS_SPACE_MAXADDR,
2112 NULL, NULL,
2113 dma_size,
2114 1,
2115 dma_size,
2116 0,
2117 NULL, NULL,
2118 &st->stats_dtag);
2119 if (error) {
2120 device_printf(sc->sc_dev, "can't create txstats DMA tag\n");
2121 return error;
2122 }
2123
2124 error = bus_dmamem_alloc(st->stats_dtag, (void **)&st->stats,
2125 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2126 &st->stats_dmap);
2127 if (error) {
2128 device_printf(sc->sc_dev, "can't allocate txstats DMA mem\n");
2129 bus_dma_tag_destroy(st->stats_dtag);
2130 st->stats_dtag = NULL;
2131 return error;
2132 }
2133
2134 error = bus_dmamap_load(st->stats_dtag, st->stats_dmap, st->stats,
2135 dma_size, bwi_dma_ring_addr, &st->stats_paddr,
2136 BUS_DMA_NOWAIT);
2137 if (error) {
2138 device_printf(sc->sc_dev, "can't load txstats DMA mem\n");
2139 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap);
2140 bus_dma_tag_destroy(st->stats_dtag);
2141 st->stats_dtag = NULL;
2142 return error;
2143 }
2144
2145 st->stats_ctrl_base = ctrl_base;
2146 return 0;
2147 }
2148
2149 static void
bwi_dma_txstats_free(struct bwi_softc * sc)2150 bwi_dma_txstats_free(struct bwi_softc *sc)
2151 {
2152 struct bwi_txstats_data *st;
2153
2154 if (sc->sc_txstats == NULL)
2155 return;
2156 st = sc->sc_txstats;
2157
2158 if (st->stats_ring_dtag != NULL) {
2159 bus_dmamap_unload(st->stats_ring_dtag, st->stats_ring_dmap);
2160 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring,
2161 st->stats_ring_dmap);
2162 bus_dma_tag_destroy(st->stats_ring_dtag);
2163 }
2164
2165 if (st->stats_dtag != NULL) {
2166 bus_dmamap_unload(st->stats_dtag, st->stats_dmap);
2167 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap);
2168 bus_dma_tag_destroy(st->stats_dtag);
2169 }
2170
2171 free(st, M_DEVBUF);
2172 }
2173
2174 static void
bwi_dma_ring_addr(void * arg,bus_dma_segment_t * seg,int nseg,int error)2175 bwi_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
2176 {
2177 KASSERT(nseg == 1, ("too many segments\n"));
2178 *((bus_addr_t *)arg) = seg->ds_addr;
2179 }
2180
2181 static int
bwi_dma_mbuf_create(struct bwi_softc * sc)2182 bwi_dma_mbuf_create(struct bwi_softc *sc)
2183 {
2184 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2185 int i, j, k, ntx, error;
2186
2187 /*
2188 * Create TX/RX mbuf DMA tag
2189 */
2190 error = bus_dma_tag_create(sc->sc_parent_dtag,
2191 1,
2192 0,
2193 BUS_SPACE_MAXADDR,
2194 BUS_SPACE_MAXADDR,
2195 NULL, NULL,
2196 MCLBYTES,
2197 1,
2198 MCLBYTES,
2199 BUS_DMA_ALLOCNOW,
2200 NULL, NULL,
2201 &sc->sc_buf_dtag);
2202 if (error) {
2203 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n");
2204 return error;
2205 }
2206
2207 ntx = 0;
2208
2209 /*
2210 * Create TX mbuf DMA map
2211 */
2212 for (i = 0; i < BWI_TX_NRING; ++i) {
2213 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
2214
2215 for (j = 0; j < BWI_TX_NDESC; ++j) {
2216 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2217 &tbd->tbd_buf[j].tb_dmap);
2218 if (error) {
2219 device_printf(sc->sc_dev, "can't create "
2220 "%dth tbd, %dth DMA map\n", i, j);
2221
2222 ntx = i;
2223 for (k = 0; k < j; ++k) {
2224 bus_dmamap_destroy(sc->sc_buf_dtag,
2225 tbd->tbd_buf[k].tb_dmap);
2226 }
2227 goto fail;
2228 }
2229 }
2230 }
2231 ntx = BWI_TX_NRING;
2232
2233 /*
2234 * Create RX mbuf DMA map and a spare DMA map
2235 */
2236 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2237 &rbd->rbd_tmp_dmap);
2238 if (error) {
2239 device_printf(sc->sc_dev,
2240 "can't create spare RX buf DMA map\n");
2241 goto fail;
2242 }
2243
2244 for (j = 0; j < BWI_RX_NDESC; ++j) {
2245 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2246 &rbd->rbd_buf[j].rb_dmap);
2247 if (error) {
2248 device_printf(sc->sc_dev, "can't create %dth "
2249 "RX buf DMA map\n", j);
2250
2251 for (k = 0; k < j; ++k) {
2252 bus_dmamap_destroy(sc->sc_buf_dtag,
2253 rbd->rbd_buf[j].rb_dmap);
2254 }
2255 bus_dmamap_destroy(sc->sc_buf_dtag,
2256 rbd->rbd_tmp_dmap);
2257 goto fail;
2258 }
2259 }
2260
2261 return 0;
2262 fail:
2263 bwi_dma_mbuf_destroy(sc, ntx, 0);
2264 return error;
2265 }
2266
2267 static void
bwi_dma_mbuf_destroy(struct bwi_softc * sc,int ntx,int nrx)2268 bwi_dma_mbuf_destroy(struct bwi_softc *sc, int ntx, int nrx)
2269 {
2270 int i, j;
2271
2272 if (sc->sc_buf_dtag == NULL)
2273 return;
2274
2275 for (i = 0; i < ntx; ++i) {
2276 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
2277
2278 for (j = 0; j < BWI_TX_NDESC; ++j) {
2279 struct bwi_txbuf *tb = &tbd->tbd_buf[j];
2280
2281 if (tb->tb_mbuf != NULL) {
2282 bus_dmamap_unload(sc->sc_buf_dtag,
2283 tb->tb_dmap);
2284 m_freem(tb->tb_mbuf);
2285 }
2286 if (tb->tb_ni != NULL)
2287 ieee80211_free_node(tb->tb_ni);
2288 bus_dmamap_destroy(sc->sc_buf_dtag, tb->tb_dmap);
2289 }
2290 }
2291
2292 if (nrx) {
2293 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2294
2295 bus_dmamap_destroy(sc->sc_buf_dtag, rbd->rbd_tmp_dmap);
2296 for (j = 0; j < BWI_RX_NDESC; ++j) {
2297 struct bwi_rxbuf *rb = &rbd->rbd_buf[j];
2298
2299 if (rb->rb_mbuf != NULL) {
2300 bus_dmamap_unload(sc->sc_buf_dtag,
2301 rb->rb_dmap);
2302 m_freem(rb->rb_mbuf);
2303 }
2304 bus_dmamap_destroy(sc->sc_buf_dtag, rb->rb_dmap);
2305 }
2306 }
2307
2308 bus_dma_tag_destroy(sc->sc_buf_dtag);
2309 sc->sc_buf_dtag = NULL;
2310 }
2311
2312 static void
bwi_enable_intrs(struct bwi_softc * sc,uint32_t enable_intrs)2313 bwi_enable_intrs(struct bwi_softc *sc, uint32_t enable_intrs)
2314 {
2315 CSR_SETBITS_4(sc, BWI_MAC_INTR_MASK, enable_intrs);
2316 }
2317
2318 static void
bwi_disable_intrs(struct bwi_softc * sc,uint32_t disable_intrs)2319 bwi_disable_intrs(struct bwi_softc *sc, uint32_t disable_intrs)
2320 {
2321 CSR_CLRBITS_4(sc, BWI_MAC_INTR_MASK, disable_intrs);
2322 }
2323
2324 static int
bwi_init_tx_ring32(struct bwi_softc * sc,int ring_idx)2325 bwi_init_tx_ring32(struct bwi_softc *sc, int ring_idx)
2326 {
2327 struct bwi_ring_data *rd;
2328 struct bwi_txbuf_data *tbd;
2329 uint32_t val, addr_hi, addr_lo;
2330
2331 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx));
2332 rd = &sc->sc_tx_rdata[ring_idx];
2333 tbd = &sc->sc_tx_bdata[ring_idx];
2334
2335 tbd->tbd_idx = 0;
2336 tbd->tbd_used = 0;
2337
2338 bzero(rd->rdata_desc, sizeof(struct bwi_desc32) * BWI_TX_NDESC);
2339 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
2340 BUS_DMASYNC_PREWRITE);
2341
2342 addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
2343 addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
2344
2345 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
2346 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
2347 BWI_TXRX32_RINGINFO_FUNC_MASK);
2348 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val);
2349
2350 val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
2351 BWI_TXRX32_CTRL_ENABLE;
2352 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val);
2353
2354 return 0;
2355 }
2356
2357 static void
bwi_init_rxdesc_ring32(struct bwi_softc * sc,uint32_t ctrl_base,bus_addr_t paddr,int hdr_size,int ndesc)2358 bwi_init_rxdesc_ring32(struct bwi_softc *sc, uint32_t ctrl_base,
2359 bus_addr_t paddr, int hdr_size, int ndesc)
2360 {
2361 uint32_t val, addr_hi, addr_lo;
2362
2363 addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
2364 addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
2365
2366 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
2367 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
2368 BWI_TXRX32_RINGINFO_FUNC_MASK);
2369 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val);
2370
2371 val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) |
2372 __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
2373 BWI_TXRX32_CTRL_ENABLE;
2374 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val);
2375
2376 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
2377 (ndesc - 1) * sizeof(struct bwi_desc32));
2378 }
2379
2380 static int
bwi_init_rx_ring32(struct bwi_softc * sc)2381 bwi_init_rx_ring32(struct bwi_softc *sc)
2382 {
2383 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2384 int i, error;
2385
2386 sc->sc_rx_bdata.rbd_idx = 0;
2387
2388 for (i = 0; i < BWI_RX_NDESC; ++i) {
2389 error = bwi_newbuf(sc, i, 1);
2390 if (error) {
2391 device_printf(sc->sc_dev,
2392 "can't allocate %dth RX buffer\n", i);
2393 return error;
2394 }
2395 }
2396 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap,
2397 BUS_DMASYNC_PREWRITE);
2398
2399 bwi_init_rxdesc_ring32(sc, rd->rdata_txrx_ctrl, rd->rdata_paddr,
2400 sizeof(struct bwi_rxbuf_hdr), BWI_RX_NDESC);
2401 return 0;
2402 }
2403
2404 static int
bwi_init_txstats32(struct bwi_softc * sc)2405 bwi_init_txstats32(struct bwi_softc *sc)
2406 {
2407 struct bwi_txstats_data *st = sc->sc_txstats;
2408 bus_addr_t stats_paddr;
2409 int i;
2410
2411 bzero(st->stats, BWI_TXSTATS_NDESC * sizeof(struct bwi_txstats));
2412 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_PREWRITE);
2413
2414 st->stats_idx = 0;
2415
2416 stats_paddr = st->stats_paddr;
2417 for (i = 0; i < BWI_TXSTATS_NDESC; ++i) {
2418 bwi_setup_desc32(sc, st->stats_ring, BWI_TXSTATS_NDESC, i,
2419 stats_paddr, sizeof(struct bwi_txstats), 0);
2420 stats_paddr += sizeof(struct bwi_txstats);
2421 }
2422 bus_dmamap_sync(st->stats_ring_dtag, st->stats_ring_dmap,
2423 BUS_DMASYNC_PREWRITE);
2424
2425 bwi_init_rxdesc_ring32(sc, st->stats_ctrl_base,
2426 st->stats_ring_paddr, 0, BWI_TXSTATS_NDESC);
2427 return 0;
2428 }
2429
2430 static void
bwi_setup_rx_desc32(struct bwi_softc * sc,int buf_idx,bus_addr_t paddr,int buf_len)2431 bwi_setup_rx_desc32(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
2432 int buf_len)
2433 {
2434 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2435
2436 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx));
2437 bwi_setup_desc32(sc, rd->rdata_desc, BWI_RX_NDESC, buf_idx,
2438 paddr, buf_len, 0);
2439 }
2440
2441 static void
bwi_setup_tx_desc32(struct bwi_softc * sc,struct bwi_ring_data * rd,int buf_idx,bus_addr_t paddr,int buf_len)2442 bwi_setup_tx_desc32(struct bwi_softc *sc, struct bwi_ring_data *rd,
2443 int buf_idx, bus_addr_t paddr, int buf_len)
2444 {
2445 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx));
2446 bwi_setup_desc32(sc, rd->rdata_desc, BWI_TX_NDESC, buf_idx,
2447 paddr, buf_len, 1);
2448 }
2449
2450 static int
bwi_init_tx_ring64(struct bwi_softc * sc,int ring_idx)2451 bwi_init_tx_ring64(struct bwi_softc *sc, int ring_idx)
2452 {
2453 /* TODO:64 */
2454 return EOPNOTSUPP;
2455 }
2456
2457 static int
bwi_init_rx_ring64(struct bwi_softc * sc)2458 bwi_init_rx_ring64(struct bwi_softc *sc)
2459 {
2460 /* TODO:64 */
2461 return EOPNOTSUPP;
2462 }
2463
2464 static int
bwi_init_txstats64(struct bwi_softc * sc)2465 bwi_init_txstats64(struct bwi_softc *sc)
2466 {
2467 /* TODO:64 */
2468 return EOPNOTSUPP;
2469 }
2470
2471 static void
bwi_setup_rx_desc64(struct bwi_softc * sc,int buf_idx,bus_addr_t paddr,int buf_len)2472 bwi_setup_rx_desc64(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
2473 int buf_len)
2474 {
2475 /* TODO:64 */
2476 }
2477
2478 static void
bwi_setup_tx_desc64(struct bwi_softc * sc,struct bwi_ring_data * rd,int buf_idx,bus_addr_t paddr,int buf_len)2479 bwi_setup_tx_desc64(struct bwi_softc *sc, struct bwi_ring_data *rd,
2480 int buf_idx, bus_addr_t paddr, int buf_len)
2481 {
2482 /* TODO:64 */
2483 }
2484
2485 static void
bwi_dma_buf_addr(void * arg,bus_dma_segment_t * seg,int nseg,bus_size_t mapsz __unused,int error)2486 bwi_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg,
2487 bus_size_t mapsz __unused, int error)
2488 {
2489 if (!error) {
2490 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg));
2491 *((bus_addr_t *)arg) = seg->ds_addr;
2492 }
2493 }
2494
2495 static int
bwi_newbuf(struct bwi_softc * sc,int buf_idx,int init)2496 bwi_newbuf(struct bwi_softc *sc, int buf_idx, int init)
2497 {
2498 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2499 struct bwi_rxbuf *rxbuf = &rbd->rbd_buf[buf_idx];
2500 struct bwi_rxbuf_hdr *hdr;
2501 bus_dmamap_t map;
2502 bus_addr_t paddr;
2503 struct mbuf *m;
2504 int error;
2505
2506 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx));
2507
2508 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
2509 if (m == NULL) {
2510 error = ENOBUFS;
2511
2512 /*
2513 * If the NIC is up and running, we need to:
2514 * - Clear RX buffer's header.
2515 * - Restore RX descriptor settings.
2516 */
2517 if (init)
2518 return error;
2519 else
2520 goto back;
2521 }
2522 m->m_len = m->m_pkthdr.len = MCLBYTES;
2523
2524 /*
2525 * Try to load RX buf into temporary DMA map
2526 */
2527 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, rbd->rbd_tmp_dmap, m,
2528 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
2529 if (error) {
2530 m_freem(m);
2531
2532 /*
2533 * See the comment above
2534 */
2535 if (init)
2536 return error;
2537 else
2538 goto back;
2539 }
2540
2541 if (!init)
2542 bus_dmamap_unload(sc->sc_buf_dtag, rxbuf->rb_dmap);
2543 rxbuf->rb_mbuf = m;
2544 rxbuf->rb_paddr = paddr;
2545
2546 /*
2547 * Swap RX buf's DMA map with the loaded temporary one
2548 */
2549 map = rxbuf->rb_dmap;
2550 rxbuf->rb_dmap = rbd->rbd_tmp_dmap;
2551 rbd->rbd_tmp_dmap = map;
2552
2553 back:
2554 /*
2555 * Clear RX buf header
2556 */
2557 hdr = mtod(rxbuf->rb_mbuf, struct bwi_rxbuf_hdr *);
2558 bzero(hdr, sizeof(*hdr));
2559 bus_dmamap_sync(sc->sc_buf_dtag, rxbuf->rb_dmap, BUS_DMASYNC_PREWRITE);
2560
2561 /*
2562 * Setup RX buf descriptor
2563 */
2564 sc->sc_setup_rxdesc(sc, buf_idx, rxbuf->rb_paddr,
2565 rxbuf->rb_mbuf->m_len - sizeof(*hdr));
2566 return error;
2567 }
2568
2569 static void
bwi_set_addr_filter(struct bwi_softc * sc,uint16_t addr_ofs,const uint8_t * addr)2570 bwi_set_addr_filter(struct bwi_softc *sc, uint16_t addr_ofs,
2571 const uint8_t *addr)
2572 {
2573 int i;
2574
2575 CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL,
2576 BWI_ADDR_FILTER_CTRL_SET | addr_ofs);
2577
2578 for (i = 0; i < (IEEE80211_ADDR_LEN / 2); ++i) {
2579 uint16_t addr_val;
2580
2581 addr_val = (uint16_t)addr[i * 2] |
2582 (((uint16_t)addr[(i * 2) + 1]) << 8);
2583 CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val);
2584 }
2585 }
2586
2587 static int
bwi_rxeof(struct bwi_softc * sc,int end_idx)2588 bwi_rxeof(struct bwi_softc *sc, int end_idx)
2589 {
2590 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2591 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2592 struct ieee80211com *ic = &sc->sc_ic;
2593 int idx, rx_data = 0;
2594
2595 idx = rbd->rbd_idx;
2596 while (idx != end_idx) {
2597 struct bwi_rxbuf *rb = &rbd->rbd_buf[idx];
2598 struct bwi_rxbuf_hdr *hdr;
2599 struct ieee80211_frame_min *wh;
2600 struct ieee80211_node *ni;
2601 struct mbuf *m;
2602 uint32_t plcp;
2603 uint16_t flags2;
2604 int buflen, wh_ofs, hdr_extra, rssi, noise, type, rate;
2605
2606 m = rb->rb_mbuf;
2607 bus_dmamap_sync(sc->sc_buf_dtag, rb->rb_dmap,
2608 BUS_DMASYNC_POSTREAD);
2609
2610 if (bwi_newbuf(sc, idx, 0)) {
2611 counter_u64_add(ic->ic_ierrors, 1);
2612 goto next;
2613 }
2614
2615 hdr = mtod(m, struct bwi_rxbuf_hdr *);
2616 flags2 = le16toh(hdr->rxh_flags2);
2617
2618 hdr_extra = 0;
2619 if (flags2 & BWI_RXH_F2_TYPE2FRAME)
2620 hdr_extra = 2;
2621 wh_ofs = hdr_extra + 6; /* XXX magic number */
2622
2623 buflen = le16toh(hdr->rxh_buflen);
2624 if (buflen < BWI_FRAME_MIN_LEN(wh_ofs)) {
2625 device_printf(sc->sc_dev,
2626 "%s: zero length data, hdr_extra %d\n",
2627 __func__, hdr_extra);
2628 counter_u64_add(ic->ic_ierrors, 1);
2629 m_freem(m);
2630 goto next;
2631 }
2632
2633 bcopy((uint8_t *)(hdr + 1) + hdr_extra, &plcp, sizeof(plcp));
2634 rssi = bwi_calc_rssi(sc, hdr);
2635 noise = bwi_calc_noise(sc);
2636
2637 m->m_len = m->m_pkthdr.len = buflen + sizeof(*hdr);
2638 m_adj(m, sizeof(*hdr) + wh_ofs);
2639
2640 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_OFDM)
2641 rate = bwi_plcp2rate(plcp, IEEE80211_T_OFDM);
2642 else
2643 rate = bwi_plcp2rate(plcp, IEEE80211_T_CCK);
2644
2645 /* RX radio tap */
2646 if (ieee80211_radiotap_active(ic))
2647 bwi_rx_radiotap(sc, m, hdr, &plcp, rate, rssi, noise);
2648
2649 m_adj(m, -IEEE80211_CRC_LEN);
2650
2651 BWI_UNLOCK(sc);
2652
2653 wh = mtod(m, struct ieee80211_frame_min *);
2654 ni = ieee80211_find_rxnode(ic, wh);
2655 if (ni != NULL) {
2656 type = ieee80211_input(ni, m, rssi - noise, noise);
2657 ieee80211_free_node(ni);
2658 } else
2659 type = ieee80211_input_all(ic, m, rssi - noise, noise);
2660 if (type == IEEE80211_FC0_TYPE_DATA) {
2661 rx_data = 1;
2662 sc->sc_rx_rate = rate;
2663 }
2664
2665 BWI_LOCK(sc);
2666 next:
2667 idx = (idx + 1) % BWI_RX_NDESC;
2668
2669 if (sc->sc_flags & BWI_F_STOP) {
2670 /*
2671 * Take the fast lane, don't do
2672 * any damage to softc
2673 */
2674 return -1;
2675 }
2676 }
2677
2678 rbd->rbd_idx = idx;
2679 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap,
2680 BUS_DMASYNC_PREWRITE);
2681
2682 return rx_data;
2683 }
2684
2685 static int
bwi_rxeof32(struct bwi_softc * sc)2686 bwi_rxeof32(struct bwi_softc *sc)
2687 {
2688 uint32_t val, rx_ctrl;
2689 int end_idx, rx_data;
2690
2691 rx_ctrl = sc->sc_rx_rdata.rdata_txrx_ctrl;
2692
2693 val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2694 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
2695 sizeof(struct bwi_desc32);
2696
2697 rx_data = bwi_rxeof(sc, end_idx);
2698 if (rx_data >= 0) {
2699 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_INDEX,
2700 end_idx * sizeof(struct bwi_desc32));
2701 }
2702 return rx_data;
2703 }
2704
2705 static int
bwi_rxeof64(struct bwi_softc * sc)2706 bwi_rxeof64(struct bwi_softc *sc)
2707 {
2708 /* TODO:64 */
2709 return 0;
2710 }
2711
2712 static void
bwi_reset_rx_ring32(struct bwi_softc * sc,uint32_t rx_ctrl)2713 bwi_reset_rx_ring32(struct bwi_softc *sc, uint32_t rx_ctrl)
2714 {
2715 int i;
2716
2717 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_CTRL, 0);
2718
2719 #define NRETRY 10
2720
2721 for (i = 0; i < NRETRY; ++i) {
2722 uint32_t status;
2723
2724 status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2725 if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) ==
2726 BWI_RX32_STATUS_STATE_DISABLED)
2727 break;
2728
2729 DELAY(1000);
2730 }
2731 if (i == NRETRY)
2732 device_printf(sc->sc_dev, "reset rx ring timedout\n");
2733
2734 #undef NRETRY
2735
2736 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_RINGINFO, 0);
2737 }
2738
2739 static void
bwi_free_txstats32(struct bwi_softc * sc)2740 bwi_free_txstats32(struct bwi_softc *sc)
2741 {
2742 bwi_reset_rx_ring32(sc, sc->sc_txstats->stats_ctrl_base);
2743 }
2744
2745 static void
bwi_free_rx_ring32(struct bwi_softc * sc)2746 bwi_free_rx_ring32(struct bwi_softc *sc)
2747 {
2748 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2749 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2750 int i;
2751
2752 bwi_reset_rx_ring32(sc, rd->rdata_txrx_ctrl);
2753
2754 for (i = 0; i < BWI_RX_NDESC; ++i) {
2755 struct bwi_rxbuf *rb = &rbd->rbd_buf[i];
2756
2757 if (rb->rb_mbuf != NULL) {
2758 bus_dmamap_unload(sc->sc_buf_dtag, rb->rb_dmap);
2759 m_freem(rb->rb_mbuf);
2760 rb->rb_mbuf = NULL;
2761 }
2762 }
2763 }
2764
2765 static void
bwi_free_tx_ring32(struct bwi_softc * sc,int ring_idx)2766 bwi_free_tx_ring32(struct bwi_softc *sc, int ring_idx)
2767 {
2768 struct bwi_ring_data *rd;
2769 struct bwi_txbuf_data *tbd;
2770 uint32_t state, val;
2771 int i;
2772
2773 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx));
2774 rd = &sc->sc_tx_rdata[ring_idx];
2775 tbd = &sc->sc_tx_bdata[ring_idx];
2776
2777 #define NRETRY 10
2778
2779 for (i = 0; i < NRETRY; ++i) {
2780 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2781 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
2782 if (state == BWI_TX32_STATUS_STATE_DISABLED ||
2783 state == BWI_TX32_STATUS_STATE_IDLE ||
2784 state == BWI_TX32_STATUS_STATE_STOPPED)
2785 break;
2786
2787 DELAY(1000);
2788 }
2789 if (i == NRETRY) {
2790 device_printf(sc->sc_dev,
2791 "%s: wait for TX ring(%d) stable timed out\n",
2792 __func__, ring_idx);
2793 }
2794
2795 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, 0);
2796 for (i = 0; i < NRETRY; ++i) {
2797 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2798 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
2799 if (state == BWI_TX32_STATUS_STATE_DISABLED)
2800 break;
2801
2802 DELAY(1000);
2803 }
2804 if (i == NRETRY)
2805 device_printf(sc->sc_dev, "%s: reset TX ring (%d) timed out\n",
2806 __func__, ring_idx);
2807
2808 #undef NRETRY
2809
2810 DELAY(1000);
2811
2812 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, 0);
2813
2814 for (i = 0; i < BWI_TX_NDESC; ++i) {
2815 struct bwi_txbuf *tb = &tbd->tbd_buf[i];
2816
2817 if (tb->tb_mbuf != NULL) {
2818 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap);
2819 m_freem(tb->tb_mbuf);
2820 tb->tb_mbuf = NULL;
2821 }
2822 if (tb->tb_ni != NULL) {
2823 ieee80211_free_node(tb->tb_ni);
2824 tb->tb_ni = NULL;
2825 }
2826 }
2827 }
2828
2829 static void
bwi_free_txstats64(struct bwi_softc * sc)2830 bwi_free_txstats64(struct bwi_softc *sc)
2831 {
2832 /* TODO:64 */
2833 }
2834
2835 static void
bwi_free_rx_ring64(struct bwi_softc * sc)2836 bwi_free_rx_ring64(struct bwi_softc *sc)
2837 {
2838 /* TODO:64 */
2839 }
2840
2841 static void
bwi_free_tx_ring64(struct bwi_softc * sc,int ring_idx)2842 bwi_free_tx_ring64(struct bwi_softc *sc, int ring_idx)
2843 {
2844 /* TODO:64 */
2845 }
2846
2847 /* XXX does not belong here */
2848 #define IEEE80211_OFDM_PLCP_RATE_MASK __BITS(3, 0)
2849 #define IEEE80211_OFDM_PLCP_LEN_MASK __BITS(16, 5)
2850
2851 static __inline void
bwi_ofdm_plcp_header(uint32_t * plcp0,int pkt_len,uint8_t rate)2852 bwi_ofdm_plcp_header(uint32_t *plcp0, int pkt_len, uint8_t rate)
2853 {
2854 uint32_t plcp;
2855
2856 plcp = __SHIFTIN(ieee80211_rate2plcp(rate, IEEE80211_T_OFDM),
2857 IEEE80211_OFDM_PLCP_RATE_MASK) |
2858 __SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK);
2859 *plcp0 = htole32(plcp);
2860 }
2861
2862 static __inline void
bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr * plcp,int pkt_len,uint8_t rate)2863 bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr *plcp, int pkt_len,
2864 uint8_t rate)
2865 {
2866 int len, service, pkt_bitlen;
2867
2868 pkt_bitlen = pkt_len * NBBY;
2869 len = howmany(pkt_bitlen * 2, rate);
2870
2871 service = IEEE80211_PLCP_SERVICE_LOCKED;
2872 if (rate == (11 * 2)) {
2873 int pkt_bitlen1;
2874
2875 /*
2876 * PLCP service field needs to be adjusted,
2877 * if TX rate is 11Mbytes/s
2878 */
2879 pkt_bitlen1 = len * 11;
2880 if (pkt_bitlen1 - pkt_bitlen >= NBBY)
2881 service |= IEEE80211_PLCP_SERVICE_LENEXT7;
2882 }
2883
2884 plcp->i_signal = ieee80211_rate2plcp(rate, IEEE80211_T_CCK);
2885 plcp->i_service = service;
2886 plcp->i_length = htole16(len);
2887 /* NOTE: do NOT touch i_crc */
2888 }
2889
2890 static __inline void
bwi_plcp_header(const struct ieee80211_rate_table * rt,void * plcp,int pkt_len,uint8_t rate)2891 bwi_plcp_header(const struct ieee80211_rate_table *rt,
2892 void *plcp, int pkt_len, uint8_t rate)
2893 {
2894 enum ieee80211_phytype modtype;
2895
2896 /*
2897 * Assume caller has zeroed 'plcp'
2898 */
2899 modtype = ieee80211_rate2phytype(rt, rate);
2900 if (modtype == IEEE80211_T_OFDM)
2901 bwi_ofdm_plcp_header(plcp, pkt_len, rate);
2902 else if (modtype == IEEE80211_T_DS)
2903 bwi_ds_plcp_header(plcp, pkt_len, rate);
2904 else
2905 panic("unsupport modulation type %u\n", modtype);
2906 }
2907
2908 static int
bwi_encap(struct bwi_softc * sc,int idx,struct mbuf * m,struct ieee80211_node * ni)2909 bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m,
2910 struct ieee80211_node *ni)
2911 {
2912 struct ieee80211vap *vap = ni->ni_vap;
2913 struct ieee80211com *ic = &sc->sc_ic;
2914 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING];
2915 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
2916 struct bwi_txbuf *tb = &tbd->tbd_buf[idx];
2917 struct bwi_mac *mac;
2918 struct bwi_txbuf_hdr *hdr;
2919 struct ieee80211_frame *wh;
2920 const struct ieee80211_txparam *tp = ni->ni_txparms;
2921 uint8_t rate, rate_fb;
2922 uint32_t mac_ctrl;
2923 uint16_t phy_ctrl;
2924 bus_addr_t paddr;
2925 int type, ismcast, pkt_len, error, rix;
2926 #if 0
2927 const uint8_t *p;
2928 int i;
2929 #endif
2930
2931 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
2932 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
2933 mac = (struct bwi_mac *)sc->sc_cur_regwin;
2934
2935 wh = mtod(m, struct ieee80211_frame *);
2936 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
2937 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
2938
2939 /* Get 802.11 frame len before prepending TX header */
2940 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN;
2941
2942 /*
2943 * Find TX rate
2944 */
2945 if (type != IEEE80211_FC0_TYPE_DATA || (m->m_flags & M_EAPOL)) {
2946 rate = rate_fb = tp->mgmtrate;
2947 } else if (ismcast) {
2948 rate = rate_fb = tp->mcastrate;
2949 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) {
2950 rate = rate_fb = tp->ucastrate;
2951 } else {
2952 rix = ieee80211_ratectl_rate(ni, NULL, pkt_len);
2953 rate = ni->ni_txrate;
2954
2955 if (rix > 0) {
2956 rate_fb = ni->ni_rates.rs_rates[rix-1] &
2957 IEEE80211_RATE_VAL;
2958 } else {
2959 rate_fb = rate;
2960 }
2961 }
2962 tb->tb_rate[0] = rate;
2963 tb->tb_rate[1] = rate_fb;
2964 sc->sc_tx_rate = rate;
2965
2966 /*
2967 * TX radio tap
2968 */
2969 if (ieee80211_radiotap_active_vap(vap)) {
2970 sc->sc_tx_th.wt_flags = 0;
2971 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED)
2972 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
2973 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_DS &&
2974 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
2975 rate != (1 * 2)) {
2976 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
2977 }
2978 sc->sc_tx_th.wt_rate = rate;
2979
2980 ieee80211_radiotap_tx(vap, m);
2981 }
2982
2983 /*
2984 * Setup the embedded TX header
2985 */
2986 M_PREPEND(m, sizeof(*hdr), M_NOWAIT);
2987 if (m == NULL) {
2988 device_printf(sc->sc_dev, "%s: prepend TX header failed\n",
2989 __func__);
2990 return ENOBUFS;
2991 }
2992 hdr = mtod(m, struct bwi_txbuf_hdr *);
2993
2994 bzero(hdr, sizeof(*hdr));
2995
2996 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc));
2997 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1));
2998
2999 if (!ismcast) {
3000 uint16_t dur;
3001
3002 dur = ieee80211_ack_duration(sc->sc_rates, rate,
3003 ic->ic_flags & ~IEEE80211_F_SHPREAMBLE);
3004
3005 hdr->txh_fb_duration = htole16(dur);
3006 }
3007
3008 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) |
3009 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK);
3010
3011 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate);
3012 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb);
3013
3014 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode,
3015 BWI_TXH_PHY_C_ANTMODE_MASK);
3016 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM)
3017 phy_ctrl |= BWI_TXH_PHY_C_OFDM;
3018 else if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && rate != (2 * 1))
3019 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE;
3020
3021 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG;
3022 if (!ismcast)
3023 mac_ctrl |= BWI_TXH_MAC_C_ACK;
3024 if (ieee80211_rate2phytype(sc->sc_rates, rate_fb) == IEEE80211_T_OFDM)
3025 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM;
3026
3027 hdr->txh_mac_ctrl = htole32(mac_ctrl);
3028 hdr->txh_phy_ctrl = htole16(phy_ctrl);
3029
3030 /* Catch any further usage */
3031 hdr = NULL;
3032 wh = NULL;
3033
3034 /* DMA load */
3035 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3036 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
3037 if (error && error != EFBIG) {
3038 device_printf(sc->sc_dev, "%s: can't load TX buffer (1) %d\n",
3039 __func__, error);
3040 goto back;
3041 }
3042
3043 if (error) { /* error == EFBIG */
3044 struct mbuf *m_new;
3045
3046 m_new = m_defrag(m, M_NOWAIT);
3047 if (m_new == NULL) {
3048 device_printf(sc->sc_dev,
3049 "%s: can't defrag TX buffer\n", __func__);
3050 error = ENOBUFS;
3051 goto back;
3052 } else {
3053 m = m_new;
3054 }
3055
3056 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3057 bwi_dma_buf_addr, &paddr,
3058 BUS_DMA_NOWAIT);
3059 if (error) {
3060 device_printf(sc->sc_dev,
3061 "%s: can't load TX buffer (2) %d\n",
3062 __func__, error);
3063 goto back;
3064 }
3065 }
3066 error = 0;
3067
3068 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE);
3069
3070 tb->tb_mbuf = m;
3071 tb->tb_ni = ni;
3072
3073 #if 0
3074 p = mtod(m, const uint8_t *);
3075 for (i = 0; i < m->m_pkthdr.len; ++i) {
3076 if (i != 0 && i % 8 == 0)
3077 printf("\n");
3078 printf("%02x ", p[i]);
3079 }
3080 printf("\n");
3081 #endif
3082 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n",
3083 idx, pkt_len, m->m_pkthdr.len);
3084
3085 /* Setup TX descriptor */
3086 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len);
3087 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
3088 BUS_DMASYNC_PREWRITE);
3089
3090 /* Kick start */
3091 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx);
3092
3093 back:
3094 if (error)
3095 m_freem(m);
3096 return error;
3097 }
3098
3099 static int
bwi_encap_raw(struct bwi_softc * sc,int idx,struct mbuf * m,struct ieee80211_node * ni,const struct ieee80211_bpf_params * params)3100 bwi_encap_raw(struct bwi_softc *sc, int idx, struct mbuf *m,
3101 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params)
3102 {
3103 struct ieee80211vap *vap = ni->ni_vap;
3104 struct ieee80211com *ic = ni->ni_ic;
3105 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING];
3106 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
3107 struct bwi_txbuf *tb = &tbd->tbd_buf[idx];
3108 struct bwi_mac *mac;
3109 struct bwi_txbuf_hdr *hdr;
3110 struct ieee80211_frame *wh;
3111 uint8_t rate, rate_fb;
3112 uint32_t mac_ctrl;
3113 uint16_t phy_ctrl;
3114 bus_addr_t paddr;
3115 int ismcast, pkt_len, error;
3116
3117 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3118 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3119 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3120
3121 wh = mtod(m, struct ieee80211_frame *);
3122 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
3123
3124 /* Get 802.11 frame len before prepending TX header */
3125 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN;
3126
3127 /*
3128 * Find TX rate
3129 */
3130 rate = params->ibp_rate0;
3131 if (!ieee80211_isratevalid(ic->ic_rt, rate)) {
3132 /* XXX fall back to mcast/mgmt rate? */
3133 m_freem(m);
3134 return EINVAL;
3135 }
3136 if (params->ibp_try1 != 0) {
3137 rate_fb = params->ibp_rate1;
3138 if (!ieee80211_isratevalid(ic->ic_rt, rate_fb)) {
3139 /* XXX fall back to rate0? */
3140 m_freem(m);
3141 return EINVAL;
3142 }
3143 } else
3144 rate_fb = rate;
3145 tb->tb_rate[0] = rate;
3146 tb->tb_rate[1] = rate_fb;
3147 sc->sc_tx_rate = rate;
3148
3149 /*
3150 * TX radio tap
3151 */
3152 if (ieee80211_radiotap_active_vap(vap)) {
3153 sc->sc_tx_th.wt_flags = 0;
3154 /* XXX IEEE80211_BPF_CRYPTO */
3155 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED)
3156 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
3157 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
3158 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3159 sc->sc_tx_th.wt_rate = rate;
3160
3161 ieee80211_radiotap_tx(vap, m);
3162 }
3163
3164 /*
3165 * Setup the embedded TX header
3166 */
3167 M_PREPEND(m, sizeof(*hdr), M_NOWAIT);
3168 if (m == NULL) {
3169 device_printf(sc->sc_dev, "%s: prepend TX header failed\n",
3170 __func__);
3171 return ENOBUFS;
3172 }
3173 hdr = mtod(m, struct bwi_txbuf_hdr *);
3174
3175 bzero(hdr, sizeof(*hdr));
3176
3177 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc));
3178 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1));
3179
3180 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG;
3181 if (!ismcast && (params->ibp_flags & IEEE80211_BPF_NOACK) == 0) {
3182 uint16_t dur;
3183
3184 dur = ieee80211_ack_duration(sc->sc_rates, rate_fb, 0);
3185
3186 hdr->txh_fb_duration = htole16(dur);
3187 mac_ctrl |= BWI_TXH_MAC_C_ACK;
3188 }
3189
3190 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) |
3191 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK);
3192
3193 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate);
3194 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb);
3195
3196 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode,
3197 BWI_TXH_PHY_C_ANTMODE_MASK);
3198 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) {
3199 phy_ctrl |= BWI_TXH_PHY_C_OFDM;
3200 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM;
3201 } else if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
3202 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE;
3203
3204 hdr->txh_mac_ctrl = htole32(mac_ctrl);
3205 hdr->txh_phy_ctrl = htole16(phy_ctrl);
3206
3207 /* Catch any further usage */
3208 hdr = NULL;
3209 wh = NULL;
3210
3211 /* DMA load */
3212 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3213 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
3214 if (error != 0) {
3215 struct mbuf *m_new;
3216
3217 if (error != EFBIG) {
3218 device_printf(sc->sc_dev,
3219 "%s: can't load TX buffer (1) %d\n",
3220 __func__, error);
3221 goto back;
3222 }
3223 m_new = m_defrag(m, M_NOWAIT);
3224 if (m_new == NULL) {
3225 device_printf(sc->sc_dev,
3226 "%s: can't defrag TX buffer\n", __func__);
3227 error = ENOBUFS;
3228 goto back;
3229 }
3230 m = m_new;
3231 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3232 bwi_dma_buf_addr, &paddr,
3233 BUS_DMA_NOWAIT);
3234 if (error) {
3235 device_printf(sc->sc_dev,
3236 "%s: can't load TX buffer (2) %d\n",
3237 __func__, error);
3238 goto back;
3239 }
3240 }
3241
3242 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE);
3243
3244 tb->tb_mbuf = m;
3245 tb->tb_ni = ni;
3246
3247 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n",
3248 idx, pkt_len, m->m_pkthdr.len);
3249
3250 /* Setup TX descriptor */
3251 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len);
3252 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
3253 BUS_DMASYNC_PREWRITE);
3254
3255 /* Kick start */
3256 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx);
3257 back:
3258 if (error)
3259 m_freem(m);
3260 return error;
3261 }
3262
3263 static void
bwi_start_tx32(struct bwi_softc * sc,uint32_t tx_ctrl,int idx)3264 bwi_start_tx32(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
3265 {
3266 idx = (idx + 1) % BWI_TX_NDESC;
3267 CSR_WRITE_4(sc, tx_ctrl + BWI_TX32_INDEX,
3268 idx * sizeof(struct bwi_desc32));
3269 }
3270
3271 static void
bwi_start_tx64(struct bwi_softc * sc,uint32_t tx_ctrl,int idx)3272 bwi_start_tx64(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
3273 {
3274 /* TODO:64 */
3275 }
3276
3277 static void
bwi_txeof_status32(struct bwi_softc * sc)3278 bwi_txeof_status32(struct bwi_softc *sc)
3279 {
3280 uint32_t val, ctrl_base;
3281 int end_idx;
3282
3283 ctrl_base = sc->sc_txstats->stats_ctrl_base;
3284
3285 val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS);
3286 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
3287 sizeof(struct bwi_desc32);
3288
3289 bwi_txeof_status(sc, end_idx);
3290
3291 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
3292 end_idx * sizeof(struct bwi_desc32));
3293
3294 bwi_start_locked(sc);
3295 }
3296
3297 static void
bwi_txeof_status64(struct bwi_softc * sc)3298 bwi_txeof_status64(struct bwi_softc *sc)
3299 {
3300 /* TODO:64 */
3301 }
3302
3303 static void
_bwi_txeof(struct bwi_softc * sc,uint16_t tx_id,int acked,int data_txcnt)3304 _bwi_txeof(struct bwi_softc *sc, uint16_t tx_id, int acked, int data_txcnt)
3305 {
3306 struct bwi_txbuf_data *tbd;
3307 struct bwi_txbuf *tb;
3308 int ring_idx, buf_idx;
3309 struct ieee80211_node *ni;
3310
3311 if (tx_id == 0) {
3312 device_printf(sc->sc_dev, "%s: zero tx id\n", __func__);
3313 return;
3314 }
3315
3316 ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK);
3317 buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK);
3318
3319 KASSERT(ring_idx == BWI_TX_DATA_RING, ("ring_idx %d", ring_idx));
3320 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx));
3321
3322 tbd = &sc->sc_tx_bdata[ring_idx];
3323 KASSERT(tbd->tbd_used > 0, ("tbd_used %d", tbd->tbd_used));
3324 tbd->tbd_used--;
3325
3326 tb = &tbd->tbd_buf[buf_idx];
3327 DPRINTF(sc, BWI_DBG_TXEOF, "txeof idx %d, "
3328 "acked %d, data_txcnt %d, ni %p\n",
3329 buf_idx, acked, data_txcnt, tb->tb_ni);
3330
3331 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap);
3332
3333 if ((ni = tb->tb_ni) != NULL) {
3334 const struct bwi_txbuf_hdr *hdr =
3335 mtod(tb->tb_mbuf, const struct bwi_txbuf_hdr *);
3336 struct ieee80211_ratectl_tx_status txs;
3337
3338 /* NB: update rate control only for unicast frames */
3339 if (hdr->txh_mac_ctrl & htole32(BWI_TXH_MAC_C_ACK)) {
3340 /*
3341 * Feed back 'acked and data_txcnt'. Note that the
3342 * generic AMRR code only understands one tx rate
3343 * and the estimator doesn't handle real retry counts
3344 * well so to avoid over-aggressive downshifting we
3345 * treat any number of retries as "1".
3346 */
3347 txs.flags = IEEE80211_RATECTL_STATUS_LONG_RETRY;
3348 txs.long_retries = acked;
3349 if (data_txcnt > 1)
3350 txs.status = IEEE80211_RATECTL_TX_SUCCESS;
3351 else {
3352 txs.status =
3353 IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED;
3354 }
3355 ieee80211_ratectl_tx_complete(ni, &txs);
3356 }
3357 ieee80211_tx_complete(ni, tb->tb_mbuf, !acked);
3358 tb->tb_ni = NULL;
3359 } else
3360 m_freem(tb->tb_mbuf);
3361 tb->tb_mbuf = NULL;
3362
3363 if (tbd->tbd_used == 0)
3364 sc->sc_tx_timer = 0;
3365 }
3366
3367 static void
bwi_txeof_status(struct bwi_softc * sc,int end_idx)3368 bwi_txeof_status(struct bwi_softc *sc, int end_idx)
3369 {
3370 struct bwi_txstats_data *st = sc->sc_txstats;
3371 int idx;
3372
3373 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_POSTREAD);
3374
3375 idx = st->stats_idx;
3376 while (idx != end_idx) {
3377 const struct bwi_txstats *stats = &st->stats[idx];
3378
3379 if ((stats->txs_flags & BWI_TXS_F_PENDING) == 0) {
3380 int data_txcnt;
3381
3382 data_txcnt = __SHIFTOUT(stats->txs_txcnt,
3383 BWI_TXS_TXCNT_DATA);
3384 _bwi_txeof(sc, le16toh(stats->txs_id),
3385 stats->txs_flags & BWI_TXS_F_ACKED,
3386 data_txcnt);
3387 }
3388 idx = (idx + 1) % BWI_TXSTATS_NDESC;
3389 }
3390 st->stats_idx = idx;
3391 }
3392
3393 static void
bwi_txeof(struct bwi_softc * sc)3394 bwi_txeof(struct bwi_softc *sc)
3395 {
3396
3397 for (;;) {
3398 uint32_t tx_status0, tx_status1 __unused;
3399 uint16_t tx_id;
3400 int data_txcnt;
3401
3402 tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS0);
3403 if ((tx_status0 & BWI_TXSTATUS0_VALID) == 0)
3404 break;
3405 tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS1);
3406
3407 tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS0_TXID_MASK);
3408 data_txcnt = __SHIFTOUT(tx_status0,
3409 BWI_TXSTATUS0_DATA_TXCNT_MASK);
3410
3411 if (tx_status0 & (BWI_TXSTATUS0_AMPDU | BWI_TXSTATUS0_PENDING))
3412 continue;
3413
3414 _bwi_txeof(sc, le16toh(tx_id), tx_status0 & BWI_TXSTATUS0_ACKED,
3415 data_txcnt);
3416 }
3417
3418 bwi_start_locked(sc);
3419 }
3420
3421 static int
bwi_bbp_power_on(struct bwi_softc * sc,enum bwi_clock_mode clk_mode)3422 bwi_bbp_power_on(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
3423 {
3424 bwi_power_on(sc, 1);
3425 return bwi_set_clock_mode(sc, clk_mode);
3426 }
3427
3428 static void
bwi_bbp_power_off(struct bwi_softc * sc)3429 bwi_bbp_power_off(struct bwi_softc *sc)
3430 {
3431 bwi_set_clock_mode(sc, BWI_CLOCK_MODE_SLOW);
3432 bwi_power_off(sc, 1);
3433 }
3434
3435 static int
bwi_get_pwron_delay(struct bwi_softc * sc)3436 bwi_get_pwron_delay(struct bwi_softc *sc)
3437 {
3438 struct bwi_regwin *com, *old;
3439 struct bwi_clock_freq freq;
3440 uint32_t val;
3441 int error;
3442
3443 com = &sc->sc_com_regwin;
3444 KASSERT(BWI_REGWIN_EXIST(com), ("no regwin"));
3445
3446 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
3447 return 0;
3448
3449 error = bwi_regwin_switch(sc, com, &old);
3450 if (error)
3451 return error;
3452
3453 bwi_get_clock_freq(sc, &freq);
3454
3455 val = CSR_READ_4(sc, BWI_PLL_ON_DELAY);
3456 sc->sc_pwron_delay = howmany((val + 2) * 1000000, freq.clkfreq_min);
3457 DPRINTF(sc, BWI_DBG_ATTACH, "power on delay %u\n", sc->sc_pwron_delay);
3458
3459 return bwi_regwin_switch(sc, old, NULL);
3460 }
3461
3462 static int
bwi_bus_attach(struct bwi_softc * sc)3463 bwi_bus_attach(struct bwi_softc *sc)
3464 {
3465 struct bwi_regwin *bus, *old;
3466 int error;
3467
3468 bus = &sc->sc_bus_regwin;
3469
3470 error = bwi_regwin_switch(sc, bus, &old);
3471 if (error)
3472 return error;
3473
3474 if (!bwi_regwin_is_enabled(sc, bus))
3475 bwi_regwin_enable(sc, bus, 0);
3476
3477 /* Disable interripts */
3478 CSR_WRITE_4(sc, BWI_INTRVEC, 0);
3479
3480 return bwi_regwin_switch(sc, old, NULL);
3481 }
3482
3483 static const char *
bwi_regwin_name(const struct bwi_regwin * rw)3484 bwi_regwin_name(const struct bwi_regwin *rw)
3485 {
3486 switch (rw->rw_type) {
3487 case BWI_REGWIN_T_COM:
3488 return "COM";
3489 case BWI_REGWIN_T_BUSPCI:
3490 return "PCI";
3491 case BWI_REGWIN_T_MAC:
3492 return "MAC";
3493 case BWI_REGWIN_T_BUSPCIE:
3494 return "PCIE";
3495 }
3496 panic("unknown regwin type 0x%04x\n", rw->rw_type);
3497 return NULL;
3498 }
3499
3500 static uint32_t
bwi_regwin_disable_bits(struct bwi_softc * sc)3501 bwi_regwin_disable_bits(struct bwi_softc *sc)
3502 {
3503 uint32_t busrev;
3504
3505 /* XXX cache this */
3506 busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK);
3507 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_MISC,
3508 "bus rev %u\n", busrev);
3509
3510 if (busrev == BWI_BUSREV_0)
3511 return BWI_STATE_LO_DISABLE1;
3512 else if (busrev == BWI_BUSREV_1)
3513 return BWI_STATE_LO_DISABLE2;
3514 else
3515 return (BWI_STATE_LO_DISABLE1 | BWI_STATE_LO_DISABLE2);
3516 }
3517
3518 int
bwi_regwin_is_enabled(struct bwi_softc * sc,struct bwi_regwin * rw)3519 bwi_regwin_is_enabled(struct bwi_softc *sc, struct bwi_regwin *rw)
3520 {
3521 uint32_t val, disable_bits;
3522
3523 disable_bits = bwi_regwin_disable_bits(sc);
3524 val = CSR_READ_4(sc, BWI_STATE_LO);
3525
3526 if ((val & (BWI_STATE_LO_CLOCK |
3527 BWI_STATE_LO_RESET |
3528 disable_bits)) == BWI_STATE_LO_CLOCK) {
3529 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is enabled\n",
3530 bwi_regwin_name(rw));
3531 return 1;
3532 } else {
3533 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is disabled\n",
3534 bwi_regwin_name(rw));
3535 return 0;
3536 }
3537 }
3538
3539 void
bwi_regwin_disable(struct bwi_softc * sc,struct bwi_regwin * rw,uint32_t flags)3540 bwi_regwin_disable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
3541 {
3542 uint32_t state_lo, disable_bits;
3543 int i;
3544
3545 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3546
3547 /*
3548 * If current regwin is in 'reset' state, it was already disabled.
3549 */
3550 if (state_lo & BWI_STATE_LO_RESET) {
3551 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT,
3552 "%s was already disabled\n", bwi_regwin_name(rw));
3553 return;
3554 }
3555
3556 disable_bits = bwi_regwin_disable_bits(sc);
3557
3558 /*
3559 * Disable normal clock
3560 */
3561 state_lo = BWI_STATE_LO_CLOCK | disable_bits;
3562 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3563
3564 /*
3565 * Wait until normal clock is disabled
3566 */
3567 #define NRETRY 1000
3568 for (i = 0; i < NRETRY; ++i) {
3569 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3570 if (state_lo & disable_bits)
3571 break;
3572 DELAY(10);
3573 }
3574 if (i == NRETRY) {
3575 device_printf(sc->sc_dev, "%s disable clock timeout\n",
3576 bwi_regwin_name(rw));
3577 }
3578
3579 for (i = 0; i < NRETRY; ++i) {
3580 uint32_t state_hi;
3581
3582 state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3583 if ((state_hi & BWI_STATE_HI_BUSY) == 0)
3584 break;
3585 DELAY(10);
3586 }
3587 if (i == NRETRY) {
3588 device_printf(sc->sc_dev, "%s wait BUSY unset timeout\n",
3589 bwi_regwin_name(rw));
3590 }
3591 #undef NRETRY
3592
3593 /*
3594 * Reset and disable regwin with gated clock
3595 */
3596 state_lo = BWI_STATE_LO_RESET | disable_bits |
3597 BWI_STATE_LO_CLOCK | BWI_STATE_LO_GATED_CLOCK |
3598 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3599 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3600
3601 /* Flush pending bus write */
3602 CSR_READ_4(sc, BWI_STATE_LO);
3603 DELAY(1);
3604
3605 /* Reset and disable regwin */
3606 state_lo = BWI_STATE_LO_RESET | disable_bits |
3607 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3608 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3609
3610 /* Flush pending bus write */
3611 CSR_READ_4(sc, BWI_STATE_LO);
3612 DELAY(1);
3613 }
3614
3615 void
bwi_regwin_enable(struct bwi_softc * sc,struct bwi_regwin * rw,uint32_t flags)3616 bwi_regwin_enable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
3617 {
3618 uint32_t state_lo, state_hi, imstate;
3619
3620 bwi_regwin_disable(sc, rw, flags);
3621
3622 /* Reset regwin with gated clock */
3623 state_lo = BWI_STATE_LO_RESET |
3624 BWI_STATE_LO_CLOCK |
3625 BWI_STATE_LO_GATED_CLOCK |
3626 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3627 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3628
3629 /* Flush pending bus write */
3630 CSR_READ_4(sc, BWI_STATE_LO);
3631 DELAY(1);
3632
3633 state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3634 if (state_hi & BWI_STATE_HI_SERROR)
3635 CSR_WRITE_4(sc, BWI_STATE_HI, 0);
3636
3637 imstate = CSR_READ_4(sc, BWI_IMSTATE);
3638 if (imstate & (BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT)) {
3639 imstate &= ~(BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT);
3640 CSR_WRITE_4(sc, BWI_IMSTATE, imstate);
3641 }
3642
3643 /* Enable regwin with gated clock */
3644 state_lo = BWI_STATE_LO_CLOCK |
3645 BWI_STATE_LO_GATED_CLOCK |
3646 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3647 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3648
3649 /* Flush pending bus write */
3650 CSR_READ_4(sc, BWI_STATE_LO);
3651 DELAY(1);
3652
3653 /* Enable regwin with normal clock */
3654 state_lo = BWI_STATE_LO_CLOCK |
3655 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3656 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3657
3658 /* Flush pending bus write */
3659 CSR_READ_4(sc, BWI_STATE_LO);
3660 DELAY(1);
3661 }
3662
3663 static void
bwi_set_bssid(struct bwi_softc * sc,const uint8_t * bssid)3664 bwi_set_bssid(struct bwi_softc *sc, const uint8_t *bssid)
3665 {
3666 struct bwi_mac *mac;
3667 struct bwi_myaddr_bssid buf;
3668 const uint8_t *p;
3669 uint32_t val;
3670 int n, i;
3671
3672 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3673 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3674 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3675
3676 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_BSSID, bssid);
3677
3678 bcopy(sc->sc_ic.ic_macaddr, buf.myaddr, sizeof(buf.myaddr));
3679 bcopy(bssid, buf.bssid, sizeof(buf.bssid));
3680
3681 n = sizeof(buf) / sizeof(val);
3682 p = (const uint8_t *)&buf;
3683 for (i = 0; i < n; ++i) {
3684 int j;
3685
3686 val = 0;
3687 for (j = 0; j < sizeof(val); ++j)
3688 val |= ((uint32_t)(*p++)) << (j * 8);
3689
3690 TMPLT_WRITE_4(mac, 0x20 + (i * sizeof(val)), val);
3691 }
3692 }
3693
3694 static void
bwi_updateslot(struct ieee80211com * ic)3695 bwi_updateslot(struct ieee80211com *ic)
3696 {
3697 struct bwi_softc *sc = ic->ic_softc;
3698 struct bwi_mac *mac;
3699
3700 BWI_LOCK(sc);
3701 if (sc->sc_flags & BWI_F_RUNNING) {
3702 DPRINTF(sc, BWI_DBG_80211, "%s\n", __func__);
3703
3704 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3705 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3706 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3707
3708 bwi_mac_updateslot(mac, (ic->ic_flags & IEEE80211_F_SHSLOT));
3709 }
3710 BWI_UNLOCK(sc);
3711 }
3712
3713 static void
bwi_calibrate(void * xsc)3714 bwi_calibrate(void *xsc)
3715 {
3716 struct bwi_softc *sc = xsc;
3717 struct bwi_mac *mac;
3718
3719 BWI_ASSERT_LOCKED(sc);
3720
3721 KASSERT(sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR,
3722 ("opmode %d", sc->sc_ic.ic_opmode));
3723
3724 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3725 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3726 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3727
3728 bwi_mac_calibrate_txpower(mac, sc->sc_txpwrcb_type);
3729 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB;
3730
3731 /* XXX 15 seconds */
3732 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc);
3733 }
3734
3735 static int
bwi_calc_rssi(struct bwi_softc * sc,const struct bwi_rxbuf_hdr * hdr)3736 bwi_calc_rssi(struct bwi_softc *sc, const struct bwi_rxbuf_hdr *hdr)
3737 {
3738 struct bwi_mac *mac;
3739
3740 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3741 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3742 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3743
3744 return bwi_rf_calc_rssi(mac, hdr);
3745 }
3746
3747 static int
bwi_calc_noise(struct bwi_softc * sc)3748 bwi_calc_noise(struct bwi_softc *sc)
3749 {
3750 struct bwi_mac *mac;
3751
3752 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3753 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3754 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3755
3756 return bwi_rf_calc_noise(mac);
3757 }
3758
3759 static __inline uint8_t
bwi_plcp2rate(const uint32_t plcp0,enum ieee80211_phytype type)3760 bwi_plcp2rate(const uint32_t plcp0, enum ieee80211_phytype type)
3761 {
3762 uint32_t plcp = le32toh(plcp0) & IEEE80211_OFDM_PLCP_RATE_MASK;
3763 return (ieee80211_plcp2rate(plcp, type));
3764 }
3765
3766 static void
bwi_rx_radiotap(struct bwi_softc * sc,struct mbuf * m,struct bwi_rxbuf_hdr * hdr,const void * plcp,int rate,int rssi,int noise)3767 bwi_rx_radiotap(struct bwi_softc *sc, struct mbuf *m,
3768 struct bwi_rxbuf_hdr *hdr, const void *plcp, int rate, int rssi, int noise)
3769 {
3770 const struct ieee80211_frame_min *wh;
3771
3772 sc->sc_rx_th.wr_flags = IEEE80211_RADIOTAP_F_FCS;
3773 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_SHPREAMBLE)
3774 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3775
3776 wh = mtod(m, const struct ieee80211_frame_min *);
3777 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED)
3778 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP;
3779
3780 sc->sc_rx_th.wr_tsf = hdr->rxh_tsf; /* No endian conversion */
3781 sc->sc_rx_th.wr_rate = rate;
3782 sc->sc_rx_th.wr_antsignal = rssi;
3783 sc->sc_rx_th.wr_antnoise = noise;
3784 }
3785
3786 static void
bwi_led_attach(struct bwi_softc * sc)3787 bwi_led_attach(struct bwi_softc *sc)
3788 {
3789 const uint8_t *led_act = NULL;
3790 uint16_t gpio, val[BWI_LED_MAX];
3791 int i;
3792
3793 for (i = 0; i < nitems(bwi_vendor_led_act); ++i) {
3794 if (sc->sc_pci_subvid == bwi_vendor_led_act[i].vid) {
3795 led_act = bwi_vendor_led_act[i].led_act;
3796 break;
3797 }
3798 }
3799 if (led_act == NULL)
3800 led_act = bwi_default_led_act;
3801
3802 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO01);
3803 val[0] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_0);
3804 val[1] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_1);
3805
3806 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO23);
3807 val[2] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_2);
3808 val[3] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_3);
3809
3810 for (i = 0; i < BWI_LED_MAX; ++i) {
3811 struct bwi_led *led = &sc->sc_leds[i];
3812
3813 if (val[i] == 0xff) {
3814 led->l_act = led_act[i];
3815 } else {
3816 if (val[i] & BWI_LED_ACT_LOW)
3817 led->l_flags |= BWI_LED_F_ACTLOW;
3818 led->l_act = __SHIFTOUT(val[i], BWI_LED_ACT_MASK);
3819 }
3820 led->l_mask = (1 << i);
3821
3822 if (led->l_act == BWI_LED_ACT_BLINK_SLOW ||
3823 led->l_act == BWI_LED_ACT_BLINK_POLL ||
3824 led->l_act == BWI_LED_ACT_BLINK) {
3825 led->l_flags |= BWI_LED_F_BLINK;
3826 if (led->l_act == BWI_LED_ACT_BLINK_POLL)
3827 led->l_flags |= BWI_LED_F_POLLABLE;
3828 else if (led->l_act == BWI_LED_ACT_BLINK_SLOW)
3829 led->l_flags |= BWI_LED_F_SLOW;
3830
3831 if (sc->sc_blink_led == NULL) {
3832 sc->sc_blink_led = led;
3833 if (led->l_flags & BWI_LED_F_SLOW)
3834 BWI_LED_SLOWDOWN(sc->sc_led_idle);
3835 }
3836 }
3837
3838 DPRINTF(sc, BWI_DBG_LED | BWI_DBG_ATTACH,
3839 "%dth led, act %d, lowact %d\n", i,
3840 led->l_act, led->l_flags & BWI_LED_F_ACTLOW);
3841 }
3842 callout_init_mtx(&sc->sc_led_blink_ch, &sc->sc_mtx, 0);
3843 }
3844
3845 static __inline uint16_t
bwi_led_onoff(const struct bwi_led * led,uint16_t val,int on)3846 bwi_led_onoff(const struct bwi_led *led, uint16_t val, int on)
3847 {
3848 if (led->l_flags & BWI_LED_F_ACTLOW)
3849 on = !on;
3850 if (on)
3851 val |= led->l_mask;
3852 else
3853 val &= ~led->l_mask;
3854 return val;
3855 }
3856
3857 static void
bwi_led_newstate(struct bwi_softc * sc,enum ieee80211_state nstate)3858 bwi_led_newstate(struct bwi_softc *sc, enum ieee80211_state nstate)
3859 {
3860 struct ieee80211com *ic = &sc->sc_ic;
3861 uint16_t val;
3862 int i;
3863
3864 if (nstate == IEEE80211_S_INIT) {
3865 callout_stop(&sc->sc_led_blink_ch);
3866 sc->sc_led_blinking = 0;
3867 }
3868
3869 if ((sc->sc_flags & BWI_F_RUNNING) == 0)
3870 return;
3871
3872 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3873 for (i = 0; i < BWI_LED_MAX; ++i) {
3874 struct bwi_led *led = &sc->sc_leds[i];
3875 int on;
3876
3877 if (led->l_act == BWI_LED_ACT_UNKN ||
3878 led->l_act == BWI_LED_ACT_NULL)
3879 continue;
3880
3881 if ((led->l_flags & BWI_LED_F_BLINK) &&
3882 nstate != IEEE80211_S_INIT)
3883 continue;
3884
3885 switch (led->l_act) {
3886 case BWI_LED_ACT_ON: /* Always on */
3887 on = 1;
3888 break;
3889 case BWI_LED_ACT_OFF: /* Always off */
3890 case BWI_LED_ACT_5GHZ: /* TODO: 11A */
3891 on = 0;
3892 break;
3893 default:
3894 on = 1;
3895 switch (nstate) {
3896 case IEEE80211_S_INIT:
3897 on = 0;
3898 break;
3899 case IEEE80211_S_RUN:
3900 if (led->l_act == BWI_LED_ACT_11G &&
3901 ic->ic_curmode != IEEE80211_MODE_11G)
3902 on = 0;
3903 break;
3904 default:
3905 if (led->l_act == BWI_LED_ACT_ASSOC)
3906 on = 0;
3907 break;
3908 }
3909 break;
3910 }
3911
3912 val = bwi_led_onoff(led, val, on);
3913 }
3914 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3915 }
3916 static void
bwi_led_event(struct bwi_softc * sc,int event)3917 bwi_led_event(struct bwi_softc *sc, int event)
3918 {
3919 struct bwi_led *led = sc->sc_blink_led;
3920 int rate;
3921
3922 if (event == BWI_LED_EVENT_POLL) {
3923 if ((led->l_flags & BWI_LED_F_POLLABLE) == 0)
3924 return;
3925 if (ticks - sc->sc_led_ticks < sc->sc_led_idle)
3926 return;
3927 }
3928
3929 sc->sc_led_ticks = ticks;
3930 if (sc->sc_led_blinking)
3931 return;
3932
3933 switch (event) {
3934 case BWI_LED_EVENT_RX:
3935 rate = sc->sc_rx_rate;
3936 break;
3937 case BWI_LED_EVENT_TX:
3938 rate = sc->sc_tx_rate;
3939 break;
3940 case BWI_LED_EVENT_POLL:
3941 rate = 0;
3942 break;
3943 default:
3944 panic("unknown LED event %d\n", event);
3945 break;
3946 }
3947 bwi_led_blink_start(sc, bwi_led_duration[rate].on_dur,
3948 bwi_led_duration[rate].off_dur);
3949 }
3950
3951 static void
bwi_led_blink_start(struct bwi_softc * sc,int on_dur,int off_dur)3952 bwi_led_blink_start(struct bwi_softc *sc, int on_dur, int off_dur)
3953 {
3954 struct bwi_led *led = sc->sc_blink_led;
3955 uint16_t val;
3956
3957 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3958 val = bwi_led_onoff(led, val, 1);
3959 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3960
3961 if (led->l_flags & BWI_LED_F_SLOW) {
3962 BWI_LED_SLOWDOWN(on_dur);
3963 BWI_LED_SLOWDOWN(off_dur);
3964 }
3965
3966 sc->sc_led_blinking = 1;
3967 sc->sc_led_blink_offdur = off_dur;
3968
3969 callout_reset(&sc->sc_led_blink_ch, on_dur, bwi_led_blink_next, sc);
3970 }
3971
3972 static void
bwi_led_blink_next(void * xsc)3973 bwi_led_blink_next(void *xsc)
3974 {
3975 struct bwi_softc *sc = xsc;
3976 uint16_t val;
3977
3978 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3979 val = bwi_led_onoff(sc->sc_blink_led, val, 0);
3980 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3981
3982 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur,
3983 bwi_led_blink_end, sc);
3984 }
3985
3986 static void
bwi_led_blink_end(void * xsc)3987 bwi_led_blink_end(void *xsc)
3988 {
3989 struct bwi_softc *sc = xsc;
3990 sc->sc_led_blinking = 0;
3991 }
3992
3993 static void
bwi_restart(void * xsc,int pending)3994 bwi_restart(void *xsc, int pending)
3995 {
3996 struct bwi_softc *sc = xsc;
3997
3998 device_printf(sc->sc_dev, "%s begin, help!\n", __func__);
3999 BWI_LOCK(sc);
4000 bwi_init_statechg(sc, 0);
4001 #if 0
4002 bwi_start_locked(sc);
4003 #endif
4004 BWI_UNLOCK(sc);
4005 }
4006