1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2008-2010 Atheros Communications Inc.
5 * Copyright (c) 2011 Adrian Chadd, Xenion Pty Ltd.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28 #include "opt_ah.h"
29
30 #include "ah.h"
31 #include "ah_desc.h"
32 #include "ah_internal.h"
33 #include "ah_eeprom_v4k.h"
34
35 #include "ar9002/ar9280.h"
36 #include "ar9002/ar9285.h"
37 #include "ar5416/ar5416reg.h"
38 #include "ar5416/ar5416phy.h"
39 #include "ar9002/ar9285phy.h"
40 #include "ar9002/ar9285_phy.h"
41
42 #include "ar9002/ar9285_diversity.h"
43
44 /*
45 * Set the antenna switch to control RX antenna diversity.
46 *
47 * If a fixed configuration is used, the LNA and div bias
48 * settings are fixed and the antenna diversity scanning routine
49 * is disabled.
50 *
51 * If a variable configuration is used, a default is programmed
52 * in and sampling commences per RXed packet.
53 *
54 * Since this is called from ar9285SetBoardValues() to setup
55 * diversity, it means that after a reset or scan, any current
56 * software diversity combining settings will be lost and won't
57 * re-appear until after the first successful sample run.
58 * Please keep this in mind if you're seeing weird performance
59 * that happens to relate to scan/diversity timing.
60 */
61 HAL_BOOL
ar9285SetAntennaSwitch(struct ath_hal * ah,HAL_ANT_SETTING settings)62 ar9285SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings)
63 {
64 int regVal;
65 const HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom;
66 const MODAL_EEP4K_HEADER *pModal = &ee->ee_base.modalHeader;
67 uint8_t ant_div_control1, ant_div_control2;
68
69 if (pModal->version < 3) {
70 HALDEBUG(ah, HAL_DEBUG_DIVERSITY, "%s: not supported\n",
71 __func__);
72 return AH_FALSE; /* Can't do diversity */
73 }
74
75 /* Store settings */
76 AH5212(ah)->ah_antControl = settings;
77 AH5212(ah)->ah_diversity = (settings == HAL_ANT_VARIABLE);
78
79 /* XXX don't fiddle if the PHY is in sleep mode or ! chan */
80
81 /* Begin setting the relevant registers */
82
83 ant_div_control1 = pModal->antdiv_ctl1;
84 ant_div_control2 = pModal->antdiv_ctl2;
85
86 regVal = OS_REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
87 regVal &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL));
88
89 /* enable antenna diversity only if diversityControl == HAL_ANT_VARIABLE */
90 if (settings == HAL_ANT_VARIABLE)
91 regVal |= SM(ant_div_control1, AR_PHY_9285_ANT_DIV_CTL);
92
93 if (settings == HAL_ANT_VARIABLE) {
94 HALDEBUG(ah, HAL_DEBUG_DIVERSITY, "%s: HAL_ANT_VARIABLE\n",
95 __func__);
96 regVal |= SM(ant_div_control2, AR_PHY_9285_ANT_DIV_ALT_LNACONF);
97 regVal |= SM((ant_div_control2 >> 2), AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
98 regVal |= SM((ant_div_control1 >> 1), AR_PHY_9285_ANT_DIV_ALT_GAINTB);
99 regVal |= SM((ant_div_control1 >> 2), AR_PHY_9285_ANT_DIV_MAIN_GAINTB);
100 } else {
101 if (settings == HAL_ANT_FIXED_A) {
102 /* Diversity disabled, RX = LNA1 */
103 HALDEBUG(ah, HAL_DEBUG_DIVERSITY, "%s: HAL_ANT_FIXED_A\n",
104 __func__);
105 regVal |= SM(HAL_ANT_DIV_COMB_LNA2, AR_PHY_9285_ANT_DIV_ALT_LNACONF);
106 regVal |= SM(HAL_ANT_DIV_COMB_LNA1, AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
107 regVal |= SM(AR_PHY_9285_ANT_DIV_GAINTB_0, AR_PHY_9285_ANT_DIV_ALT_GAINTB);
108 regVal |= SM(AR_PHY_9285_ANT_DIV_GAINTB_1, AR_PHY_9285_ANT_DIV_MAIN_GAINTB);
109 }
110 else if (settings == HAL_ANT_FIXED_B) {
111 /* Diversity disabled, RX = LNA2 */
112 HALDEBUG(ah, HAL_DEBUG_DIVERSITY, "%s: HAL_ANT_FIXED_B\n",
113 __func__);
114 regVal |= SM(HAL_ANT_DIV_COMB_LNA1, AR_PHY_9285_ANT_DIV_ALT_LNACONF);
115 regVal |= SM(HAL_ANT_DIV_COMB_LNA2, AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
116 regVal |= SM(AR_PHY_9285_ANT_DIV_GAINTB_1, AR_PHY_9285_ANT_DIV_ALT_GAINTB);
117 regVal |= SM(AR_PHY_9285_ANT_DIV_GAINTB_0, AR_PHY_9285_ANT_DIV_MAIN_GAINTB);
118 }
119 }
120
121 OS_REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal);
122 regVal = OS_REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
123 regVal = OS_REG_READ(ah, AR_PHY_CCK_DETECT);
124 regVal &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
125 if (settings == HAL_ANT_VARIABLE)
126 regVal |= SM((ant_div_control1 >> 3), AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
127
128 OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal);
129 regVal = OS_REG_READ(ah, AR_PHY_CCK_DETECT);
130
131 /*
132 * If Diversity combining is available and the diversity setting
133 * is to allow variable diversity, enable it by default.
134 *
135 * This will be eventually overridden by the software antenna
136 * diversity logic.
137 *
138 * Note that yes, this following section overrides the above
139 * settings for the LNA configuration and fast-bias.
140 */
141 if (ar9285_check_div_comb(ah) && AH5212(ah)->ah_diversity == AH_TRUE) {
142 // If support DivComb, set MAIN to LNA1 and ALT to LNA2 at the first beginning
143 HALDEBUG(ah, HAL_DEBUG_DIVERSITY,
144 "%s: Enable initial settings for combined diversity\n",
145 __func__);
146 regVal = OS_REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
147 regVal &= (~(AR_PHY_9285_ANT_DIV_MAIN_LNACONF | AR_PHY_9285_ANT_DIV_ALT_LNACONF));
148 regVal |= (HAL_ANT_DIV_COMB_LNA1 << AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S);
149 regVal |= (HAL_ANT_DIV_COMB_LNA2 << AR_PHY_9285_ANT_DIV_ALT_LNACONF_S);
150 regVal &= (~(AR_PHY_9285_FAST_DIV_BIAS));
151 regVal |= (0 << AR_PHY_9285_FAST_DIV_BIAS_S);
152 OS_REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal);
153 }
154
155 return AH_TRUE;
156 }
157