1 /*-
2 * SPDX-License-Identifier: ISC
3 *
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19 #include "opt_ah.h"
20
21 #include "ah.h"
22 #include "ah_internal.h"
23 #include "ah_devid.h"
24
25 #include "ah_eeprom_v14.h"
26
27 #include "ar5416/ar5416.h"
28 #include "ar5416/ar5416reg.h"
29 #include "ar5416/ar5416phy.h"
30
31 #include "ar5416/ar5416.ini"
32
33 static void ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore,
34 HAL_BOOL power_off);
35 static void ar5416DisablePCIE(struct ath_hal *ah);
36 static void ar5416WriteIni(struct ath_hal *ah,
37 const struct ieee80211_channel *chan);
38 static void ar5416SpurMitigate(struct ath_hal *ah,
39 const struct ieee80211_channel *chan);
40
41 static void
ar5416AniSetup(struct ath_hal * ah)42 ar5416AniSetup(struct ath_hal *ah)
43 {
44 static const struct ar5212AniParams aniparams = {
45 .maxNoiseImmunityLevel = 4, /* levels 0..4 */
46 .totalSizeDesired = { -55, -55, -55, -55, -62 },
47 .coarseHigh = { -14, -14, -14, -14, -12 },
48 .coarseLow = { -64, -64, -64, -64, -70 },
49 .firpwr = { -78, -78, -78, -78, -80 },
50 .maxSpurImmunityLevel = 7,
51 .cycPwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 },
52 .maxFirstepLevel = 2, /* levels 0..2 */
53 .firstep = { 0, 4, 8 },
54 .ofdmTrigHigh = 500,
55 .ofdmTrigLow = 200,
56 .cckTrigHigh = 200,
57 .cckTrigLow = 100,
58 .rssiThrHigh = 40,
59 .rssiThrLow = 7,
60 .period = 100,
61 };
62 /* NB: disable ANI noise immmunity for reliable RIFS rx */
63 AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL);
64 ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE);
65 }
66
67 /*
68 * AR5416 doesn't do OLC or temperature compensation.
69 */
70 static void
ar5416olcInit(struct ath_hal * ah)71 ar5416olcInit(struct ath_hal *ah)
72 {
73 }
74
75 static void
ar5416olcTempCompensation(struct ath_hal * ah)76 ar5416olcTempCompensation(struct ath_hal *ah)
77 {
78 }
79
80 /*
81 * Attach for an AR5416 part.
82 */
83 void
ar5416InitState(struct ath_hal_5416 * ahp5416,uint16_t devid,HAL_SOFTC sc,HAL_BUS_TAG st,HAL_BUS_HANDLE sh,HAL_STATUS * status)84 ar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc,
85 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status)
86 {
87 struct ath_hal_5212 *ahp;
88 struct ath_hal *ah;
89
90 ahp = &ahp5416->ah_5212;
91 ar5212InitState(ahp, devid, sc, st, sh, status);
92 ah = &ahp->ah_priv.h;
93
94 /* override 5212 methods for our needs */
95 ah->ah_magic = AR5416_MAGIC;
96 ah->ah_getRateTable = ar5416GetRateTable;
97 ah->ah_detach = ar5416Detach;
98
99 /* Reset functions */
100 ah->ah_reset = ar5416Reset;
101 ah->ah_phyDisable = ar5416PhyDisable;
102 ah->ah_disable = ar5416Disable;
103 ah->ah_configPCIE = ar5416ConfigPCIE;
104 ah->ah_disablePCIE = ar5416DisablePCIE;
105 ah->ah_perCalibration = ar5416PerCalibration;
106 ah->ah_perCalibrationN = ar5416PerCalibrationN;
107 ah->ah_resetCalValid = ar5416ResetCalValid;
108 ah->ah_setTxPowerLimit = ar5416SetTxPowerLimit;
109 ah->ah_setTxPower = ar5416SetTransmitPower;
110 ah->ah_setBoardValues = ar5416SetBoardValues;
111
112 /* Transmit functions */
113 ah->ah_stopTxDma = ar5416StopTxDma;
114 ah->ah_setupTxDesc = ar5416SetupTxDesc;
115 ah->ah_setupXTxDesc = ar5416SetupXTxDesc;
116 ah->ah_fillTxDesc = ar5416FillTxDesc;
117 ah->ah_procTxDesc = ar5416ProcTxDesc;
118 ah->ah_getTxCompletionRates = ar5416GetTxCompletionRates;
119 ah->ah_setupTxQueue = ar5416SetupTxQueue;
120 ah->ah_resetTxQueue = ar5416ResetTxQueue;
121
122 /* Receive Functions */
123 ah->ah_getRxFilter = ar5416GetRxFilter;
124 ah->ah_setRxFilter = ar5416SetRxFilter;
125 ah->ah_stopDmaReceive = ar5416StopDmaReceive;
126 ah->ah_startPcuReceive = ar5416StartPcuReceive;
127 ah->ah_stopPcuReceive = ar5416StopPcuReceive;
128 ah->ah_setupRxDesc = ar5416SetupRxDesc;
129 ah->ah_procRxDesc = ar5416ProcRxDesc;
130 ah->ah_rxMonitor = ar5416RxMonitor;
131 ah->ah_aniPoll = ar5416AniPoll;
132 ah->ah_procMibEvent = ar5416ProcessMibIntr;
133
134 /* Misc Functions */
135 ah->ah_getCapability = ar5416GetCapability;
136 ah->ah_setCapability = ar5416SetCapability;
137 ah->ah_getDiagState = ar5416GetDiagState;
138 ah->ah_setLedState = ar5416SetLedState;
139 ah->ah_gpioCfgOutput = ar5416GpioCfgOutput;
140 ah->ah_gpioCfgInput = ar5416GpioCfgInput;
141 ah->ah_gpioGet = ar5416GpioGet;
142 ah->ah_gpioSet = ar5416GpioSet;
143 ah->ah_gpioSetIntr = ar5416GpioSetIntr;
144 ah->ah_getTsf64 = ar5416GetTsf64;
145 ah->ah_setTsf64 = ar5416SetTsf64;
146 ah->ah_resetTsf = ar5416ResetTsf;
147 ah->ah_getRfGain = ar5416GetRfgain;
148 ah->ah_setAntennaSwitch = ar5416SetAntennaSwitch;
149 ah->ah_setDecompMask = ar5416SetDecompMask;
150 ah->ah_setCoverageClass = ar5416SetCoverageClass;
151 ah->ah_setQuiet = ar5416SetQuiet;
152 ah->ah_getMibCycleCounts = ar5416GetMibCycleCounts;
153 ah->ah_setChainMasks = ar5416SetChainMasks;
154
155 ah->ah_resetKeyCacheEntry = ar5416ResetKeyCacheEntry;
156 ah->ah_setKeyCacheEntry = ar5416SetKeyCacheEntry;
157
158 /* DFS Functions */
159 ah->ah_enableDfs = ar5416EnableDfs;
160 ah->ah_getDfsThresh = ar5416GetDfsThresh;
161 ah->ah_getDfsDefaultThresh = ar5416GetDfsDefaultThresh;
162 ah->ah_procRadarEvent = ar5416ProcessRadarEvent;
163 ah->ah_isFastClockEnabled = ar5416IsFastClockEnabled;
164
165 /* Spectral Scan Functions */
166 ah->ah_spectralConfigure = ar5416ConfigureSpectralScan;
167 ah->ah_spectralGetConfig = ar5416GetSpectralParams;
168 ah->ah_spectralStart = ar5416StartSpectralScan;
169 ah->ah_spectralStop = ar5416StopSpectralScan;
170 ah->ah_spectralIsEnabled = ar5416IsSpectralEnabled;
171 ah->ah_spectralIsActive = ar5416IsSpectralActive;
172
173 /* Power Management Functions */
174 ah->ah_setPowerMode = ar5416SetPowerMode;
175
176 /* Beacon Management Functions */
177 ah->ah_setBeaconTimers = ar5416SetBeaconTimers;
178 ah->ah_beaconInit = ar5416BeaconInit;
179 ah->ah_setStationBeaconTimers = ar5416SetStaBeaconTimers;
180 ah->ah_resetStationBeaconTimers = ar5416ResetStaBeaconTimers;
181 ah->ah_getNextTBTT = ar5416GetNextTBTT;
182
183 /* 802.11n Functions */
184 ah->ah_chainTxDesc = ar5416ChainTxDesc;
185 ah->ah_setupFirstTxDesc = ar5416SetupFirstTxDesc;
186 ah->ah_setupLastTxDesc = ar5416SetupLastTxDesc;
187 ah->ah_set11nRateScenario = ar5416Set11nRateScenario;
188 ah->ah_set11nAggrFirst = ar5416Set11nAggrFirst;
189 ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle;
190 ah->ah_set11nAggrLast = ar5416Set11nAggrLast;
191 ah->ah_clr11nAggr = ar5416Clr11nAggr;
192 ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration;
193 ah->ah_get11nExtBusy = ar5416Get11nExtBusy;
194 ah->ah_set11nMac2040 = ar5416Set11nMac2040;
195 ah->ah_get11nRxClear = ar5416Get11nRxClear;
196 ah->ah_set11nRxClear = ar5416Set11nRxClear;
197 ah->ah_set11nVirtMoreFrag = ar5416Set11nVirtualMoreFrag;
198
199 /* Interrupt functions */
200 ah->ah_isInterruptPending = ar5416IsInterruptPending;
201 ah->ah_getPendingInterrupts = ar5416GetPendingInterrupts;
202 ah->ah_setInterrupts = ar5416SetInterrupts;
203
204 /* Bluetooth Coexistence functions */
205 ah->ah_btCoexSetInfo = ar5416SetBTCoexInfo;
206 ah->ah_btCoexSetConfig = ar5416BTCoexConfig;
207 ah->ah_btCoexSetQcuThresh = ar5416BTCoexSetQcuThresh;
208 ah->ah_btCoexSetWeights = ar5416BTCoexSetWeights;
209 ah->ah_btCoexSetBmissThresh = ar5416BTCoexSetupBmissThresh;
210 ah->ah_btCoexSetParameter = ar5416BTCoexSetParameter;
211 ah->ah_btCoexDisable = ar5416BTCoexDisable;
212 ah->ah_btCoexEnable = ar5416BTCoexEnable;
213 AH5416(ah)->ah_btCoexSetDiversity = ar5416BTCoexAntennaDiversity;
214
215 ahp->ah_priv.ah_getWirelessModes= ar5416GetWirelessModes;
216 ahp->ah_priv.ah_eepromRead = ar5416EepromRead;
217 #ifdef AH_SUPPORT_WRITE_EEPROM
218 ahp->ah_priv.ah_eepromWrite = ar5416EepromWrite;
219 #endif
220 ahp->ah_priv.ah_getChipPowerLimits = ar5416GetChipPowerLimits;
221
222 /* Internal ops */
223 AH5416(ah)->ah_writeIni = ar5416WriteIni;
224 AH5416(ah)->ah_spurMitigate = ar5416SpurMitigate;
225
226 /* Internal baseband ops */
227 AH5416(ah)->ah_initPLL = ar5416InitPLL;
228
229 /* Internal calibration ops */
230 AH5416(ah)->ah_cal_initcal = ar5416InitCalHardware;
231
232 /* Internal TX power control related operations */
233 AH5416(ah)->ah_olcInit = ar5416olcInit;
234 AH5416(ah)->ah_olcTempCompensation = ar5416olcTempCompensation;
235 AH5416(ah)->ah_setPowerCalTable = ar5416SetPowerCalTable;
236
237 /*
238 * Start by setting all Owl devices to 2x2
239 */
240 AH5416(ah)->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK;
241 AH5416(ah)->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK;
242
243 /* Enable all ANI functions to begin with */
244 AH5416(ah)->ah_ani_function = 0xffffffff;
245
246 /* Set overridable ANI methods */
247 AH5212(ah)->ah_aniControl = ar5416AniControl;
248
249 /*
250 * Default FIFO Trigger levels
251 *
252 * These define how filled the TX FIFO needs to be before
253 * the baseband begins to be given some data.
254 *
255 * To be paranoid, we ensure that the TX trigger level always
256 * has at least enough space for two TX DMA to occur.
257 * The TX DMA size is currently hard-coded to AR_TXCFG_DMASZ_128B.
258 * That means we need to leave at least 256 bytes available in
259 * the TX DMA FIFO.
260 */
261 #define AR_FTRIG_512B 0x00000080 // 5 bits total
262 /*
263 * AR9285/AR9271 have half the size TX FIFO compared to
264 * other devices
265 */
266 if (AR_SREV_KITE(ah) || AR_SREV_9271(ah)) {
267 AH5212(ah)->ah_txTrigLev = (AR_FTRIG_256B >> AR_FTRIG_S);
268 AH5212(ah)->ah_maxTxTrigLev = ((2048 / 64) - 1);
269 } else {
270 AH5212(ah)->ah_txTrigLev = (AR_FTRIG_512B >> AR_FTRIG_S);
271 AH5212(ah)->ah_maxTxTrigLev = ((4096 / 64) - 1);
272 }
273 #undef AR_FTRIG_512B
274
275 /* And now leave some headspace - 256 bytes */
276 AH5212(ah)->ah_maxTxTrigLev -= 4;
277 }
278
279 uint32_t
ar5416GetRadioRev(struct ath_hal * ah)280 ar5416GetRadioRev(struct ath_hal *ah)
281 {
282 uint32_t val;
283 int i;
284
285 /* Read Radio Chip Rev Extract */
286 OS_REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
287 for (i = 0; i < 8; i++)
288 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
289 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
290 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
291 return ath_hal_reverseBits(val, 8);
292 }
293
294 /*
295 * Attach for an AR5416 part.
296 */
297 static struct ath_hal *
ar5416Attach(uint16_t devid,HAL_SOFTC sc,HAL_BUS_TAG st,HAL_BUS_HANDLE sh,uint16_t * eepromdata,HAL_OPS_CONFIG * ah_config,HAL_STATUS * status)298 ar5416Attach(uint16_t devid, HAL_SOFTC sc,
299 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,
300 HAL_OPS_CONFIG *ah_config, HAL_STATUS *status)
301 {
302 struct ath_hal_5416 *ahp5416;
303 struct ath_hal_5212 *ahp;
304 struct ath_hal *ah;
305 uint32_t val;
306 HAL_STATUS ecode;
307 HAL_BOOL rfStatus;
308
309 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
310 __func__, sc, (void*) st, (void*) sh);
311
312 /* NB: memory is returned zero'd */
313 ahp5416 = ath_hal_malloc(sizeof (struct ath_hal_5416) +
314 /* extra space for Owl 2.1/2.2 WAR */
315 sizeof(ar5416Addac)
316 );
317 if (ahp5416 == AH_NULL) {
318 HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
319 "%s: cannot allocate memory for state block\n", __func__);
320 *status = HAL_ENOMEM;
321 return AH_NULL;
322 }
323 ar5416InitState(ahp5416, devid, sc, st, sh, status);
324 ahp = &ahp5416->ah_5212;
325 ah = &ahp->ah_priv.h;
326
327 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
328 /* reset chip */
329 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", __func__);
330 ecode = HAL_EIO;
331 goto bad;
332 }
333
334 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
335 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", __func__);
336 ecode = HAL_EIO;
337 goto bad;
338 }
339 /* Read Revisions from Chips before taking out of reset */
340 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID;
341 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S;
342 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION;
343 AH_PRIVATE(ah)->ah_ispcie = (devid == AR5416_DEVID_PCIE);
344
345 /* setup common ini data; rf backends handle remainder */
346 HAL_INI_INIT(&ahp->ah_ini_modes, ar5416Modes, 6);
347 HAL_INI_INIT(&ahp->ah_ini_common, ar5416Common, 2);
348
349 HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar5416BB_RfGain, 3);
350 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar5416Bank0, 2);
351 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar5416Bank1, 2);
352 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar5416Bank2, 2);
353 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar5416Bank3, 3);
354 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar5416Bank6, 3);
355 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar5416Bank7, 2);
356 HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar5416Addac, 2);
357
358 if (! IS_5416V2_2(ah)) { /* Owl 2.1/2.0 */
359 ath_hal_printf(ah, "[ath] Enabling CLKDRV workaround for AR5416 < v2.2\n");
360 struct ini {
361 uint32_t *data; /* NB: !const */
362 int rows, cols;
363 };
364 /* override CLKDRV value */
365 OS_MEMCPY(&AH5416(ah)[1], ar5416Addac, sizeof(ar5416Addac));
366 AH5416(ah)->ah_ini_addac.data = (uint32_t *) &AH5416(ah)[1];
367 HAL_INI_VAL((struct ini *)&AH5416(ah)->ah_ini_addac, 31, 1) = 0;
368 }
369
370 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar5416PciePhy, 2);
371 ar5416AttachPCIE(ah);
372
373 ecode = ath_hal_v14EepromAttach(ah);
374 if (ecode != HAL_OK)
375 goto bad;
376
377 if (!ar5416ChipReset(ah, AH_NULL, HAL_RESET_NORMAL)) { /* reset chip */
378 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n",
379 __func__);
380 ecode = HAL_EIO;
381 goto bad;
382 }
383
384 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
385
386 if (!ar5212ChipTest(ah)) {
387 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
388 __func__);
389 ecode = HAL_ESELFTEST;
390 goto bad;
391 }
392
393 /*
394 * Set correct Baseband to analog shift
395 * setting to access analog chips.
396 */
397 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
398
399 /* Read Radio Chip Rev Extract */
400 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah);
401 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
402 case AR_RAD5122_SREV_MAJOR: /* Fowl: 5G/2x2 */
403 case AR_RAD2122_SREV_MAJOR: /* Fowl: 2+5G/2x2 */
404 case AR_RAD2133_SREV_MAJOR: /* Fowl: 2G/3x3 */
405 case AR_RAD5133_SREV_MAJOR: /* Fowl: 2+5G/3x3 */
406 break;
407 default:
408 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
409 /*
410 * When RF_Silen is used the analog chip is reset.
411 * So when the system boots with radio switch off
412 * the RF chip rev reads back as zero and we need
413 * to use the mac+phy revs to set the radio rev.
414 */
415 AH_PRIVATE(ah)->ah_analog5GhzRev =
416 AR_RAD5133_SREV_MAJOR;
417 break;
418 }
419 /* NB: silently accept anything in release code per Atheros */
420 #ifdef AH_DEBUG
421 HALDEBUG(ah, HAL_DEBUG_ANY,
422 "%s: 5G Radio Chip Rev 0x%02X is not supported by "
423 "this driver\n", __func__,
424 AH_PRIVATE(ah)->ah_analog5GhzRev);
425 ecode = HAL_ENOTSUPP;
426 goto bad;
427 #endif
428 }
429
430 /*
431 * Got everything we need now to setup the capabilities.
432 */
433 if (!ar5416FillCapabilityInfo(ah)) {
434 ecode = HAL_EEREAD;
435 goto bad;
436 }
437
438 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
439 if (ecode != HAL_OK) {
440 HALDEBUG(ah, HAL_DEBUG_ANY,
441 "%s: error getting mac address from EEPROM\n", __func__);
442 goto bad;
443 }
444 /* XXX How about the serial number ? */
445 /* Read Reg Domain */
446 AH_PRIVATE(ah)->ah_currentRD =
447 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);
448 AH_PRIVATE(ah)->ah_currentRDext =
449 ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL);
450
451 /*
452 * ah_miscMode is populated by ar5416FillCapabilityInfo()
453 * starting from griffin. Set here to make sure that
454 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is
455 * placed into hardware.
456 */
457 if (ahp->ah_miscMode != 0)
458 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);
459
460 rfStatus = ar2133RfAttach(ah, &ecode);
461 if (!rfStatus) {
462 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
463 __func__, ecode);
464 goto bad;
465 }
466
467 ar5416AniSetup(ah); /* Anti Noise Immunity */
468
469 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ;
470 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ;
471 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ;
472 AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ;
473 AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ;
474 AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ;
475
476 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
477
478 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
479
480 return ah;
481 bad:
482 if (ahp)
483 ar5416Detach((struct ath_hal *) ahp);
484 if (status)
485 *status = ecode;
486 return AH_NULL;
487 }
488
489 void
ar5416Detach(struct ath_hal * ah)490 ar5416Detach(struct ath_hal *ah)
491 {
492 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__);
493
494 HALASSERT(ah != AH_NULL);
495 HALASSERT(ah->ah_magic == AR5416_MAGIC);
496
497 /* Make sure that chip is awake before writing to it */
498 if (! ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
499 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
500 "%s: failed to wake up chip\n",
501 __func__);
502
503 ar5416AniDetach(ah);
504 ar5212RfDetach(ah);
505 ah->ah_disable(ah);
506 ar5416SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE);
507 ath_hal_eepromDetach(ah);
508 ath_hal_free(ah);
509 }
510
511 void
ar5416AttachPCIE(struct ath_hal * ah)512 ar5416AttachPCIE(struct ath_hal *ah)
513 {
514 if (AH_PRIVATE(ah)->ah_ispcie)
515 ath_hal_configPCIE(ah, AH_FALSE, AH_FALSE);
516 else
517 ath_hal_disablePCIE(ah);
518 }
519
520 static void
ar5416ConfigPCIE(struct ath_hal * ah,HAL_BOOL restore,HAL_BOOL power_off)521 ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off)
522 {
523
524 /* This is only applicable for AR5418 (AR5416 PCIe) */
525 if (! AH_PRIVATE(ah)->ah_ispcie)
526 return;
527
528 if (! restore) {
529 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
530 OS_DELAY(1000);
531 }
532
533 if (power_off) { /* Power-off */
534 /* clear bit 19 to disable L1 */
535 OS_REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
536 } else { /* Power-on */
537 /* Set default WAR values for Owl */
538 OS_REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
539
540 /* set bit 19 to allow forcing of pcie core into L1 state */
541 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
542 }
543 }
544
545 /*
546 * Disable PCIe PHY if PCIe isn't used.
547 */
548 static void
ar5416DisablePCIE(struct ath_hal * ah)549 ar5416DisablePCIE(struct ath_hal *ah)
550 {
551
552 /* PCIe? Don't */
553 if (AH_PRIVATE(ah)->ah_ispcie)
554 return;
555
556 /* .. Only applicable for AR5416v2 or later */
557 if (! (AR_SREV_OWL(ah) && AR_SREV_OWL_20_OR_LATER(ah)))
558 return;
559
560 OS_REG_WRITE_BUFFER_ENABLE(ah);
561
562 /*
563 * Disable the PCIe PHY.
564 */
565 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
566 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
567 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
568 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
569 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
570 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
571 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
572 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
573 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
574
575 /* Load the new settings */
576 OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
577
578 OS_REG_WRITE_BUFFER_FLUSH(ah);
579 OS_REG_WRITE_BUFFER_DISABLE(ah);
580 }
581
582 static void
ar5416WriteIni(struct ath_hal * ah,const struct ieee80211_channel * chan)583 ar5416WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
584 {
585 u_int modesIndex, freqIndex;
586 int regWrites = 0;
587
588 /* Setup the indices for the next set of register array writes */
589 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */
590 if (IEEE80211_IS_CHAN_2GHZ(chan)) {
591 freqIndex = 2;
592 if (IEEE80211_IS_CHAN_HT40(chan))
593 modesIndex = 3;
594 else if (IEEE80211_IS_CHAN_108G(chan))
595 modesIndex = 5;
596 else
597 modesIndex = 4;
598 } else {
599 freqIndex = 1;
600 if (IEEE80211_IS_CHAN_HT40(chan) ||
601 IEEE80211_IS_CHAN_TURBO(chan))
602 modesIndex = 2;
603 else
604 modesIndex = 1;
605 }
606
607 /* Set correct Baseband to analog shift setting to access analog chips. */
608 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
609
610 /*
611 * Write addac shifts
612 */
613 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
614
615 /* NB: only required for Sowl */
616 if (AR_SREV_SOWL(ah))
617 ar5416EepromSetAddac(ah, chan);
618
619 regWrites = ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_addac, 1,
620 regWrites);
621 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
622
623 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,
624 modesIndex, regWrites);
625 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,
626 1, regWrites);
627
628 /* XXX updated regWrites? */
629 AH5212(ah)->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites);
630 }
631
632 /*
633 * Convert to baseband spur frequency given input channel frequency
634 * and compute register settings below.
635 */
636
637 static void
ar5416SpurMitigate(struct ath_hal * ah,const struct ieee80211_channel * chan)638 ar5416SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan)
639 {
640 uint16_t freq = ath_hal_gethwchannel(ah, chan);
641 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
642 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 };
643 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
644 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 };
645 static const int inc[4] = { 0, 100, 0, 0 };
646
647 int bb_spur = AR_NO_SPUR;
648 int bin, cur_bin;
649 int spur_freq_sd;
650 int spur_delta_phase;
651 int denominator;
652 int upper, lower, cur_vit_mask;
653 int tmp, new;
654 int i;
655
656 int8_t mask_m[123];
657 int8_t mask_p[123];
658 int8_t mask_amt;
659 int tmp_mask;
660 int cur_bb_spur;
661 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan);
662
663 OS_MEMZERO(mask_m, sizeof(mask_m));
664 OS_MEMZERO(mask_p, sizeof(mask_p));
665
666 /*
667 * Need to verify range +/- 9.5 for static ht20, otherwise spur
668 * is out-of-band and can be ignored.
669 */
670 /* XXX ath9k changes */
671 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
672 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz);
673 if (AR_NO_SPUR == cur_bb_spur)
674 break;
675 cur_bb_spur = cur_bb_spur - (freq * 10);
676 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
677 bb_spur = cur_bb_spur;
678 break;
679 }
680 }
681 if (AR_NO_SPUR == bb_spur)
682 return;
683
684 bin = bb_spur * 32;
685
686 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0));
687 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
688 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
689 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
690 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
691
692 OS_REG_WRITE_BUFFER_ENABLE(ah);
693
694 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new);
695
696 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
697 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
698 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
699 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
700 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
701 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new);
702 /*
703 * Should offset bb_spur by +/- 10 MHz for dynamic 2040 MHz
704 * config, no offset for HT20.
705 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20,
706 * /80 for dyn2040.
707 */
708 spur_delta_phase = ((bb_spur * 524288) / 100) &
709 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
710 /*
711 * in 11A mode the denominator of spur_freq_sd should be 40 and
712 * it should be 44 in 11G
713 */
714 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 440 : 400;
715 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
716
717 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
718 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
719 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
720 OS_REG_WRITE(ah, AR_PHY_TIMING11, new);
721
722 /*
723 * ============================================
724 * pilot mask 1 [31:0] = +6..-26, no 0 bin
725 * pilot mask 2 [19:0] = +26..+7
726 *
727 * channel mask 1 [31:0] = +6..-26, no 0 bin
728 * channel mask 2 [19:0] = +26..+7
729 */
730 //cur_bin = -26;
731 cur_bin = -6000;
732 upper = bin + 100;
733 lower = bin - 100;
734
735 for (i = 0; i < 4; i++) {
736 int pilot_mask = 0;
737 int chan_mask = 0;
738 int bp = 0;
739 for (bp = 0; bp < 30; bp++) {
740 if ((cur_bin > lower) && (cur_bin < upper)) {
741 pilot_mask = pilot_mask | 0x1 << bp;
742 chan_mask = chan_mask | 0x1 << bp;
743 }
744 cur_bin += 100;
745 }
746 cur_bin += inc[i];
747 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
748 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask);
749 }
750
751 /* =================================================
752 * viterbi mask 1 based on channel magnitude
753 * four levels 0-3
754 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c)
755 * [1 2 2 1] for -9.6 or [1 2 1] for +16
756 * - enable_mask_ppm, all bins move with freq
757 *
758 * - mask_select, 8 bits for rates (reg 67,0x990c)
759 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c)
760 * choose which mask to use mask or mask2
761 */
762
763 /*
764 * viterbi mask 2 2nd set for per data rate puncturing
765 * four levels 0-3
766 * - mask_select, 8 bits for rates (reg 67)
767 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994)
768 * [1 2 2 1] for -9.6 or [1 2 1] for +16
769 */
770 cur_vit_mask = 6100;
771 upper = bin + 120;
772 lower = bin - 120;
773
774 for (i = 0; i < 123; i++) {
775 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
776 if ((abs(cur_vit_mask - bin)) < 75) {
777 mask_amt = 1;
778 } else {
779 mask_amt = 0;
780 }
781 if (cur_vit_mask < 0) {
782 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
783 } else {
784 mask_p[cur_vit_mask / 100] = mask_amt;
785 }
786 }
787 cur_vit_mask -= 100;
788 }
789
790 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
791 | (mask_m[48] << 26) | (mask_m[49] << 24)
792 | (mask_m[50] << 22) | (mask_m[51] << 20)
793 | (mask_m[52] << 18) | (mask_m[53] << 16)
794 | (mask_m[54] << 14) | (mask_m[55] << 12)
795 | (mask_m[56] << 10) | (mask_m[57] << 8)
796 | (mask_m[58] << 6) | (mask_m[59] << 4)
797 | (mask_m[60] << 2) | (mask_m[61] << 0);
798 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
799 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
800
801 tmp_mask = (mask_m[31] << 28)
802 | (mask_m[32] << 26) | (mask_m[33] << 24)
803 | (mask_m[34] << 22) | (mask_m[35] << 20)
804 | (mask_m[36] << 18) | (mask_m[37] << 16)
805 | (mask_m[48] << 14) | (mask_m[39] << 12)
806 | (mask_m[40] << 10) | (mask_m[41] << 8)
807 | (mask_m[42] << 6) | (mask_m[43] << 4)
808 | (mask_m[44] << 2) | (mask_m[45] << 0);
809 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
810 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
811
812 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
813 | (mask_m[18] << 26) | (mask_m[18] << 24)
814 | (mask_m[20] << 22) | (mask_m[20] << 20)
815 | (mask_m[22] << 18) | (mask_m[22] << 16)
816 | (mask_m[24] << 14) | (mask_m[24] << 12)
817 | (mask_m[25] << 10) | (mask_m[26] << 8)
818 | (mask_m[27] << 6) | (mask_m[28] << 4)
819 | (mask_m[29] << 2) | (mask_m[30] << 0);
820 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
821 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
822
823 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28)
824 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24)
825 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20)
826 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16)
827 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12)
828 | (mask_m[10] << 10) | (mask_m[11] << 8)
829 | (mask_m[12] << 6) | (mask_m[13] << 4)
830 | (mask_m[14] << 2) | (mask_m[15] << 0);
831 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
832 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
833
834 tmp_mask = (mask_p[15] << 28)
835 | (mask_p[14] << 26) | (mask_p[13] << 24)
836 | (mask_p[12] << 22) | (mask_p[11] << 20)
837 | (mask_p[10] << 18) | (mask_p[ 9] << 16)
838 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12)
839 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8)
840 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4)
841 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0);
842 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
843 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
844
845 tmp_mask = (mask_p[30] << 28)
846 | (mask_p[29] << 26) | (mask_p[28] << 24)
847 | (mask_p[27] << 22) | (mask_p[26] << 20)
848 | (mask_p[25] << 18) | (mask_p[24] << 16)
849 | (mask_p[23] << 14) | (mask_p[22] << 12)
850 | (mask_p[21] << 10) | (mask_p[20] << 8)
851 | (mask_p[19] << 6) | (mask_p[18] << 4)
852 | (mask_p[17] << 2) | (mask_p[16] << 0);
853 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
854 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
855
856 tmp_mask = (mask_p[45] << 28)
857 | (mask_p[44] << 26) | (mask_p[43] << 24)
858 | (mask_p[42] << 22) | (mask_p[41] << 20)
859 | (mask_p[40] << 18) | (mask_p[39] << 16)
860 | (mask_p[38] << 14) | (mask_p[37] << 12)
861 | (mask_p[36] << 10) | (mask_p[35] << 8)
862 | (mask_p[34] << 6) | (mask_p[33] << 4)
863 | (mask_p[32] << 2) | (mask_p[31] << 0);
864 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
865 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
866
867 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
868 | (mask_p[59] << 26) | (mask_p[58] << 24)
869 | (mask_p[57] << 22) | (mask_p[56] << 20)
870 | (mask_p[55] << 18) | (mask_p[54] << 16)
871 | (mask_p[53] << 14) | (mask_p[52] << 12)
872 | (mask_p[51] << 10) | (mask_p[50] << 8)
873 | (mask_p[49] << 6) | (mask_p[48] << 4)
874 | (mask_p[47] << 2) | (mask_p[46] << 0);
875 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
876 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
877
878 OS_REG_WRITE_BUFFER_FLUSH(ah);
879 OS_REG_WRITE_BUFFER_DISABLE(ah);
880 }
881
882 /*
883 * Fill all software cached or static hardware state information.
884 * Return failure if capabilities are to come from EEPROM and
885 * cannot be read.
886 */
887 HAL_BOOL
ar5416FillCapabilityInfo(struct ath_hal * ah)888 ar5416FillCapabilityInfo(struct ath_hal *ah)
889 {
890 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
891 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps;
892 uint16_t val;
893
894 /* Construct wireless mode from EEPROM */
895 pCap->halWirelessModes = 0;
896 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) {
897 pCap->halWirelessModes |= HAL_MODE_11A
898 | HAL_MODE_11NA_HT20
899 | HAL_MODE_11NA_HT40PLUS
900 | HAL_MODE_11NA_HT40MINUS
901 ;
902 }
903 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE)) {
904 pCap->halWirelessModes |= HAL_MODE_11G
905 | HAL_MODE_11NG_HT20
906 | HAL_MODE_11NG_HT40PLUS
907 | HAL_MODE_11NG_HT40MINUS
908 ;
909 pCap->halWirelessModes |= HAL_MODE_11A
910 | HAL_MODE_11NA_HT20
911 | HAL_MODE_11NA_HT40PLUS
912 | HAL_MODE_11NA_HT40MINUS
913 ;
914 }
915
916 pCap->halLow2GhzChan = 2312;
917 pCap->halHigh2GhzChan = 2732;
918
919 pCap->halLow5GhzChan = 4915;
920 pCap->halHigh5GhzChan = 6100;
921
922 pCap->halCipherCkipSupport = AH_FALSE;
923 pCap->halCipherTkipSupport = AH_TRUE;
924 pCap->halCipherAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES);
925
926 pCap->halMicCkipSupport = AH_FALSE;
927 pCap->halMicTkipSupport = AH_TRUE;
928 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES);
929 /*
930 * Starting with Griffin TX+RX mic keys can be combined
931 * in one key cache slot.
932 */
933 pCap->halTkipMicTxRxKeySupport = AH_TRUE;
934 pCap->halChanSpreadSupport = AH_TRUE;
935 pCap->halSleepAfterBeaconBroken = AH_TRUE;
936
937 pCap->halCompressSupport = AH_FALSE;
938 pCap->halBurstSupport = AH_TRUE;
939 pCap->halFastFramesSupport = AH_TRUE;
940 pCap->halChapTuningSupport = AH_TRUE;
941 pCap->halTurboPrimeSupport = AH_TRUE;
942
943 pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G;
944
945 pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */
946 pCap->halNumMRRetries = 4; /* Hardware supports 4 MRR */
947 pCap->halNumTxMaps = 1; /* Single TX ptr per descr */
948 pCap->halVEOLSupport = AH_TRUE;
949 pCap->halBssIdMaskSupport = AH_TRUE;
950 pCap->halMcastKeySrchSupport = AH_TRUE; /* Works on AR5416 and later */
951 pCap->halTsfAddSupport = AH_TRUE;
952 pCap->hal4AddrAggrSupport = AH_FALSE; /* Broken in Owl */
953 pCap->halSpectralScanSupport = AH_FALSE; /* AR9280 and later */
954
955 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK)
956 pCap->halTotalQueues = val;
957 else
958 pCap->halTotalQueues = HAL_NUM_TX_QUEUES;
959
960 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK)
961 pCap->halKeyCacheSize = val;
962 else
963 pCap->halKeyCacheSize = AR5416_KEYTABLE_SIZE;
964
965 /* XXX Which chips? */
966 pCap->halChanHalfRate = AH_TRUE;
967 pCap->halChanQuarterRate = AH_TRUE;
968
969 pCap->halTxTstampPrecision = 32;
970 pCap->halRxTstampPrecision = 32;
971 pCap->halHwPhyCounterSupport = AH_TRUE;
972 pCap->halIntrMask = HAL_INT_COMMON
973 | HAL_INT_RX
974 | HAL_INT_TX
975 | HAL_INT_FATAL
976 | HAL_INT_BNR
977 | HAL_INT_BMISC
978 | HAL_INT_DTIMSYNC
979 | HAL_INT_TSFOOR
980 | HAL_INT_CST
981 | HAL_INT_GTT
982 ;
983
984 pCap->halFastCCSupport = AH_TRUE;
985 pCap->halNumGpioPins = 14;
986 pCap->halWowSupport = AH_FALSE;
987 pCap->halWowMatchPatternExact = AH_FALSE;
988 pCap->halBtCoexSupport = AH_FALSE; /* XXX need support */
989 pCap->halAutoSleepSupport = AH_FALSE;
990 pCap->hal4kbSplitTransSupport = AH_TRUE;
991 /* Disable this so Block-ACK works correctly */
992 pCap->halHasRxSelfLinkedTail = AH_FALSE;
993 #if 0 /* XXX not yet */
994 pCap->halNumAntCfg2GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_2GHZ);
995 pCap->halNumAntCfg5GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_5GHZ);
996 #endif
997 pCap->halHTSupport = AH_TRUE;
998 pCap->halTxChainMask = ath_hal_eepromGet(ah, AR_EEP_TXMASK, AH_NULL);
999 /* XXX CB71 uses GPIO 0 to indicate 3 rx chains */
1000 pCap->halRxChainMask = ath_hal_eepromGet(ah, AR_EEP_RXMASK, AH_NULL);
1001 /* AR5416 may have 3 antennas but is a 2x2 stream device */
1002 pCap->halTxStreams = 2;
1003 pCap->halRxStreams = 2;
1004
1005 /*
1006 * If the TX or RX chainmask has less than 2 chains active,
1007 * mark it as a 1-stream device for the relevant stream.
1008 */
1009 if (owl_get_ntxchains(pCap->halTxChainMask) == 1)
1010 pCap->halTxStreams = 1;
1011 /* XXX Eww */
1012 if (owl_get_ntxchains(pCap->halRxChainMask) == 1)
1013 pCap->halRxStreams = 1;
1014 pCap->halRtsAggrLimit = 8*1024; /* Owl 2.0 limit */
1015 pCap->halMbssidAggrSupport = AH_FALSE; /* Broken on Owl */
1016 pCap->halForcePpmSupport = AH_TRUE;
1017 pCap->halEnhancedPmSupport = AH_TRUE;
1018 pCap->halBssidMatchSupport = AH_TRUE;
1019 pCap->halGTTSupport = AH_TRUE;
1020 pCap->halCSTSupport = AH_TRUE;
1021 pCap->halEnhancedDfsSupport = AH_FALSE;
1022 /*
1023 * BB Read WAR: this is only for AR5008/AR9001 NICs
1024 * It is also set individually in the AR91xx attach functions.
1025 */
1026 if (AR_SREV_OWL(ah))
1027 pCap->halHasBBReadWar = AH_TRUE;
1028
1029 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) &&
1030 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) {
1031 /* NB: enabled by default */
1032 ahpriv->ah_rfkillEnabled = AH_TRUE;
1033 pCap->halRfSilentSupport = AH_TRUE;
1034 }
1035
1036 /*
1037 * The MAC will mark frames as RXed if there's a descriptor
1038 * to write them to. So if it hits a self-linked final descriptor,
1039 * it'll keep ACKing frames even though they're being silently
1040 * dropped. Thus, this particular feature of the driver can't
1041 * be used for 802.11n devices.
1042 */
1043 ahpriv->ah_rxornIsFatal = AH_FALSE;
1044
1045 /*
1046 * If it's a PCI NIC, ask the HAL OS layer to serialise
1047 * register access, or SMP machines may cause the hardware
1048 * to hang. This is applicable to AR5416 and AR9220; I'm not
1049 * sure about AR9160 or AR9227.
1050 */
1051 if (! AH_PRIVATE(ah)->ah_ispcie)
1052 pCap->halSerialiseRegWar = 1;
1053
1054 /*
1055 * AR5416 and later NICs support MYBEACON filtering.
1056 */
1057 pCap->halRxDoMyBeacon = AH_TRUE;
1058
1059 return AH_TRUE;
1060 }
1061
1062 static const char*
ar5416Probe(uint16_t vendorid,uint16_t devid)1063 ar5416Probe(uint16_t vendorid, uint16_t devid)
1064 {
1065 if (vendorid == ATHEROS_VENDOR_ID) {
1066 if (devid == AR5416_DEVID_PCI)
1067 return "Atheros 5416";
1068 if (devid == AR5416_DEVID_PCIE)
1069 return "Atheros 5418";
1070 }
1071 return AH_NULL;
1072 }
1073 AH_CHIP(AR5416, ar5416Probe, ar5416Attach);
1074