1 /*-
2 * SPDX-License-Identifier: ISC
3 *
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19 #include "opt_ah.h"
20
21 #include "ah.h"
22 #include "ah_internal.h"
23 #include "ah_desc.h"
24
25 #include "ar5212/ar5212.h"
26 #include "ar5212/ar5212reg.h"
27 #include "ar5212/ar5212desc.h"
28
29 /*
30 * Get the RXDP.
31 */
32 uint32_t
ar5212GetRxDP(struct ath_hal * ath,HAL_RX_QUEUE qtype)33 ar5212GetRxDP(struct ath_hal *ath, HAL_RX_QUEUE qtype)
34 {
35
36 HALASSERT(qtype == HAL_RX_QUEUE_HP);
37 return OS_REG_READ(ath, AR_RXDP);
38 }
39
40 /*
41 * Set the RxDP.
42 */
43 void
ar5212SetRxDP(struct ath_hal * ah,uint32_t rxdp,HAL_RX_QUEUE qtype)44 ar5212SetRxDP(struct ath_hal *ah, uint32_t rxdp, HAL_RX_QUEUE qtype)
45 {
46
47 HALASSERT(qtype == HAL_RX_QUEUE_HP);
48 OS_REG_WRITE(ah, AR_RXDP, rxdp);
49 HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp);
50 }
51
52 /*
53 * Set Receive Enable bits.
54 */
55 void
ar5212EnableReceive(struct ath_hal * ah)56 ar5212EnableReceive(struct ath_hal *ah)
57 {
58 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);
59 }
60
61 /*
62 * Stop Receive at the DMA engine
63 */
64 HAL_BOOL
ar5212StopDmaReceive(struct ath_hal * ah)65 ar5212StopDmaReceive(struct ath_hal *ah)
66 {
67 OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_DMA_STOP);
68 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
69 if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) {
70 OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_DMA_STOP_ERR);
71 #ifdef AH_DEBUG
72 ath_hal_printf(ah, "%s: dma failed to stop in 10ms\n"
73 "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n",
74 __func__,
75 OS_REG_READ(ah, AR_CR),
76 OS_REG_READ(ah, AR_DIAG_SW));
77 #endif
78 return AH_FALSE;
79 } else {
80 return AH_TRUE;
81 }
82 }
83
84 /*
85 * Start Transmit at the PCU engine (unpause receive)
86 */
87 void
ar5212StartPcuReceive(struct ath_hal * ah,HAL_BOOL is_scanning)88 ar5212StartPcuReceive(struct ath_hal *ah, HAL_BOOL is_scanning)
89 {
90 struct ath_hal_private *ahp = AH_PRIVATE(ah);
91
92 OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_PCU_START);
93 OS_REG_WRITE(ah, AR_DIAG_SW,
94 OS_REG_READ(ah, AR_DIAG_SW) &~ AR_DIAG_RX_DIS);
95 ar5212EnableMibCounters(ah);
96 /* NB: restore current settings if we're not scanning */
97 ar5212AniReset(ah, ahp->ah_curchan, ahp->ah_opmode, !is_scanning);
98 }
99
100 /*
101 * Stop Transmit at the PCU engine (pause receive)
102 */
103 void
ar5212StopPcuReceive(struct ath_hal * ah)104 ar5212StopPcuReceive(struct ath_hal *ah)
105 {
106 OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_PCU_STOP);
107 OS_REG_WRITE(ah, AR_DIAG_SW,
108 OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_RX_DIS);
109 ar5212DisableMibCounters(ah);
110 }
111
112 /*
113 * Set multicast filter 0 (lower 32-bits)
114 * filter 1 (upper 32-bits)
115 */
116 void
ar5212SetMulticastFilter(struct ath_hal * ah,uint32_t filter0,uint32_t filter1)117 ar5212SetMulticastFilter(struct ath_hal *ah, uint32_t filter0, uint32_t filter1)
118 {
119 OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0);
120 OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1);
121 }
122
123 /*
124 * Clear multicast filter by index
125 */
126 HAL_BOOL
ar5212ClrMulticastFilterIndex(struct ath_hal * ah,uint32_t ix)127 ar5212ClrMulticastFilterIndex(struct ath_hal *ah, uint32_t ix)
128 {
129 uint32_t val;
130
131 if (ix >= 64)
132 return AH_FALSE;
133 if (ix >= 32) {
134 val = OS_REG_READ(ah, AR_MCAST_FIL1);
135 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32))));
136 } else {
137 val = OS_REG_READ(ah, AR_MCAST_FIL0);
138 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix)));
139 }
140 return AH_TRUE;
141 }
142
143 /*
144 * Set multicast filter by index
145 */
146 HAL_BOOL
ar5212SetMulticastFilterIndex(struct ath_hal * ah,uint32_t ix)147 ar5212SetMulticastFilterIndex(struct ath_hal *ah, uint32_t ix)
148 {
149 uint32_t val;
150
151 if (ix >= 64)
152 return AH_FALSE;
153 if (ix >= 32) {
154 val = OS_REG_READ(ah, AR_MCAST_FIL1);
155 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32))));
156 } else {
157 val = OS_REG_READ(ah, AR_MCAST_FIL0);
158 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val | (1<<ix)));
159 }
160 return AH_TRUE;
161 }
162
163 /*
164 * Get the receive filter.
165 */
166 uint32_t
ar5212GetRxFilter(struct ath_hal * ah)167 ar5212GetRxFilter(struct ath_hal *ah)
168 {
169 uint32_t bits = OS_REG_READ(ah, AR_RX_FILTER);
170 uint32_t phybits = OS_REG_READ(ah, AR_PHY_ERR);
171 if (phybits & AR_PHY_ERR_RADAR)
172 bits |= HAL_RX_FILTER_PHYRADAR;
173 if (phybits & (AR_PHY_ERR_OFDM_TIMING|AR_PHY_ERR_CCK_TIMING))
174 bits |= HAL_RX_FILTER_PHYERR;
175 if (AH_PRIVATE(ah)->ah_caps.halBssidMatchSupport &&
176 (AH5212(ah)->ah_miscMode & AR_MISC_MODE_BSSID_MATCH_FORCE))
177 bits |= HAL_RX_FILTER_BSSID;
178 return bits;
179 }
180
181 /*
182 * Set the receive filter.
183 */
184 void
ar5212SetRxFilter(struct ath_hal * ah,uint32_t bits)185 ar5212SetRxFilter(struct ath_hal *ah, uint32_t bits)
186 {
187 struct ath_hal_5212 *ahp = AH5212(ah);
188 uint32_t phybits;
189
190 OS_REG_WRITE(ah, AR_RX_FILTER,
191 bits &~ (HAL_RX_FILTER_PHYRADAR|HAL_RX_FILTER_PHYERR|
192 HAL_RX_FILTER_BSSID));
193 phybits = 0;
194 if (bits & HAL_RX_FILTER_PHYRADAR)
195 phybits |= AR_PHY_ERR_RADAR;
196 if (bits & HAL_RX_FILTER_PHYERR)
197 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
198 OS_REG_WRITE(ah, AR_PHY_ERR, phybits);
199 if (phybits) {
200 OS_REG_WRITE(ah, AR_RXCFG,
201 OS_REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
202 } else {
203 OS_REG_WRITE(ah, AR_RXCFG,
204 OS_REG_READ(ah, AR_RXCFG) &~ AR_RXCFG_ZLFDMA);
205 }
206 if (AH_PRIVATE(ah)->ah_caps.halBssidMatchSupport) {
207 if (bits & HAL_RX_FILTER_BSSID)
208 ahp->ah_miscMode |= AR_MISC_MODE_BSSID_MATCH_FORCE;
209 else
210 ahp->ah_miscMode &= ~AR_MISC_MODE_BSSID_MATCH_FORCE;
211 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);
212 }
213 }
214
215 /*
216 * Initialize RX descriptor, by clearing the status and setting
217 * the size (and any other flags).
218 */
219 HAL_BOOL
ar5212SetupRxDesc(struct ath_hal * ah,struct ath_desc * ds,uint32_t size,u_int flags)220 ar5212SetupRxDesc(struct ath_hal *ah, struct ath_desc *ds,
221 uint32_t size, u_int flags)
222 {
223 struct ar5212_desc *ads = AR5212DESC(ds);
224
225 HALASSERT((size &~ AR_BufLen) == 0);
226
227 ads->ds_ctl0 = 0;
228 ads->ds_ctl1 = size & AR_BufLen;
229
230 if (flags & HAL_RXDESC_INTREQ)
231 ads->ds_ctl1 |= AR_RxInterReq;
232 ads->ds_rxstatus0 = ads->ds_rxstatus1 = 0;
233
234 return AH_TRUE;
235 }
236
237 /*
238 * Process an RX descriptor, and return the status to the caller.
239 * Copy some hardware specific items into the software portion
240 * of the descriptor.
241 *
242 * NB: the caller is responsible for validating the memory contents
243 * of the descriptor (e.g. flushing any cached copy).
244 */
245 HAL_STATUS
ar5212ProcRxDesc(struct ath_hal * ah,struct ath_desc * ds,uint32_t pa,struct ath_desc * nds,uint64_t tsf,struct ath_rx_status * rs)246 ar5212ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds,
247 uint32_t pa, struct ath_desc *nds, uint64_t tsf,
248 struct ath_rx_status *rs)
249 {
250 struct ar5212_desc *ads = AR5212DESC(ds);
251 struct ar5212_desc *ands = AR5212DESC(nds);
252
253 if ((ads->ds_rxstatus1 & AR_Done) == 0)
254 return HAL_EINPROGRESS;
255 /*
256 * Given the use of a self-linked tail be very sure that the hw is
257 * done with this descriptor; the hw may have done this descriptor
258 * once and picked it up again...make sure the hw has moved on.
259 */
260 if ((ands->ds_rxstatus1&AR_Done) == 0 && OS_REG_READ(ah, AR_RXDP) == pa)
261 return HAL_EINPROGRESS;
262
263 rs->rs_datalen = ads->ds_rxstatus0 & AR_DataLen;
264 rs->rs_tstamp = MS(ads->ds_rxstatus1, AR_RcvTimestamp);
265 rs->rs_status = 0;
266 rs->rs_rssi = MS(ads->ds_rxstatus0, AR_RcvSigStrength);
267 /* discard invalid h/w rssi data */
268 if (rs->rs_rssi == -128)
269 rs->rs_rssi = 0;
270 if (ads->ds_rxstatus1 & AR_KeyIdxValid)
271 rs->rs_keyix = MS(ads->ds_rxstatus1, AR_KeyIdx);
272 else
273 rs->rs_keyix = HAL_RXKEYIX_INVALID;
274 if (ads->ds_rxstatus1 & AR_KeyCacheMiss)
275 rs->rs_status |= HAL_RXERR_KEYMISS;
276 /* NB: caller expected to do rate table mapping */
277 rs->rs_rate = MS(ads->ds_rxstatus0, AR_RcvRate);
278 rs->rs_antenna = MS(ads->ds_rxstatus0, AR_RcvAntenna);
279 rs->rs_more = (ads->ds_rxstatus0 & AR_More) ? 1 : 0;
280
281 /*
282 * The AR5413 (at least) sometimes sets both AR_CRCErr and
283 * AR_PHYErr when reporting radar pulses. In this instance
284 * set HAL_RXERR_PHY as well as HAL_RXERR_CRC and
285 * let the driver layer figure out what to do.
286 *
287 * See PR kern/169362.
288 */
289 if ((ads->ds_rxstatus1 & AR_FrmRcvOK) == 0) {
290 /*
291 * These four bits should not be set together. The
292 * 5212 spec states a Michael error can only occur if
293 * DecryptCRCErr not set (and TKIP is used). Experience
294 * indicates however that you can also get Michael errors
295 * when a CRC error is detected, but these are specious.
296 * Consequently we filter them out here so we don't
297 * confuse and/or complicate drivers.
298 */
299 if (ads->ds_rxstatus1 & AR_PHYErr) {
300 u_int phyerr;
301
302 rs->rs_status |= HAL_RXERR_PHY;
303 phyerr = MS(ads->ds_rxstatus1, AR_PHYErrCode);
304 rs->rs_phyerr = phyerr;
305 if (!AH5212(ah)->ah_hasHwPhyCounters &&
306 phyerr != HAL_PHYERR_RADAR)
307 ar5212AniPhyErrReport(ah, rs);
308 }
309
310 if (ads->ds_rxstatus1 & AR_CRCErr)
311 rs->rs_status |= HAL_RXERR_CRC;
312 else if (ads->ds_rxstatus1 & AR_DecryptCRCErr)
313 rs->rs_status |= HAL_RXERR_DECRYPT;
314 else if (ads->ds_rxstatus1 & AR_MichaelErr)
315 rs->rs_status |= HAL_RXERR_MIC;
316 }
317 return HAL_OK;
318 }
319