1 /*
2 * Copyright 2006-2015, Haiku, Inc. All Rights Reserved.
3 * Distributed under the terms of the MIT License.
4 *
5 * Authors:
6 * Axel Dörfler, axeld@pinc-software.de
7 * Michael Lotz, mmlr@mlotz.ch
8 * Alexander von Gluck IV, kallisti5@unixzen.com
9 * Rudolf Cornelissen, ruud@highsand-juicylake.nl
10 */
11
12
13 #include "Ports.h"
14
15 #include <ddc.h>
16 #include <dp_raw.h>
17 #include <stdlib.h>
18 #include <string.h>
19 #include <Debug.h>
20 #include <KernelExport.h>
21
22 #include "accelerant.h"
23 #include "accelerant_protos.h"
24 #include "intel_extreme.h"
25
26 #include "FlexibleDisplayInterface.h"
27 #include "PanelFitter.h"
28 #include "TigerLakePLL.h"
29
30 #include <new>
31
32
33 #undef TRACE
34 #define TRACE_PORTS
35 #ifdef TRACE_PORTS
36 # define TRACE(x...) _sPrintf("intel_extreme: " x)
37 #else
38 # define TRACE(x...)
39 #endif
40
41 #define ERROR(x...) _sPrintf("intel_extreme: " x)
42 #define CALLED(x...) TRACE("CALLED %s\n", __PRETTY_FUNCTION__)
43
44
45 static bool
wait_for_set(addr_t address,uint32 mask,uint32 timeout)46 wait_for_set(addr_t address, uint32 mask, uint32 timeout)
47 {
48 int interval = 50;
49 uint32 i = 0;
50 for(i = 0; i <= timeout; i += interval) {
51 spin(interval);
52 if ((read32(address) & mask) != 0)
53 return true;
54 }
55 return false;
56 }
57
58
59 static bool
wait_for_clear(addr_t address,uint32 mask,uint32 timeout)60 wait_for_clear(addr_t address, uint32 mask, uint32 timeout)
61 {
62 int interval = 50;
63 uint32 i = 0;
64 for(i = 0; i <= timeout; i += interval) {
65 spin(interval);
66 if ((read32(address) & mask) == 0)
67 return true;
68 }
69 return false;
70 }
71
72
73 static uint32
wait_for_clear_status(addr_t address,uint32 mask,uint32 timeout)74 wait_for_clear_status(addr_t address, uint32 mask, uint32 timeout)
75 {
76 int interval = 50;
77 uint32 i = 0;
78 uint32 status = 0;
79 for(i = 0; i <= timeout; i += interval) {
80 spin(interval);
81 status = read32(address);
82 if ((status & mask) == 0)
83 return status;
84 }
85 return status;
86 }
87
88
Port(port_index index,const char * baseName)89 Port::Port(port_index index, const char* baseName)
90 :
91 fPipe(NULL),
92 fEDIDState(B_NO_INIT),
93 fPortIndex(index),
94 fPortName(NULL)
95 {
96 char portID[2];
97 portID[0] = 'A' + index - INTEL_PORT_A;
98 portID[1] = 0;
99
100 char buffer[32];
101 buffer[0] = 0;
102
103 strlcat(buffer, baseName, sizeof(buffer));
104 strlcat(buffer, " ", sizeof(buffer));
105 strlcat(buffer, portID, sizeof(buffer));
106 fPortName = strdup(buffer);
107 }
108
109
~Port()110 Port::~Port()
111 {
112 free(fPortName);
113 }
114
115
116 bool
HasEDID()117 Port::HasEDID()
118 {
119 if (fEDIDState == B_NO_INIT)
120 GetEDID(NULL);
121
122 return fEDIDState == B_OK;
123 }
124
125
126 status_t
SetPipe(Pipe * pipe)127 Port::SetPipe(Pipe* pipe)
128 {
129 CALLED();
130
131 if (pipe == NULL) {
132 ERROR("%s: Invalid pipe provided!\n", __func__);
133 return B_ERROR;
134 }
135
136 uint32 portRegister = _PortRegister();
137 if (portRegister == 0) {
138 ERROR("%s: Invalid PortRegister ((0x%" B_PRIx32 ") for %s\n", __func__,
139 portRegister, PortName());
140 return B_ERROR;
141 }
142
143 // TODO: UnAssignPipe? This likely needs reworked a little
144 if (fPipe != NULL) {
145 ERROR("%s: Can't reassign display pipe (yet)\n", __func__);
146 return B_ERROR;
147 }
148
149 switch (pipe->Index()) {
150 case INTEL_PIPE_B:
151 TRACE("%s: Assigning %s (0x%" B_PRIx32 ") to pipe B\n", __func__,
152 PortName(), portRegister);
153 break;
154 case INTEL_PIPE_C:
155 TRACE("%s: Assigning %s (0x%" B_PRIx32 ") to pipe C\n", __func__,
156 PortName(), portRegister);
157 break;
158 case INTEL_PIPE_D:
159 TRACE("%s: Assigning %s (0x%" B_PRIx32 ") to pipe D\n", __func__,
160 PortName(), portRegister);
161 break;
162 default:
163 TRACE("%s: Assigning %s (0x%" B_PRIx32 ") to pipe A\n", __func__,
164 PortName(), portRegister);
165 break;
166 }
167
168 uint32 portState = read32(portRegister);
169
170 // generation 6 gfx SandyBridge/SNB non-DP use the same 2 bits on all ports (eDP = 1 bit).
171 // generation 7 gfx IvyBridge/IVB non-DP use the same 2 bits on all ports (eDP = 2 bits).
172 // DP ports/all DDI ports: Pipe selections works differently, via own SetPipe() implementation.
173 if (gInfo->shared_info->pch_info == INTEL_PCH_CPT) {
174 portState &= ~PORT_TRANS_SEL_MASK;
175 switch (pipe->Index()) {
176 case INTEL_PIPE_B:
177 write32(portRegister, portState | PORT_TRANS_B_SEL_CPT);
178 break;
179 case INTEL_PIPE_C:
180 write32(portRegister, portState | PORT_TRANS_C_SEL_CPT);
181 break;
182 default:
183 write32(portRegister, portState | PORT_TRANS_A_SEL_CPT);
184 break;
185 }
186 } else {
187 // generation 3/4/5 gfx uses the same single bit on all ports
188 if (pipe->Index() == INTEL_PIPE_A)
189 write32(portRegister, portState & ~DISPLAY_MONITOR_PIPE_B);
190 else
191 write32(portRegister, portState | DISPLAY_MONITOR_PIPE_B);
192 }
193 fPipe = pipe;
194
195 if (fPipe == NULL)
196 return B_NO_MEMORY;
197
198 // Disable display pipe until modesetting enables it
199 if (fPipe->IsEnabled())
200 fPipe->Enable(false);
201
202 read32(portRegister);
203
204 return B_OK;
205 }
206
207
208 status_t
Power(bool enabled)209 Port::Power(bool enabled)
210 {
211 if (fPipe == NULL) {
212 ERROR("%s: Setting power mode without assigned pipe!\n", __func__);
213 return B_ERROR;
214 }
215
216 fPipe->Enable(enabled);
217
218 return B_OK;
219 }
220
221
222 status_t
GetEDID(edid1_info * edid,bool forceRead)223 Port::GetEDID(edid1_info* edid, bool forceRead)
224 {
225 CALLED();
226
227 if (fEDIDState == B_NO_INIT || forceRead) {
228 TRACE("%s: trying to read EDID\n", PortName());
229
230 i2c_bus bus;
231 if (SetupI2c(&bus) != B_OK)
232 return fEDIDState;
233
234 fEDIDState = ddc2_read_edid1(&bus, &fEDIDInfo, NULL, NULL);
235
236 if (fEDIDState == B_OK) {
237 TRACE("%s: found EDID information!\n", PortName());
238 edid_dump(&fEDIDInfo);
239 } else if (SetupI2cFallback(&bus) == B_OK) {
240 fEDIDState = ddc2_read_edid1(&bus, &fEDIDInfo, NULL, NULL);
241
242 if (fEDIDState == B_OK) {
243 TRACE("%s: found EDID information!\n", PortName());
244 edid_dump(&fEDIDInfo);
245 }
246 }
247 }
248
249 if (fEDIDState != B_OK) {
250 TRACE("%s: no EDID information found.\n", PortName());
251 return fEDIDState;
252 }
253
254 if (edid != NULL)
255 memcpy(edid, &fEDIDInfo, sizeof(edid1_info));
256
257 return B_OK;
258 }
259
260
261 status_t
SetupI2c(i2c_bus * bus)262 Port::SetupI2c(i2c_bus *bus)
263 {
264 addr_t ddcRegister = _DDCRegister();
265 if (ddcRegister == 0) {
266 TRACE("%s: no DDC register found\n", PortName());
267 fEDIDState = B_ERROR;
268 return fEDIDState;
269 }
270
271 TRACE("%s: using ddc @ 0x%" B_PRIxADDR "\n", PortName(), ddcRegister);
272
273 ddc2_init_timing(bus);
274 bus->cookie = (void*)ddcRegister;
275 bus->set_signals = &_SetI2CSignals;
276 bus->get_signals = &_GetI2CSignals;
277
278 return B_OK;
279 }
280
281
282 status_t
SetupI2cFallback(i2c_bus * bus)283 Port::SetupI2cFallback(i2c_bus *bus)
284 {
285 return B_ERROR;
286 }
287
288
289 status_t
GetPLLLimits(pll_limits & limits)290 Port::GetPLLLimits(pll_limits& limits)
291 {
292 return B_ERROR;
293 }
294
295
296 pipe_index
PipePreference()297 Port::PipePreference()
298 {
299 CALLED();
300 // Ideally we could just return INTEL_PIPE_ANY for all devices by default, but
301 // this doesn't quite work yet. We need to use the BIOS presetup pipes for now.
302 if (gInfo->shared_info->device_type.Generation() < 4)
303 return INTEL_PIPE_ANY;
304
305 // Notes:
306 // - The BIOSes seen sofar do not use PIPE C by default.
307 // - The BIOSes seen sofar program transcoder A to PIPE A, etc.
308 // - Later devices add a pipe C alongside the added transcoder C.
309
310 if ((gInfo->shared_info->device_type.Generation() <= 7) &&
311 (!gInfo->shared_info->device_type.HasDDI())) {
312 uint32 portState = read32(_PortRegister());
313 if (gInfo->shared_info->pch_info == INTEL_PCH_CPT) {
314 portState &= PORT_TRANS_SEL_MASK;
315 if (portState == PORT_TRANS_B_SEL_CPT)
316 return INTEL_PIPE_B;
317 else
318 return INTEL_PIPE_A;
319 } else {
320 if (portState & DISPLAY_MONITOR_PIPE_B)
321 return INTEL_PIPE_B;
322 else
323 return INTEL_PIPE_A;
324 }
325 }
326
327 if (gInfo->shared_info->device_type.HasDDI()) {
328 // scan all our pipes to find the one connected to the current port
329 uint32 pipeState = 0;
330 for (uint32 pipeCnt = 0; pipeCnt < 4; pipeCnt++) {
331 switch (pipeCnt) {
332 case 0:
333 pipeState = read32(PIPE_DDI_FUNC_CTL_A);
334 break;
335 case 1:
336 pipeState = read32(PIPE_DDI_FUNC_CTL_B);
337 break;
338 case 2:
339 pipeState = read32(PIPE_DDI_FUNC_CTL_C);
340 break;
341 default:
342 pipeState = read32(PIPE_DDI_FUNC_CTL_EDP);
343 break;
344 }
345
346 if ((((pipeState & PIPE_DDI_SELECT_MASK) >> PIPE_DDI_SELECT_SHIFT) + 1)
347 == (uint32)PortIndex()) {
348 switch (pipeCnt) {
349 case 0:
350 return INTEL_PIPE_A;
351 case 1:
352 return INTEL_PIPE_B;
353 case 2:
354 return INTEL_PIPE_C;
355 default:
356 return INTEL_PIPE_D;
357 }
358 }
359 }
360 }
361
362 return INTEL_PIPE_ANY;
363 }
364
365
366 status_t
_GetI2CSignals(void * cookie,int * _clock,int * _data)367 Port::_GetI2CSignals(void* cookie, int* _clock, int* _data)
368 {
369 addr_t ioRegister = (addr_t)cookie;
370 uint32 value = read32(ioRegister);
371
372 *_clock = (value & I2C_CLOCK_VALUE_IN) != 0;
373 *_data = (value & I2C_DATA_VALUE_IN) != 0;
374
375 return B_OK;
376 }
377
378
379 status_t
_SetI2CSignals(void * cookie,int clock,int data)380 Port::_SetI2CSignals(void* cookie, int clock, int data)
381 {
382 addr_t ioRegister = (addr_t)cookie;
383 uint32 value;
384
385 if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_83x)) {
386 // on these chips, the reserved values are fixed
387 value = 0;
388 } else {
389 // on all others, we have to preserve them manually
390 value = read32(ioRegister) & I2C_RESERVED;
391 }
392
393 // if we send clk or data, we always send low logic level;
394 // if we want to send high level, we actually receive and let the
395 // external pullup resistors create the high level on the bus.
396 value |= I2C_DATA_VALUE_MASK; //sets data = 0, always latch
397 value |= I2C_CLOCK_VALUE_MASK; //sets clock = 0, always latch
398
399 if (data != 0)
400 value |= I2C_DATA_DIRECTION_MASK;
401 else {
402 value |= I2C_DATA_DIRECTION_MASK | I2C_DATA_DIRECTION_OUT;
403 }
404
405 if (clock != 0)
406 value |= I2C_CLOCK_DIRECTION_MASK;
407 else {
408 value |= I2C_CLOCK_DIRECTION_MASK | I2C_CLOCK_DIRECTION_OUT;
409 }
410
411 write32(ioRegister, value);
412 read32(ioRegister);
413 // make sure the PCI bus has flushed the write
414
415 return B_OK;
416 }
417
418
419 bool
_IsPortInVBT(uint32 * foundIndex)420 Port::_IsPortInVBT(uint32* foundIndex)
421 {
422 // check VBT mapping
423 bool found = false;
424 const uint32 deviceConfigCount = gInfo->shared_info->device_config_count;
425 for (uint32 i = 0; i < deviceConfigCount; i++) {
426 child_device_config& config = gInfo->shared_info->device_configs[i];
427 if (config.dvo_port > DVO_PORT_HDMII) {
428 ERROR("%s: DVO port unknown\n", __func__);
429 continue;
430 }
431 dvo_port port = (dvo_port)config.dvo_port;
432 switch (PortIndex()) {
433 case INTEL_PORT_A:
434 found = port == DVO_PORT_HDMIA || port == DVO_PORT_DPA;
435 break;
436 case INTEL_PORT_B:
437 found = port == DVO_PORT_HDMIB || port == DVO_PORT_DPB;
438 break;
439 case INTEL_PORT_C:
440 found = port == DVO_PORT_HDMIC || port == DVO_PORT_DPC;
441 break;
442 case INTEL_PORT_D:
443 found = port == DVO_PORT_HDMID || port == DVO_PORT_DPD;
444 break;
445 case INTEL_PORT_E:
446 found = port == DVO_PORT_HDMIE || port == DVO_PORT_DPE || port == DVO_PORT_CRT;
447 break;
448 case INTEL_PORT_F:
449 found = port == DVO_PORT_HDMIF || port == DVO_PORT_DPF;
450 break;
451 case INTEL_PORT_G:
452 found = port == DVO_PORT_HDMIG || port == DVO_PORT_DPG;
453 break;
454 default:
455 ERROR("%s: DDI port unknown\n", __func__);
456 break;
457 }
458 if (found) {
459 if (foundIndex != NULL)
460 *foundIndex = i;
461 break;
462 }
463 }
464 return found;
465 }
466
467
468 bool
_IsDisplayPortInVBT()469 Port::_IsDisplayPortInVBT()
470 {
471 uint32 foundIndex = 0;
472 if (!_IsPortInVBT(&foundIndex))
473 return false;
474 child_device_config& config = gInfo->shared_info->device_configs[foundIndex];
475 return config.aux_channel > 0 && (config.device_type & DEVICE_TYPE_DISPLAYPORT_OUTPUT) != 0;
476 }
477
478
479 bool
_IsHdmiInVBT()480 Port::_IsHdmiInVBT()
481 {
482 uint32 foundIndex = 0;
483 if (!_IsPortInVBT(&foundIndex))
484 return false;
485 child_device_config& config = gInfo->shared_info->device_configs[foundIndex];
486 return config.ddc_pin > 0 && ((config.device_type & DEVICE_TYPE_NOT_HDMI_OUTPUT) == 0
487 || (config.device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING) != 0);
488 }
489
490
491 bool
_IsEDPPort()492 Port::_IsEDPPort()
493 {
494 uint32 foundIndex = 0;
495 if (!_IsPortInVBT(&foundIndex))
496 return false;
497 child_device_config& config = gInfo->shared_info->device_configs[foundIndex];
498 return (config.device_type & (DEVICE_TYPE_INTERNAL_CONNECTOR | DEVICE_TYPE_DISPLAYPORT_OUTPUT))
499 == (DEVICE_TYPE_INTERNAL_CONNECTOR | DEVICE_TYPE_DISPLAYPORT_OUTPUT);
500 }
501
502
503 addr_t
_DDCPin()504 Port::_DDCPin()
505 {
506 uint32 foundIndex = 0;
507 if (!_IsPortInVBT(&foundIndex))
508 return 0;
509 child_device_config& config = gInfo->shared_info->device_configs[foundIndex];
510 if (gInfo->shared_info->pch_info >= INTEL_PCH_ICP) {
511 switch (config.ddc_pin) {
512 case 1:
513 return INTEL_I2C_IO_A;
514 case 2:
515 return INTEL_I2C_IO_B;
516 case 3:
517 return INTEL_I2C_IO_C;
518 case 4:
519 return INTEL_I2C_IO_I;
520 case 5:
521 return INTEL_I2C_IO_J;
522 case 6:
523 return INTEL_I2C_IO_K;
524 case 7:
525 return INTEL_I2C_IO_L;
526 case 8:
527 return INTEL_I2C_IO_M;
528 case 9:
529 return INTEL_I2C_IO_N;
530 default:
531 return 0;
532 }
533 } else if (gInfo->shared_info->pch_info >= INTEL_PCH_CNP) {
534 switch (config.ddc_pin) {
535 case 1:
536 return INTEL_I2C_IO_A;
537 case 2:
538 return INTEL_I2C_IO_B;
539 case 3:
540 return INTEL_I2C_IO_D;
541 case 4:
542 return INTEL_I2C_IO_C;
543 default:
544 return 0;
545 }
546 } else if (gInfo->shared_info->device_type.Generation() == 9) {
547 switch (config.ddc_pin) {
548 case 4:
549 return INTEL_I2C_IO_D;
550 case 5:
551 return INTEL_I2C_IO_E;
552 case 6:
553 return INTEL_I2C_IO_F;
554 default:
555 return 0;
556 }
557 } else if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_BDW)) {
558 switch (config.ddc_pin) {
559 case 2:
560 return INTEL_I2C_IO_A;
561 case 4:
562 return INTEL_I2C_IO_D;
563 case 5:
564 return INTEL_I2C_IO_E;
565 case 6:
566 return INTEL_I2C_IO_F;
567 default:
568 return 0;
569 }
570 } else {
571 switch (config.ddc_pin) {
572 case 1:
573 return INTEL_I2C_IO_B;
574 case 2:
575 return INTEL_I2C_IO_A;
576 case 3:
577 return INTEL_I2C_IO_C;
578 case 4:
579 return INTEL_I2C_IO_D;
580 case 5:
581 return INTEL_I2C_IO_E;
582 case 6:
583 return INTEL_I2C_IO_F;
584 default:
585 return 0;
586 }
587 }
588
589 }
590
591
592 status_t
_SetupDpAuxI2c(i2c_bus * bus)593 Port::_SetupDpAuxI2c(i2c_bus *bus)
594 {
595 CALLED();
596
597 ddc2_init_timing(bus);
598 bus->cookie = this;
599 bus->send_receive = &_DpAuxSendReceiveHook;
600
601 if (gInfo->shared_info->device_type.Generation() >= 11) {
602 uint32 value = read32(ICL_PWR_WELL_CTL_AUX2);
603 if ((value & HSW_PWR_WELL_CTL_STATE(0)) != 0)
604 return B_OK;
605
606 write32(ICL_PWR_WELL_CTL_AUX2, value | HSW_PWR_WELL_CTL_REQ(0));
607 if (!wait_for_set(ICL_PWR_WELL_CTL_AUX2, HSW_PWR_WELL_CTL_STATE(0), 1000))
608 ERROR("%s: %s AUX didn't power on within 1000us!\n", __func__, PortName());
609 }
610 return B_OK;
611 }
612
613
614 status_t
_DpAuxSendReceive(uint32 slaveAddress,const uint8 * writeBuffer,size_t writeLength,uint8 * readBuffer,size_t readLength)615 Port::_DpAuxSendReceive(uint32 slaveAddress,
616 const uint8 *writeBuffer, size_t writeLength, uint8 *readBuffer, size_t readLength)
617 {
618 size_t transferLength = 16;
619
620 dp_aux_msg message;
621 memset(&message, 0, sizeof(message));
622
623 if (writeBuffer != NULL) {
624 message.address = slaveAddress;
625 message.buffer = NULL;
626 message.request = DP_AUX_I2C_WRITE;
627 message.size = 0;
628 ssize_t result = _DpAuxTransfer(&message);
629 if (result < 0)
630 return result;
631
632 for (size_t i = 0; i < writeLength;) {
633 message.buffer = (void*)(writeBuffer + i);
634 message.size = min_c(transferLength, writeLength - i);
635 // Middle-Of-Transmission on final transaction
636 if (writeLength - i > transferLength)
637 message.request |= DP_AUX_I2C_MOT;
638 else
639 message.request &= ~DP_AUX_I2C_MOT;
640
641 for (int attempt = 0; attempt < 7; attempt++) {
642 ssize_t result = _DpAuxTransfer(&message);
643 if (result < 0) {
644 ERROR("%s: aux_ch transaction failed!\n", __func__);
645 return result;
646 }
647
648 switch (message.reply & DP_AUX_I2C_REPLY_MASK) {
649 case DP_AUX_I2C_REPLY_ACK:
650 goto nextWrite;
651 case DP_AUX_I2C_REPLY_NACK:
652 TRACE("%s: aux i2c nack\n", __func__);
653 return B_IO_ERROR;
654 case DP_AUX_I2C_REPLY_DEFER:
655 TRACE("%s: aux i2c defer\n", __func__);
656 snooze(400);
657 break;
658 default:
659 TRACE("%s: aux invalid I2C reply: 0x%02x\n",
660 __func__, message.reply);
661 return B_ERROR;
662 }
663 }
664 nextWrite:
665 if (result < 0)
666 return result;
667 i += message.size;
668 }
669 }
670
671
672 if (readBuffer != NULL) {
673 message.address = slaveAddress;
674 message.buffer = NULL;
675 message.request = DP_AUX_I2C_READ;
676 message.size = 0;
677 ssize_t result = _DpAuxTransfer(&message);
678 if (result < 0)
679 return result;
680
681 for (size_t i = 0; i < readLength;) {
682 message.buffer = readBuffer + i;
683 message.size = min_c(transferLength, readLength - i);
684 // Middle-Of-Transmission on final transaction
685 if (readLength - i > transferLength)
686 message.request |= DP_AUX_I2C_MOT;
687 else
688 message.request &= ~DP_AUX_I2C_MOT;
689
690 for (int attempt = 0; attempt < 7; attempt++) {
691 result = _DpAuxTransfer(&message);
692 if (result < 0) {
693 ERROR("%s: aux_ch transaction failed!\n", __func__);
694 return result;
695 }
696
697 switch (message.reply & DP_AUX_I2C_REPLY_MASK) {
698 case DP_AUX_I2C_REPLY_ACK:
699 goto nextRead;
700 case DP_AUX_I2C_REPLY_NACK:
701 TRACE("%s: aux i2c nack\n", __func__);
702 return B_IO_ERROR;
703 case DP_AUX_I2C_REPLY_DEFER:
704 TRACE("%s: aux i2c defer\n", __func__);
705 snooze(400);
706 break;
707 default:
708 TRACE("%s: aux invalid I2C reply: 0x%02x\n",
709 __func__, message.reply);
710 return B_ERROR;
711 }
712 }
713 nextRead:
714 if (result < 0)
715 return result;
716 if (result == 0)
717 i += message.size;
718 }
719 }
720
721 return B_OK;
722 }
723
724
725 status_t
_DpAuxSendReceiveHook(const struct i2c_bus * bus,uint32 slaveAddress,const uint8 * writeBuffer,size_t writeLength,uint8 * readBuffer,size_t readLength)726 Port::_DpAuxSendReceiveHook(const struct i2c_bus *bus, uint32 slaveAddress,
727 const uint8 *writeBuffer, size_t writeLength, uint8 *readBuffer, size_t readLength)
728 {
729 CALLED();
730 Port* port = (Port*)bus->cookie;
731 return port->_DpAuxSendReceive(slaveAddress, writeBuffer, writeLength, readBuffer, readLength);
732 }
733
734
735 ssize_t
_DpAuxTransfer(dp_aux_msg * message)736 Port::_DpAuxTransfer(dp_aux_msg* message)
737 {
738 CALLED();
739 if (message == NULL) {
740 ERROR("%s: DP message is invalid!\n", __func__);
741 return B_ERROR;
742 }
743
744 if (message->size > 16) {
745 ERROR("%s: Too many bytes! (%" B_PRIuSIZE ")\n", __func__,
746 message->size);
747 return B_ERROR;
748 }
749
750 uint8 transmitSize = message->size > 0 ? 4 : 3;
751 uint8 receiveSize;
752
753 switch(message->request & ~DP_AUX_I2C_MOT) {
754 case DP_AUX_NATIVE_WRITE:
755 case DP_AUX_I2C_WRITE:
756 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
757 transmitSize += message->size;
758 break;
759 }
760
761 // If not bare address, check for buffer
762 if (message->size > 0 && message->buffer == NULL) {
763 ERROR("%s: DP message uninitalized buffer!\n", __func__);
764 return B_ERROR;
765 }
766
767 uint8 receiveBuffer[20];
768 uint8 transmitBuffer[20];
769 transmitBuffer[0] = (message->request << 4) | ((message->address >> 16) & 0xf);
770 transmitBuffer[1] = (message->address >> 8) & 0xff;
771 transmitBuffer[2] = message->address & 0xff;
772 transmitBuffer[3] = message->size != 0 ? (message->size - 1) : 0;
773
774 uint8 retry;
775 for (retry = 0; retry < 7; retry++) {
776 ssize_t result = B_ERROR;
777 switch(message->request & ~DP_AUX_I2C_MOT) {
778 case DP_AUX_NATIVE_WRITE:
779 case DP_AUX_I2C_WRITE:
780 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
781 receiveSize = 2;
782 if (message->buffer != NULL)
783 memcpy(transmitBuffer + 4, message->buffer, message->size);
784 result = _DpAuxTransfer(transmitBuffer,
785 transmitSize, receiveBuffer, receiveSize);
786 if (result > 0) {
787 message->reply = receiveBuffer[0] >> 4;
788 if (result > 1)
789 result = min_c(receiveBuffer[1], message->size);
790 else
791 result = message->size;
792 }
793 break;
794 case DP_AUX_NATIVE_READ:
795 case DP_AUX_I2C_READ:
796 receiveSize = message->size + 1;
797 result = _DpAuxTransfer(transmitBuffer,
798 transmitSize, receiveBuffer, receiveSize);
799 if (result > 0) {
800 message->reply = receiveBuffer[0] >> 4;
801 result--;
802 if (message->buffer != NULL)
803 memcpy(message->buffer, receiveBuffer + 1, result);
804 }
805 break;
806 default:
807 ERROR("%s: Unknown dp_aux_msg request!\n", __func__);
808 return B_ERROR;
809 }
810
811 if (result == B_BUSY)
812 continue;
813 else if (result < B_OK)
814 return result;
815
816 switch (message->reply & DP_AUX_NATIVE_REPLY_MASK) {
817 case DP_AUX_NATIVE_REPLY_ACK:
818 return B_OK;
819 case DP_AUX_NATIVE_REPLY_NACK:
820 TRACE("%s: aux native reply nack\n", __func__);
821 return B_IO_ERROR;
822 case DP_AUX_NATIVE_REPLY_DEFER:
823 TRACE("%s: aux reply defer received. Snoozing.\n", __func__);
824 snooze(400);
825 break;
826 default:
827 TRACE("%s: aux invalid native reply: 0x%02x\n", __func__,
828 message->reply);
829 return B_IO_ERROR;
830 }
831 }
832
833 ERROR("%s: IO Error. %" B_PRIu8 " attempts\n", __func__, retry);
834 return B_IO_ERROR;
835 }
836
837
838 ssize_t
_DpAuxTransfer(uint8 * transmitBuffer,uint8 transmitSize,uint8 * receiveBuffer,uint8 receiveSize)839 Port::_DpAuxTransfer(uint8* transmitBuffer, uint8 transmitSize,
840 uint8* receiveBuffer, uint8 receiveSize)
841 {
842 addr_t channelControl;
843 addr_t channelData[5];
844 aux_channel channel = _DpAuxChannel();
845 TRACE("%s: %s DpAuxChannel: 0x%x\n", __func__, PortName(), channel);
846 if (gInfo->shared_info->device_type.Generation() >= 9
847 || (gInfo->shared_info->pch_info != INTEL_PCH_NONE && channel == AUX_CH_A)) {
848 channelControl = DP_AUX_CH_CTL(channel);
849 for (int i = 0; i < 5; i++)
850 channelData[i] = DP_AUX_CH_DATA(channel, i);
851 } else if (gInfo->shared_info->pch_info != INTEL_PCH_NONE) {
852 channelControl = PCH_DP_AUX_CH_CTL(channel);
853 for (int i = 0; i < 5; i++)
854 channelData[i] = PCH_DP_AUX_CH_DATA(channel, i);
855 } else {
856 ERROR("Port::_DpAuxTransfer() unknown register config\n");
857 return B_BUSY;
858 }
859 if (transmitSize > 20 || receiveSize > 20)
860 return E2BIG;
861
862 int tries = 0;
863 while ((read32(channelControl) & INTEL_DP_AUX_CTL_BUSY) != 0) {
864 if (tries++ == 3) {
865 ERROR("%s: %s AUX channel is busy!\n", __func__, PortName());
866 return B_BUSY;
867 }
868 snooze(1000);
869 }
870
871 uint32 sendControl = 0;
872 if (gInfo->shared_info->device_type.Generation() >= 9) {
873 sendControl = INTEL_DP_AUX_CTL_BUSY | INTEL_DP_AUX_CTL_DONE | INTEL_DP_AUX_CTL_INTERRUPT
874 | INTEL_DP_AUX_CTL_TIMEOUT_ERROR | INTEL_DP_AUX_CTL_TIMEOUT_1600us | INTEL_DP_AUX_CTL_RECEIVE_ERROR
875 | (transmitSize << INTEL_DP_AUX_CTL_MSG_SIZE_SHIFT) | INTEL_DP_AUX_CTL_FW_SYNC_PULSE_SKL(32)
876 | INTEL_DP_AUX_CTL_SYNC_PULSE_SKL(32);
877 } else {
878 uint32 frequency = gInfo->shared_info->hw_cdclk;
879 if (channel != AUX_CH_A)
880 frequency = gInfo->shared_info->hraw_clock;
881 uint32 aux_clock_divider = (frequency + 2000 / 2) / 2000;
882 if (gInfo->shared_info->pch_info == INTEL_PCH_LPT && channel != AUX_CH_A)
883 aux_clock_divider = 0x48; // or 0x3f
884 uint32 timeout = INTEL_DP_AUX_CTL_TIMEOUT_400us;
885 if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_BDW))
886 timeout = INTEL_DP_AUX_CTL_TIMEOUT_600us;
887 sendControl = INTEL_DP_AUX_CTL_BUSY | INTEL_DP_AUX_CTL_DONE | INTEL_DP_AUX_CTL_INTERRUPT
888 | INTEL_DP_AUX_CTL_TIMEOUT_ERROR | timeout | INTEL_DP_AUX_CTL_RECEIVE_ERROR
889 | (transmitSize << INTEL_DP_AUX_CTL_MSG_SIZE_SHIFT) | (3 << INTEL_DP_AUX_CTL_PRECHARGE_2US_SHIFT)
890 | (aux_clock_divider << INTEL_DP_AUX_CTL_BIT_CLOCK_2X_SHIFT);
891 }
892
893 uint8 retry;
894 uint32 status = 0;
895 for (retry = 0; retry < 5; retry++) {
896 for (uint8 i = 0; i < transmitSize;) {
897 uint8 index = i / 4;
898 uint32 data = ((uint32)transmitBuffer[i++]) << 24;
899 if (i < transmitSize)
900 data |= ((uint32)transmitBuffer[i++]) << 16;
901 if (i < transmitSize)
902 data |= ((uint32)transmitBuffer[i++]) << 8;
903 if (i < transmitSize)
904 data |= transmitBuffer[i++];
905 write32(channelData[index], data);
906 }
907 write32(channelControl, sendControl);
908
909 // wait 10 ms reading channelControl until INTEL_DP_AUX_CTL_BUSY
910 status = wait_for_clear_status(channelControl, INTEL_DP_AUX_CTL_BUSY, 10000);
911 if ((status & INTEL_DP_AUX_CTL_BUSY) != 0) {
912 ERROR("%s: %s AUX channel stayed busy for 10000us!\n", __func__, PortName());
913 }
914
915 write32(channelControl, status | INTEL_DP_AUX_CTL_DONE | INTEL_DP_AUX_CTL_TIMEOUT_ERROR
916 | INTEL_DP_AUX_CTL_RECEIVE_ERROR);
917 if ((status & INTEL_DP_AUX_CTL_TIMEOUT_ERROR) != 0)
918 continue;
919 if ((status & INTEL_DP_AUX_CTL_RECEIVE_ERROR) != 0) {
920 snooze(400);
921 continue;
922 }
923 if ((status & INTEL_DP_AUX_CTL_DONE) != 0)
924 goto done;
925 }
926
927 if ((status & INTEL_DP_AUX_CTL_DONE) == 0) {
928 ERROR("%s: Busy Error. %" B_PRIu8 " attempts\n", __func__, retry);
929 return B_BUSY;
930 }
931 done:
932 if ((status & INTEL_DP_AUX_CTL_RECEIVE_ERROR) != 0)
933 return B_IO_ERROR;
934 if ((status & INTEL_DP_AUX_CTL_TIMEOUT_ERROR) != 0)
935 return B_TIMEOUT;
936
937 uint8 bytes = (status & INTEL_DP_AUX_CTL_MSG_SIZE_MASK) >> INTEL_DP_AUX_CTL_MSG_SIZE_SHIFT;
938 if (bytes == 0 || bytes > 20) {
939 ERROR("%s: Status byte count incorrect %u\n", __func__, bytes);
940 return B_BUSY;
941 }
942 if (bytes > receiveSize)
943 bytes = receiveSize;
944 for (uint8 i = 0; i < bytes;) {
945 uint32 data = read32(channelData[i / 4]);
946 receiveBuffer[i++] = data >> 24;
947 if (i < bytes)
948 receiveBuffer[i++] = data >> 16;
949 if (i < bytes)
950 receiveBuffer[i++] = data >> 8;
951 if (i < bytes)
952 receiveBuffer[i++] = data;
953 }
954
955 return bytes;
956 }
957
958
959 aux_channel
_DpAuxChannel()960 Port::_DpAuxChannel()
961 {
962 uint32 foundIndex = 0;
963 if (!_IsPortInVBT(&foundIndex))
964 return AUX_CH_A;
965 child_device_config& config = gInfo->shared_info->device_configs[foundIndex];
966 switch (config.aux_channel) {
967 case DP_AUX_B:
968 return AUX_CH_B;
969 case DP_AUX_C:
970 return AUX_CH_C;
971 case DP_AUX_D:
972 return AUX_CH_D;
973 case DP_AUX_E:
974 return AUX_CH_E;
975 case DP_AUX_F:
976 return AUX_CH_F;
977 default:
978 return AUX_CH_A;
979 }
980 }
981
982
983 // #pragma mark - Analog Port
984
985
AnalogPort()986 AnalogPort::AnalogPort()
987 :
988 Port(INTEL_PORT_A, "Analog")
989 {
990 }
991
992
993 bool
IsConnected()994 AnalogPort::IsConnected()
995 {
996 TRACE("%s: %s PortRegister: 0x%" B_PRIxADDR "\n", __func__, PortName(),
997 _PortRegister());
998 return HasEDID();
999 }
1000
1001
1002 addr_t
_DDCRegister()1003 AnalogPort::_DDCRegister()
1004 {
1005 // always fixed
1006 return INTEL_I2C_IO_A;
1007 }
1008
1009
1010 addr_t
_PortRegister()1011 AnalogPort::_PortRegister()
1012 {
1013 // always fixed
1014 return INTEL_ANALOG_PORT;
1015 }
1016
1017
1018 status_t
SetDisplayMode(display_mode * target,uint32 colorMode)1019 AnalogPort::SetDisplayMode(display_mode* target, uint32 colorMode)
1020 {
1021 CALLED();
1022 TRACE("%s: %s %dx%d\n", __func__, PortName(), target->timing.h_display,
1023 target->timing.v_display);
1024
1025 if (fPipe == NULL) {
1026 ERROR("%s: Setting display mode without assigned pipe!\n", __func__);
1027 return B_ERROR;
1028 }
1029
1030 // Setup PanelFitter and Train FDI if it exists
1031 PanelFitter* fitter = fPipe->PFT();
1032 if (fitter != NULL)
1033 fitter->Enable(target->timing);
1034 FDILink* link = fPipe->FDI();
1035 if (link != NULL) {
1036 uint32 lanes = 0;
1037 uint32 linkBandwidth = 0;
1038 uint32 bitsPerPixel = 0;
1039 link->PreTrain(&target->timing, &linkBandwidth, &lanes, &bitsPerPixel);
1040 fPipe->SetFDILink(target->timing, linkBandwidth, lanes, bitsPerPixel);
1041 link->Train(&target->timing, lanes);
1042 }
1043 pll_divisors divisors;
1044 compute_pll_divisors(&target->timing, &divisors, false);
1045
1046 uint32 extraPLLFlags = 0;
1047 if (gInfo->shared_info->device_type.Generation() >= 3)
1048 extraPLLFlags |= DISPLAY_PLL_MODE_NORMAL;
1049
1050 // Program general pipe config
1051 fPipe->Configure(target);
1052
1053 // Program pipe PLL's
1054 fPipe->ConfigureClocks(divisors, target->timing.pixel_clock, extraPLLFlags);
1055
1056 write32(_PortRegister(), (read32(_PortRegister())
1057 & ~(DISPLAY_MONITOR_POLARITY_MASK | DISPLAY_MONITOR_VGA_POLARITY))
1058 | ((target->timing.flags & B_POSITIVE_HSYNC) != 0
1059 ? DISPLAY_MONITOR_POSITIVE_HSYNC : 0)
1060 | ((target->timing.flags & B_POSITIVE_VSYNC) != 0
1061 ? DISPLAY_MONITOR_POSITIVE_VSYNC : 0));
1062
1063 // Program target display mode
1064 fPipe->ConfigureTimings(target);
1065
1066 // Set fCurrentMode to our set display mode
1067 memcpy(&fCurrentMode, target, sizeof(display_mode));
1068
1069 return B_OK;
1070 }
1071
1072
1073 // #pragma mark - LVDS Panel
1074
1075
LVDSPort()1076 LVDSPort::LVDSPort()
1077 :
1078 Port(INTEL_PORT_C, "LVDS")
1079 {
1080 // Always unlock LVDS port as soon as we start messing with it.
1081 uint32 panelControl = INTEL_PANEL_CONTROL;
1082 if (gInfo->shared_info->pch_info != INTEL_PCH_NONE) {
1083 // FIXME writing there results in black screen on SandyBridge
1084 return;
1085 // panelControl = PCH_PANEL_CONTROL;
1086 }
1087 write32(panelControl, read32(panelControl) | PANEL_REGISTER_UNLOCK);
1088 }
1089
1090
1091 pipe_index
PipePreference()1092 LVDSPort::PipePreference()
1093 {
1094 CALLED();
1095 // Older devices have hardcoded pipe/port mappings, so just use that
1096 if (gInfo->shared_info->device_type.Generation() < 4)
1097 return INTEL_PIPE_B;
1098
1099 // Ideally we could just return INTEL_PIPE_ANY for the newer devices, but
1100 // this doesn't quite work yet.
1101
1102 // On SandyBridge and later, there is a transcoder C. On SandyBridge at least
1103 // that can't be used by the LVDS port (but A and B would be fine).
1104 // On Ibex Point, SandyBridge and IvyBridge (tested) changing pipes does not
1105 // work yet.
1106 // Notes:
1107 // - Switching Pipes only works reliably when a 'full modeswitch' is executed
1108 // (FDI training) so we have to reuse the BIOS preset setup always for now.
1109 // - The BIOSes seen sofar do not use PIPE C by default.
1110 // - The BIOSes seen sofar program transcoder A to PIPE A, etc.
1111 // - Later devices add a pipe C alongside the added transcoder C.
1112
1113 // FIXME How's this setup in newer gens? Currently return Pipe B fixed there..
1114 if (gInfo->shared_info->device_type.Generation() <= 7) {
1115 uint32 portState = read32(_PortRegister());
1116 if (gInfo->shared_info->pch_info == INTEL_PCH_CPT) {
1117 portState &= PORT_TRANS_SEL_MASK;
1118 if (portState == PORT_TRANS_B_SEL_CPT)
1119 return INTEL_PIPE_B;
1120 else
1121 return INTEL_PIPE_A;
1122 } else {
1123 if (portState & DISPLAY_MONITOR_PIPE_B)
1124 return INTEL_PIPE_B;
1125 else
1126 return INTEL_PIPE_A;
1127 }
1128 }
1129
1130 return INTEL_PIPE_B;
1131 }
1132
1133
1134 bool
IsConnected()1135 LVDSPort::IsConnected()
1136 {
1137 TRACE("%s: %s PortRegister: 0x%" B_PRIxADDR "\n", __func__, PortName(),
1138 _PortRegister());
1139
1140 if (gInfo->shared_info->pch_info != INTEL_PCH_NONE) {
1141 uint32 registerValue = read32(_PortRegister());
1142 // there's a detection bit we can use
1143 if ((registerValue & PCH_LVDS_DETECTED) == 0) {
1144 TRACE("LVDS: Not detected\n");
1145 return false;
1146 }
1147 // TODO: Skip if eDP support
1148 } else if (gInfo->shared_info->device_type.Generation() <= 4) {
1149 // Older generations don't have LVDS detection. If not mobile skip.
1150 if (!gInfo->shared_info->device_type.IsMobile()) {
1151 TRACE("LVDS: Skipping LVDS detection due to gen and not mobile\n");
1152 return false;
1153 }
1154 // If mobile, try to grab EDID
1155 // Linux seems to look at lid status for LVDS port detection
1156 // If we don't get EDID, we can use vbios native mode or vesa?
1157 if (!HasEDID()) {
1158 if (gInfo->shared_info->has_vesa_edid_info) {
1159 TRACE("LVDS: Using VESA edid info\n");
1160 memcpy(&fEDIDInfo, &gInfo->shared_info->vesa_edid_info,
1161 sizeof(edid1_info));
1162 if (fEDIDState != B_OK) {
1163 fEDIDState = B_OK;
1164 // HasEDID now true
1165 edid_dump(&fEDIDInfo);
1166 }
1167 } else if (gInfo->shared_info->got_vbt) {
1168 TRACE("LVDS: No EDID, but force enabled as we have a VBT\n");
1169 return true;
1170 } else {
1171 TRACE("LVDS: Couldn't find any valid EDID!\n");
1172 return false;
1173 }
1174 }
1175 }
1176
1177 // Try getting EDID, as the LVDS port doesn't overlap with anything else,
1178 // we don't run the risk of getting someone else's data.
1179 return HasEDID();
1180 }
1181
1182
1183 addr_t
_DDCRegister()1184 LVDSPort::_DDCRegister()
1185 {
1186 // always fixed
1187 return INTEL_I2C_IO_C;
1188 }
1189
1190
1191 addr_t
_PortRegister()1192 LVDSPort::_PortRegister()
1193 {
1194 // always fixed
1195 return INTEL_DIGITAL_LVDS_PORT;
1196 }
1197
1198
1199 status_t
SetDisplayMode(display_mode * target,uint32 colorMode)1200 LVDSPort::SetDisplayMode(display_mode* target, uint32 colorMode)
1201 {
1202 CALLED();
1203 if (target == NULL) {
1204 ERROR("%s: Invalid target mode passed!\n", __func__);
1205 return B_ERROR;
1206 }
1207
1208 TRACE("%s: %s-%d %dx%d\n", __func__, PortName(), PortIndex(),
1209 target->timing.h_display, target->timing.v_display);
1210
1211 if (fPipe == NULL) {
1212 ERROR("%s: Setting display mode without assigned pipe!\n", __func__);
1213 return B_ERROR;
1214 }
1215
1216 addr_t panelControl = INTEL_PANEL_CONTROL;
1217 addr_t panelStatus = INTEL_PANEL_STATUS;
1218 if (gInfo->shared_info->pch_info != INTEL_PCH_NONE) {
1219 panelControl = PCH_PANEL_CONTROL;
1220 panelStatus = PCH_PANEL_STATUS;
1221 }
1222
1223 if (gInfo->shared_info->device_type.Generation() != 4) {
1224 // TODO not needed on any generation if we are using the panel fitter
1225 // Power off Panel
1226 write32(panelControl,
1227 read32(panelControl) & ~PANEL_CONTROL_POWER_TARGET_ON);
1228 read32(panelControl);
1229
1230 if (!wait_for_clear(panelStatus, PANEL_STATUS_POWER_ON, 1000)) {
1231 ERROR("%s: %s didn't power off within 1000ms!\n", __func__,
1232 PortName());
1233 }
1234 }
1235
1236 // For LVDS panels, we may need to set the timings according to the panel
1237 // native video mode, and let the panel fitter do the scaling. But the
1238 // place where the scaling happens varies accross generations of devices.
1239 display_timing hardwareTarget;
1240 bool needsScaling = false;
1241
1242 // TODO figure out how it's done (or if we need to configure something at
1243 // all) for other generations
1244 if (gInfo->shared_info->device_type.Generation() <= 6
1245 && gInfo->shared_info->device_type.Generation() >= 3
1246 && gInfo->shared_info->got_vbt) {
1247 // Set vbios hardware panel mode as base
1248 hardwareTarget = gInfo->shared_info->panel_timing;
1249
1250 if (hardwareTarget.h_display == target->timing.h_display
1251 && hardwareTarget.v_display == target->timing.v_display) {
1252 // We are setting the native video mode, nothing special to do
1253 // Note: this means refresh and timing might vary according to requested mode.
1254 hardwareTarget = target->timing;
1255 TRACE("%s: Setting LVDS to native resolution at %" B_PRIu32 "Hz\n", __func__,
1256 hardwareTarget.pixel_clock * 1000 / (hardwareTarget.h_total * hardwareTarget.v_total));
1257 } else {
1258 // We need to enable the panel fitter
1259 TRACE("%s: Hardware mode will actually be %dx%d at %" B_PRIu32 "Hz\n", __func__,
1260 hardwareTarget.h_display, hardwareTarget.v_display,
1261 hardwareTarget.pixel_clock * 1000 / (hardwareTarget.h_total * hardwareTarget.v_total));
1262
1263 // FIXME we should also get the refresh frequency from the target
1264 // mode, and then "sanitize" the resulting mode we made up.
1265 needsScaling = true;
1266 }
1267 } else {
1268 TRACE("Setting LVDS mode without VBT info or on unhandled hardware "
1269 "generation, scaling may not work\n");
1270 // We don't have VBT data, try to set the requested mode directly
1271 // and hope for the best
1272 hardwareTarget = target->timing;
1273 }
1274
1275 // Setup PanelFitter and Train FDI if it exists
1276 PanelFitter* fitter = fPipe->PFT();
1277 if (fitter != NULL)
1278 fitter->Enable(hardwareTarget);
1279 FDILink* link = fPipe->FDI();
1280 if (link != NULL) {
1281 uint32 lanes = 0;
1282 uint32 linkBandwidth = 0;
1283 uint32 bitsPerPixel = 0;
1284 link->PreTrain(&hardwareTarget, &linkBandwidth, &lanes, &bitsPerPixel);
1285 fPipe->SetFDILink(hardwareTarget, linkBandwidth, lanes, bitsPerPixel);
1286 link->Train(&hardwareTarget, lanes);
1287 }
1288
1289 pll_divisors divisors;
1290 compute_pll_divisors(&hardwareTarget, &divisors, true);
1291
1292 uint32 lvds = read32(_PortRegister())
1293 | LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
1294
1295 if (gInfo->shared_info->device_type.Generation() == 4) {
1296 // LVDS_A3_POWER_UP == 24bpp
1297 // otherwise, 18bpp
1298 if ((lvds & LVDS_A3_POWER_MASK) != LVDS_A3_POWER_UP)
1299 lvds |= LVDS_18BIT_DITHER;
1300 }
1301
1302 // LVDS on PCH needs set before display enable
1303 if (gInfo->shared_info->pch_info == INTEL_PCH_CPT) {
1304 lvds &= ~PORT_TRANS_SEL_MASK;
1305 if (fPipe->Index() == INTEL_PIPE_A)
1306 lvds |= PORT_TRANS_A_SEL_CPT;
1307 else
1308 lvds |= PORT_TRANS_B_SEL_CPT;
1309 }
1310
1311 // Set the B0-B3 data pairs corresponding to whether we're going to
1312 // set the DPLLs for dual-channel mode or not.
1313 if (divisors.p2 == 5 || divisors.p2 == 7) {
1314 TRACE("LVDS: dual channel\n");
1315 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
1316 } else {
1317 TRACE("LVDS: single channel\n");
1318 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
1319 }
1320
1321 // LVDS port control moves polarity bits because Intel hates you.
1322 // Set LVDS sync polarity
1323 lvds &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
1324
1325 // set on - polarity.
1326 if ((target->timing.flags & B_POSITIVE_HSYNC) == 0)
1327 lvds |= LVDS_HSYNC_POLARITY;
1328 if ((target->timing.flags & B_POSITIVE_VSYNC) == 0)
1329 lvds |= LVDS_VSYNC_POLARITY;
1330
1331 TRACE("%s: LVDS Write: 0x%" B_PRIx32 "\n", __func__, lvds);
1332 write32(_PortRegister(), lvds);
1333 read32(_PortRegister());
1334
1335 uint32 extraPLLFlags = 0;
1336
1337 // DPLL mode LVDS for i915+
1338 if (gInfo->shared_info->device_type.Generation() >= 3)
1339 extraPLLFlags |= DISPLAY_PLL_MODE_LVDS | DISPLAY_PLL_2X_CLOCK;
1340
1341 // Program general pipe config
1342 fPipe->Configure(target);
1343
1344 // Program pipe PLL's (using the hardware mode timings, since that's what
1345 // the PLL is used for)
1346 fPipe->ConfigureClocks(divisors, hardwareTarget.pixel_clock,
1347 extraPLLFlags);
1348
1349 if (gInfo->shared_info->device_type.Generation() != 4) {
1350 // G45: no need to power the panel off
1351 // Power on Panel
1352 write32(panelControl,
1353 read32(panelControl) | PANEL_CONTROL_POWER_TARGET_ON);
1354 read32(panelControl);
1355
1356 if (!wait_for_set(panelStatus, PANEL_STATUS_POWER_ON, 1000)) {
1357 ERROR("%s: %s didn't power on within 1000us!\n", __func__,
1358 PortName());
1359 }
1360 }
1361
1362 // Program target display mode
1363 fPipe->ConfigureTimings(target, !needsScaling);
1364
1365 if (needsScaling) {
1366 if (gInfo->shared_info->device_type.Generation() <= 4) {
1367 // Enable panel fitter in automatic mode. It will figure out
1368 // the scaling ratios automatically.
1369 uint32 panelFitterControl = read32(INTEL_PANEL_FIT_CONTROL);
1370 panelFitterControl |= PANEL_FITTER_ENABLED;
1371 panelFitterControl &= ~(PANEL_FITTER_SCALING_MODE_MASK
1372 | PANEL_FITTER_PIPE_MASK);
1373 panelFitterControl |= PANEL_FITTER_PIPE_B;
1374 // LVDS is always on pipe B.
1375 write32(INTEL_PANEL_FIT_CONTROL, panelFitterControl);
1376 }
1377 // TODO do we need to do anything on later generations?
1378 } else {
1379 if (gInfo->shared_info->device_type.Generation() == 4
1380 || gInfo->shared_info->device_type.Generation() == 3) {
1381 // Bypass the panel fitter
1382 uint32 panelFitterControl = read32(INTEL_PANEL_FIT_CONTROL);
1383 panelFitterControl &= ~PANEL_FITTER_ENABLED;
1384 write32(INTEL_PANEL_FIT_CONTROL, panelFitterControl);
1385 } else {
1386 // We don't need to do anything more for later generations, the
1387 // scaling is handled at the transcoder level. We may want to
1388 // configure dithering, but the code below ignores the previous
1389 // value in the register and may mess things up so we should do
1390 // this in a safeer way. For now, assume the BIOS did the right
1391 // thing.
1392 #if 0
1393 // Disable panel fitting, but enable 8 to 6-bit dithering
1394 write32(INTEL_PANEL_FIT_CONTROL, 0x4);
1395 // TODO: do not do this if the connected panel is 24-bit
1396 // (I don't know how to detect that)
1397 #endif
1398 }
1399 }
1400
1401 // Set fCurrentMode to our set display mode
1402 memcpy(&fCurrentMode, target, sizeof(display_mode));
1403
1404 return B_OK;
1405 }
1406
1407
1408 // #pragma mark - DVI/SDVO/generic
1409
1410
DigitalPort(port_index index,const char * baseName)1411 DigitalPort::DigitalPort(port_index index, const char* baseName)
1412 :
1413 Port(index, baseName)
1414 {
1415 }
1416
1417
1418 bool
IsConnected()1419 DigitalPort::IsConnected()
1420 {
1421 TRACE("%s: %s PortRegister: 0x%" B_PRIxADDR "\n", __func__, PortName(),
1422 _PortRegister());
1423
1424 // As this port overlaps with pretty much everything, this must be called
1425 // after having ruled out all other port types.
1426 return HasEDID();
1427 }
1428
1429
1430 addr_t
_DDCRegister()1431 DigitalPort::_DDCRegister()
1432 {
1433 //TODO: IS BROXTON, B = B, C = C, D = NIL
1434 switch (PortIndex()) {
1435 case INTEL_PORT_B:
1436 return INTEL_I2C_IO_E;
1437 case INTEL_PORT_C:
1438 return INTEL_I2C_IO_D;
1439 case INTEL_PORT_D:
1440 return INTEL_I2C_IO_F;
1441 default:
1442 return 0;
1443 }
1444
1445 return 0;
1446 }
1447
1448
1449 addr_t
_PortRegister()1450 DigitalPort::_PortRegister()
1451 {
1452 switch (PortIndex()) {
1453 case INTEL_PORT_A:
1454 return INTEL_DIGITAL_PORT_A;
1455 case INTEL_PORT_B:
1456 return INTEL_DIGITAL_PORT_B;
1457 case INTEL_PORT_C:
1458 return INTEL_DIGITAL_PORT_C;
1459 default:
1460 return 0;
1461 }
1462 return 0;
1463 }
1464
1465
1466 status_t
SetDisplayMode(display_mode * target,uint32 colorMode)1467 DigitalPort::SetDisplayMode(display_mode* target, uint32 colorMode)
1468 {
1469 CALLED();
1470 TRACE("%s: %s %dx%d\n", __func__, PortName(), target->timing.h_display,
1471 target->timing.v_display);
1472
1473 if (fPipe == NULL) {
1474 ERROR("%s: Setting display mode without assigned pipe!\n", __func__);
1475 return B_ERROR;
1476 }
1477
1478 // Setup PanelFitter and Train FDI if it exists
1479 PanelFitter* fitter = fPipe->PFT();
1480 if (fitter != NULL)
1481 fitter->Enable(target->timing);
1482 FDILink* link = fPipe->FDI();
1483 if (link != NULL) {
1484 uint32 lanes = 0;
1485 uint32 linkBandwidth = 0;
1486 uint32 bitsPerPixel = 0;
1487 link->PreTrain(&target->timing, &linkBandwidth, &lanes, &bitsPerPixel);
1488 fPipe->SetFDILink(target->timing, linkBandwidth, lanes, bitsPerPixel);
1489 link->Train(&target->timing, lanes);
1490 }
1491
1492 pll_divisors divisors;
1493 compute_pll_divisors(&target->timing, &divisors, false);
1494
1495 uint32 extraPLLFlags = 0;
1496 if (gInfo->shared_info->device_type.Generation() >= 3)
1497 extraPLLFlags |= DISPLAY_PLL_MODE_NORMAL | DISPLAY_PLL_2X_CLOCK;
1498
1499 // Program general pipe config
1500 fPipe->Configure(target);
1501
1502 // Program pipe PLL's
1503 fPipe->ConfigureClocks(divisors, target->timing.pixel_clock, extraPLLFlags);
1504
1505 // Program target display mode
1506 fPipe->ConfigureTimings(target);
1507
1508 // Set fCurrentMode to our set display mode
1509 memcpy(&fCurrentMode, target, sizeof(display_mode));
1510
1511 return B_OK;
1512 }
1513
1514
1515 // #pragma mark - LVDS Panel
1516 // #pragma mark - HDMI
1517
1518
HDMIPort(port_index index)1519 HDMIPort::HDMIPort(port_index index)
1520 :
1521 DigitalPort(index, "HDMI")
1522 {
1523 }
1524
1525
1526 bool
IsConnected()1527 HDMIPort::IsConnected()
1528 {
1529 if (!gInfo->shared_info->device_type.SupportsHDMI())
1530 return false;
1531
1532 addr_t portRegister = _PortRegister();
1533 TRACE("%s: %s PortRegister: 0x%" B_PRIxADDR "\n", __func__, PortName(),
1534 portRegister);
1535
1536 if (portRegister == 0)
1537 return false;
1538
1539 const uint32 deviceConfigCount = gInfo->shared_info->device_config_count;
1540 if (gInfo->shared_info->device_type.Generation() >= 6 && deviceConfigCount > 0) {
1541 // check VBT mapping
1542 if (!_IsPortInVBT()) {
1543 TRACE("%s: %s: port not found in VBT\n", __func__, PortName());
1544 return false;
1545 } else
1546 TRACE("%s: %s: port found in VBT\n", __func__, PortName());
1547 }
1548
1549 //Notes:
1550 //- DISPLAY_MONITOR_PORT_DETECTED does only tell you *some* sort of digital display is
1551 // connected to the port *if* you have the AUX channel stuff under power. It does not
1552 // tell you which -type- of digital display is connected.
1553 //- Since we rely on the BIOS anyway, let's just use the conclusions it made for us :)
1554 // Beware though: set_display_power_mode() uses this DISPLAY_MONITOR_PORT_ENABLED bit
1555 // for DPMS as well. So we should better buffer our findings here for i.e. possible
1556 // accelerant clones starting up. For DPMS there's currently no problem as this bit
1557 // is only programmed for LVDS, DVI and VGA while we detect presence only for DP and HDMI.
1558 //
1559 //if ((read32(portRegister) & DISPLAY_MONITOR_PORT_DETECTED) == 0)
1560 if ((read32(portRegister) & DISPLAY_MONITOR_PORT_ENABLED) == 0)
1561 return false;
1562
1563 return HasEDID();
1564 }
1565
1566
1567 addr_t
_PortRegister()1568 HDMIPort::_PortRegister()
1569 {
1570 // on PCH there's an additional port sandwiched in
1571 bool hasPCH = (gInfo->shared_info->pch_info != INTEL_PCH_NONE);
1572 bool fourthGen = gInfo->shared_info->device_type.InGroup(INTEL_GROUP_VLV);
1573
1574 switch (PortIndex()) {
1575 case INTEL_PORT_B:
1576 if (fourthGen)
1577 return GEN4_HDMI_PORT_B;
1578 return hasPCH ? PCH_HDMI_PORT_B : INTEL_HDMI_PORT_B;
1579 case INTEL_PORT_C:
1580 if (fourthGen)
1581 return GEN4_HDMI_PORT_C;
1582 return hasPCH ? PCH_HDMI_PORT_C : INTEL_HDMI_PORT_C;
1583 case INTEL_PORT_D:
1584 if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_CHV))
1585 return CHV_HDMI_PORT_D;
1586 return hasPCH ? PCH_HDMI_PORT_D : 0;
1587 default:
1588 return 0;
1589 }
1590
1591 return 0;
1592 }
1593
1594
1595 // #pragma mark - DisplayPort
1596
1597
DisplayPort(port_index index,const char * baseName)1598 DisplayPort::DisplayPort(port_index index, const char* baseName)
1599 :
1600 Port(index, baseName)
1601 {
1602 }
1603
1604
1605 pipe_index
PipePreference()1606 DisplayPort::PipePreference()
1607 {
1608 CALLED();
1609 if (gInfo->shared_info->device_type.Generation() <= 4)
1610 return INTEL_PIPE_ANY;
1611
1612 // Notes:
1613 // - The BIOSes seen sofar do not use PIPE C by default.
1614 // - Looks like BIOS selected Transcoder (A,B,C) is not always same as selected Pipe (A,B,C)
1615 // so these should probably be handled seperately. For now this is OK as we don't touch
1616 // the pipe for DisplayPort, only the transcoder..
1617 uint32 TranscoderPort = INTEL_TRANS_DP_PORT_NONE;
1618 switch (PortIndex()) {
1619 case INTEL_PORT_A:
1620 if (gInfo->shared_info->device_type.Generation() == 6) {
1621 if (((read32(INTEL_DISPLAY_PORT_A) & INTEL_DISP_PORTA_SNB_PIPE_MASK)
1622 >> INTEL_DISP_PORTA_SNB_PIPE_SHIFT) == INTEL_DISP_PORTA_SNB_PIPE_A) {
1623 return INTEL_PIPE_A;
1624 } else {
1625 return INTEL_PIPE_B;
1626 }
1627 }
1628 if (gInfo->shared_info->device_type.Generation() == 7) {
1629 uint32 Pipe = (read32(INTEL_DISPLAY_PORT_A) & INTEL_DISP_PORTA_IVB_PIPE_MASK)
1630 >> INTEL_DISP_PORTA_IVB_PIPE_SHIFT;
1631 switch (Pipe) {
1632 case INTEL_DISP_PORTA_IVB_PIPE_A:
1633 return INTEL_PIPE_A;
1634 case INTEL_DISP_PORTA_IVB_PIPE_B:
1635 return INTEL_PIPE_B;
1636 case INTEL_DISP_PORTA_IVB_PIPE_C:
1637 return INTEL_PIPE_C;
1638 default:
1639 return INTEL_PIPE_ANY;
1640 }
1641 }
1642 return INTEL_PIPE_ANY;
1643 case INTEL_PORT_B:
1644 TranscoderPort = INTEL_TRANS_DP_PORT_B;
1645 break;
1646 case INTEL_PORT_C:
1647 TranscoderPort = INTEL_TRANS_DP_PORT_C;
1648 break;
1649 case INTEL_PORT_D:
1650 TranscoderPort = INTEL_TRANS_DP_PORT_D;
1651 break;
1652 default:
1653 return INTEL_PIPE_ANY;
1654 }
1655
1656 for (uint32 Transcoder = 0; Transcoder < 3; Transcoder++) {
1657 if ((read32(INTEL_TRANSCODER_A_DP_CTL + (Transcoder << 12)) & INTEL_TRANS_DP_PORT_MASK) ==
1658 INTEL_TRANS_DP_PORT(TranscoderPort)) {
1659 switch (Transcoder) {
1660 case 0:
1661 return INTEL_PIPE_A;
1662 case 1:
1663 return INTEL_PIPE_B;
1664 case 2:
1665 return INTEL_PIPE_C;
1666 }
1667 }
1668 }
1669
1670 return INTEL_PIPE_ANY;
1671 }
1672
1673
1674 status_t
SetPipe(Pipe * pipe)1675 DisplayPort::SetPipe(Pipe* pipe)
1676 {
1677 CALLED();
1678
1679 if (pipe == NULL) {
1680 ERROR("%s: Invalid pipe provided!\n", __PRETTY_FUNCTION__);
1681 return B_ERROR;
1682 }
1683
1684 // TODO: UnAssignPipe? This likely needs reworked a little
1685 if (fPipe != NULL) {
1686 ERROR("%s: Can't reassign display pipe (yet)\n", __PRETTY_FUNCTION__);
1687 return B_ERROR;
1688 }
1689
1690 // generation 3/4/5 gfx have no eDP ports.
1691 // generation 6 gfx SandyBridge/SNB uses one bit (b30) on the eDP port.
1692 // generation 7 gfx IvyBridge/IVB uses 2 bits (b29-30) on the eDP port.
1693 // on all other DP ports pipe selections works differently (indirect).
1694 // fixme: implement..
1695 TRACE("%s: Assuming pipe %d is assigned by BIOS to port %d (fixme)\n", __PRETTY_FUNCTION__,
1696 pipe->Index(), PortIndex());
1697
1698 fPipe = pipe;
1699
1700 if (fPipe == NULL)
1701 return B_NO_MEMORY;
1702
1703 // Disable display pipe until modesetting enables it
1704 if (fPipe->IsEnabled())
1705 fPipe->Enable(false);
1706
1707 return B_OK;
1708 }
1709
1710
1711 status_t
SetupI2c(i2c_bus * bus)1712 DisplayPort::SetupI2c(i2c_bus *bus)
1713 {
1714 CALLED();
1715
1716 const uint32 deviceConfigCount = gInfo->shared_info->device_config_count;
1717 if (gInfo->shared_info->device_type.Generation() >= 6 && deviceConfigCount > 0) {
1718 if (!_IsDisplayPortInVBT())
1719 return Port::SetupI2c(bus);
1720 }
1721
1722 return _SetupDpAuxI2c(bus);
1723 }
1724
1725
1726 bool
IsConnected()1727 DisplayPort::IsConnected()
1728 {
1729 addr_t portRegister = _PortRegister();
1730
1731 TRACE("%s: %s PortRegister: 0x%" B_PRIxADDR "\n", __func__, PortName(),
1732 portRegister);
1733
1734 if (portRegister == 0)
1735 return false;
1736
1737 const uint32 deviceConfigCount = gInfo->shared_info->device_config_count;
1738 if (gInfo->shared_info->device_type.Generation() >= 6 && deviceConfigCount > 0) {
1739 // check VBT mapping
1740 if (!_IsPortInVBT()) {
1741 TRACE("%s: %s: port not found in VBT\n", __func__, PortName());
1742 return false;
1743 } else
1744 TRACE("%s: %s: port found in VBT\n", __func__, PortName());
1745 }
1746
1747 //Notes:
1748 //- DISPLAY_MONITOR_PORT_DETECTED does only tell you *some* sort of digital display is
1749 // connected to the port *if* you have the AUX channel stuff under power. It does not
1750 // tell you which -type- of digital display is connected.
1751 //- Since we rely on the BIOS anyway, let's just use the conclusions it made for us :)
1752 // Beware though: set_display_power_mode() uses this DISPLAY_MONITOR_PORT_ENABLED bit
1753 // for DPMS as well. So we should better buffer our findings here for i.e. possible
1754 // accelerant clones starting up. For DPMS there's currently no problem as this bit
1755 // is only programmed for LVDS, DVI and VGA while we detect presence only for DP and HDMI.
1756 //
1757 //if ((read32(portRegister) & DISPLAY_MONITOR_PORT_DETECTED) == 0) {
1758 if ((read32(portRegister) & DISPLAY_MONITOR_PORT_ENABLED) == 0) {
1759 TRACE("%s: %s link not detected\n", __func__, PortName());
1760 return false;
1761 }
1762
1763 TRACE("%s: %s link detected\n", __func__, PortName());
1764 bool edidDetected = HasEDID();
1765
1766 // On laptops we always have an internal panel.. (this is on the eDP port)
1767 if ((gInfo->shared_info->device_type.IsMobile() || _IsEDPPort())
1768 && (PortIndex() == INTEL_PORT_A) && !edidDetected) {
1769 if (gInfo->shared_info->has_vesa_edid_info) {
1770 TRACE("%s: Laptop. Using VESA edid info\n", __func__);
1771 memcpy(&fEDIDInfo, &gInfo->shared_info->vesa_edid_info,
1772 sizeof(edid1_info));
1773 if (fEDIDState != B_OK) {
1774 fEDIDState = B_OK;
1775 // HasEDID now true
1776 edid_dump(&fEDIDInfo);
1777 }
1778 return true;
1779 } else if (gInfo->shared_info->got_vbt) {
1780 TRACE("%s: Laptop. No EDID, but force enabled as we have a VBT\n", __func__);
1781 return true;
1782 }
1783 }
1784
1785 //since EDID is not correctly implemented yet for this connection type we'll do without it for now
1786 //return HasEDID();
1787 return true;
1788 }
1789
1790
1791 addr_t
_DDCRegister()1792 DisplayPort::_DDCRegister()
1793 {
1794 return 0;
1795 }
1796
1797
1798 addr_t
_PortRegister()1799 DisplayPort::_PortRegister()
1800 {
1801 // There are 6000 lines of intel linux code probing DP registers
1802 // to properly detect DP vs eDP to then in-turn properly figure out
1803 // what is DP and what is HDMI. It only takes 3 lines to
1804 // ignore DisplayPort on ValleyView / CherryView
1805
1806 if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_VLV)
1807 || gInfo->shared_info->device_type.InGroup(INTEL_GROUP_CHV)) {
1808 ERROR("TODO: DisplayPort on ValleyView / CherryView");
1809 return 0;
1810 }
1811
1812 // Intel, are humans even involved anymore?
1813 // This is a lot more complex than this code makes it look. (see defines)
1814 // INTEL_DISPLAY_PORT_X moves around a lot based on PCH
1815 // except on ValleyView and CherryView.
1816 switch (PortIndex()) {
1817 case INTEL_PORT_A:
1818 return INTEL_DISPLAY_PORT_A;
1819 case INTEL_PORT_B:
1820 if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_VLV))
1821 return VLV_DISPLAY_PORT_B;
1822 return INTEL_DISPLAY_PORT_B;
1823 case INTEL_PORT_C:
1824 if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_VLV))
1825 return VLV_DISPLAY_PORT_C;
1826 return INTEL_DISPLAY_PORT_C;
1827 case INTEL_PORT_D:
1828 if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_CHV))
1829 return CHV_DISPLAY_PORT_D;
1830 else if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_VLV))
1831 return 0;
1832 return INTEL_DISPLAY_PORT_D;
1833 default:
1834 return 0;
1835 }
1836
1837 return 0;
1838 }
1839
1840
1841 status_t
_SetPortLinkGen4(const display_timing & timing)1842 DisplayPort::_SetPortLinkGen4(const display_timing& timing)
1843 {
1844 // Khz / 10. ( each output octet encoded as 10 bits.
1845 //fixme: always so?
1846 uint32 linkBandwidth = 270000; //khz
1847 uint32 fPipeOffset = 0;
1848 if (fPipe->Index() == INTEL_PIPE_B)
1849 fPipeOffset = 0x1000;
1850
1851 TRACE("%s: DP M1 data before: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_PIPE_A_DATA_M + fPipeOffset));
1852 TRACE("%s: DP N1 data before: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_PIPE_A_DATA_N + fPipeOffset));
1853 TRACE("%s: DP M1 link before: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_PIPE_A_LINK_M + fPipeOffset));
1854 TRACE("%s: DP N1 link before: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_PIPE_A_LINK_N + fPipeOffset));
1855
1856 uint32 bitsPerPixel = 24; //fixme: always so?
1857 uint32 lanes = 4; //fixme: always so?
1858
1859 //Setup Data M/N
1860 uint64 linkspeed = lanes * linkBandwidth * 8;
1861 uint64 ret_n = 1;
1862 while(ret_n < linkspeed) {
1863 ret_n *= 2;
1864 }
1865 if (ret_n > 0x800000) {
1866 ret_n = 0x800000;
1867 }
1868 uint64 ret_m = timing.pixel_clock * ret_n * bitsPerPixel / linkspeed;
1869 while ((ret_n > 0xffffff) || (ret_m > 0xffffff)) {
1870 ret_m >>= 1;
1871 ret_n >>= 1;
1872 }
1873 //Set TU size bits (to default, max) before link training so that error detection works
1874 write32(INTEL_PIPE_A_DATA_M + fPipeOffset, ret_m | FDI_PIPE_MN_TU_SIZE_MASK);
1875 write32(INTEL_PIPE_A_DATA_N + fPipeOffset, ret_n);
1876
1877 //Setup Link M/N
1878 linkspeed = linkBandwidth;
1879 ret_n = 1;
1880 while(ret_n < linkspeed) {
1881 ret_n *= 2;
1882 }
1883 if (ret_n > 0x800000) {
1884 ret_n = 0x800000;
1885 }
1886 ret_m = timing.pixel_clock * ret_n / linkspeed;
1887 while ((ret_n > 0xffffff) || (ret_m > 0xffffff)) {
1888 ret_m >>= 1;
1889 ret_n >>= 1;
1890 }
1891 write32(INTEL_PIPE_A_LINK_M + fPipeOffset, ret_m);
1892 //Writing Link N triggers all four registers to be activated also (on next VBlank)
1893 write32(INTEL_PIPE_A_LINK_N + fPipeOffset, ret_n);
1894
1895 TRACE("%s: DP M1 data after: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_PIPE_A_DATA_M + fPipeOffset));
1896 TRACE("%s: DP N1 data after: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_PIPE_A_DATA_N + fPipeOffset));
1897 TRACE("%s: DP M1 link after: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_PIPE_A_LINK_M + fPipeOffset));
1898 TRACE("%s: DP N1 link after: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_PIPE_A_LINK_N + fPipeOffset));
1899
1900 return B_OK;
1901 }
1902
1903
1904 status_t
_SetPortLinkGen6(const display_timing & timing)1905 DisplayPort::_SetPortLinkGen6(const display_timing& timing)
1906 {
1907 // Khz / 10. ( each output octet encoded as 10 bits.
1908 //note: (fixme) eDP is fixed option 162 or 270Mc, other DPs go via DPLL programming to one of the same vals.
1909 uint32 linkBandwidth = 270000; //khz
1910 TRACE("%s: DP link reference clock is %gMhz\n", __func__, linkBandwidth / 1000.0f);
1911
1912 uint32 fPipeOffset = 0;
1913 switch (fPipe->Index()) {
1914 case INTEL_PIPE_B:
1915 fPipeOffset = 0x1000;
1916 break;
1917 case INTEL_PIPE_C:
1918 fPipeOffset = 0x2000;
1919 break;
1920 default:
1921 break;
1922 }
1923
1924 TRACE("%s: DP M1 data before: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_TRANSCODER_A_DATA_M1 + fPipeOffset));
1925 TRACE("%s: DP N1 data before: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_TRANSCODER_A_DATA_N1 + fPipeOffset));
1926 TRACE("%s: DP M1 link before: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_TRANSCODER_A_LINK_M1 + fPipeOffset));
1927 TRACE("%s: DP N1 link before: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_TRANSCODER_A_LINK_N1 + fPipeOffset));
1928
1929 uint32 bitsPerPixel =
1930 (read32(INTEL_TRANSCODER_A_DP_CTL + fPipeOffset) & INTEL_TRANS_DP_BPC_MASK) >> INTEL_TRANS_DP_COLOR_SHIFT;
1931 switch (bitsPerPixel) {
1932 case PIPE_DDI_8BPC:
1933 bitsPerPixel = 24;
1934 break;
1935 case PIPE_DDI_10BPC:
1936 bitsPerPixel = 30;
1937 break;
1938 case PIPE_DDI_6BPC:
1939 bitsPerPixel = 18;
1940 break;
1941 case PIPE_DDI_12BPC:
1942 bitsPerPixel = 36;
1943 break;
1944 default:
1945 ERROR("%s: DP illegal link colordepth set.\n", __func__);
1946 return B_ERROR;
1947 }
1948 TRACE("%s: DP link colordepth: %" B_PRIu32 "\n", __func__, bitsPerPixel);
1949
1950 uint32 lanes = ((read32(_PortRegister()) & INTEL_DISP_PORT_WIDTH_MASK) >> INTEL_DISP_PORT_WIDTH_SHIFT) + 1;
1951 if (lanes > 4) {
1952 ERROR("%s: DP illegal number of lanes set.\n", __func__);
1953 return B_ERROR;
1954 }
1955 TRACE("%s: DP mode with %" B_PRIx32 " lane(s) in use\n", __func__, lanes);
1956
1957 //Reserving 5% bandwidth for possible spread spectrum clock use
1958 uint32 bps = timing.pixel_clock * bitsPerPixel * 21 / 20;
1959 //use DIV_ROUND_UP:
1960 uint32 required_lanes = (bps + (linkBandwidth * 8) - 1) / (linkBandwidth * 8);
1961 TRACE("%s: DP mode needs %" B_PRIx32 " lane(s) in use\n", __func__, required_lanes);
1962 if (required_lanes > lanes) {
1963 //Note that we *must* abort as otherwise the PIPE/DP-link hangs forever (without retraining!).
1964 ERROR("%s: DP not enough lanes active for requested mode.\n", __func__);
1965 return B_ERROR;
1966 }
1967
1968 //Setup Data M/N
1969 uint64 linkspeed = lanes * linkBandwidth * 8;
1970 uint64 ret_n = 1;
1971 while(ret_n < linkspeed) {
1972 ret_n *= 2;
1973 }
1974 if (ret_n > 0x800000) {
1975 ret_n = 0x800000;
1976 }
1977 uint64 ret_m = timing.pixel_clock * ret_n * bitsPerPixel / linkspeed;
1978 while ((ret_n > 0xffffff) || (ret_m > 0xffffff)) {
1979 ret_m >>= 1;
1980 ret_n >>= 1;
1981 }
1982 //Set TU size bits (to default, max) before link training so that error detection works
1983 write32(INTEL_TRANSCODER_A_DATA_M1 + fPipeOffset, ret_m | INTEL_TRANSCODER_MN_TU_SIZE_MASK);
1984 write32(INTEL_TRANSCODER_A_DATA_N1 + fPipeOffset, ret_n);
1985
1986 //Setup Link M/N
1987 linkspeed = linkBandwidth;
1988 ret_n = 1;
1989 while(ret_n < linkspeed) {
1990 ret_n *= 2;
1991 }
1992 if (ret_n > 0x800000) {
1993 ret_n = 0x800000;
1994 }
1995 ret_m = timing.pixel_clock * ret_n / linkspeed;
1996 while ((ret_n > 0xffffff) || (ret_m > 0xffffff)) {
1997 ret_m >>= 1;
1998 ret_n >>= 1;
1999 }
2000 write32(INTEL_TRANSCODER_A_LINK_M1 + fPipeOffset, ret_m);
2001 //Writing Link N triggers all four registers to be activated also (on next VBlank)
2002 write32(INTEL_TRANSCODER_A_LINK_N1 + fPipeOffset, ret_n);
2003
2004 TRACE("%s: DP M1 data after: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_TRANSCODER_A_DATA_M1 + fPipeOffset));
2005 TRACE("%s: DP N1 data after: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_TRANSCODER_A_DATA_N1 + fPipeOffset));
2006 TRACE("%s: DP M1 link after: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_TRANSCODER_A_LINK_M1 + fPipeOffset));
2007 TRACE("%s: DP N1 link after: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_TRANSCODER_A_LINK_N1 + fPipeOffset));
2008
2009 return B_OK;
2010 }
2011
2012
2013 status_t
SetDisplayMode(display_mode * target,uint32 colorMode)2014 DisplayPort::SetDisplayMode(display_mode* target, uint32 colorMode)
2015 {
2016 CALLED();
2017 TRACE("%s: %s %dx%d\n", __func__, PortName(), target->timing.h_display,
2018 target->timing.v_display);
2019
2020 if (fPipe == NULL) {
2021 ERROR("%s: Setting display mode without assigned pipe!\n", __func__);
2022 return B_ERROR;
2023 }
2024
2025 status_t result = B_OK;
2026 if (gInfo->shared_info->device_type.Generation() <= 4) {
2027 fPipe->ConfigureTimings(target);
2028 result = _SetPortLinkGen4(target->timing);
2029 } else {
2030 display_timing hardwareTarget = target->timing;
2031 bool needsScaling = false;
2032 if ((PortIndex() == INTEL_PORT_A)
2033 && (gInfo->shared_info->device_type.IsMobile() || _IsEDPPort())) {
2034 // For internal panels, we may need to set the timings according to the panel
2035 // native video mode, and let the panel fitter do the scaling.
2036 // note: upto/including generation 5 laptop panels are still LVDS types, handled elsewhere.
2037
2038 if (gInfo->shared_info->got_vbt) {
2039 // Set vbios hardware panel mode as base
2040 hardwareTarget = gInfo->shared_info->panel_timing;
2041
2042 if (hardwareTarget.h_display == target->timing.h_display
2043 && hardwareTarget.v_display == target->timing.v_display) {
2044 // We are feeding the native video mode, nothing to do: disable scaling
2045 TRACE("%s: Requested mode is panel's native resolution: disabling scaling\n", __func__);
2046 } else {
2047 // We need to enable the panel fitter
2048 TRACE("%s: Requested mode is not panel's native resolution: enabling scaling\n", __func__);
2049 needsScaling = true;
2050 }
2051 } else {
2052 //fixme: We should now first try for EDID info detailed timing, highest res in list: that's the
2053 //native mode as well. If we also have no EDID, then fallback to setting mode directly as below.
2054
2055 TRACE("%s: Setting internal panel mode without VBT info generation, scaling may not work\n",
2056 __func__);
2057 // We don't have VBT data, try to set the requested mode directly
2058 // and hope for the best
2059 hardwareTarget = target->timing;
2060 }
2061 }
2062
2063 result = B_OK;
2064 if (PortIndex() != INTEL_PORT_A)
2065 result = _SetPortLinkGen6(hardwareTarget);
2066
2067 if (result == B_OK) {
2068 // Setup PanelFitter and Train FDI if it exists
2069 PanelFitter* fitter = fPipe->PFT();
2070 if (fitter != NULL)
2071 fitter->Enable(hardwareTarget);
2072
2073 uint32 lanes = 0;
2074 uint32 linkBandwidth = 0;
2075 uint32 bitsPerPixel = 0;
2076 if (PortIndex() != INTEL_PORT_A) {
2077 FDILink* link = fPipe->FDI();
2078 if (link != NULL) {
2079 link->PreTrain(&hardwareTarget, &linkBandwidth, &lanes, &bitsPerPixel);
2080 fPipe->SetFDILink(hardwareTarget, linkBandwidth, lanes, bitsPerPixel);
2081 link->Train(&hardwareTarget, lanes);
2082 }
2083 } else {
2084 // 'local' eDP port is in use
2085 linkBandwidth =
2086 (read32(INTEL_DISPLAY_PORT_A) & INTEL_DISP_EDP_PLL_FREQ_MASK) >> INTEL_DISP_EDP_PLL_FREQ_SHIFT;
2087 switch (linkBandwidth) {
2088 case INTEL_DISP_EDP_PLL_FREQ_270:
2089 linkBandwidth = 270000; //khz
2090 break;
2091 case INTEL_DISP_EDP_PLL_FREQ_162:
2092 linkBandwidth = 162000; //khz
2093 break;
2094 default:
2095 TRACE("%s: eDP illegal reference clock ID set, assuming 270Mhz.\n", __func__);
2096 linkBandwidth = 270000; //khz
2097 }
2098
2099 bitsPerPixel =
2100 (read32(INTEL_DISPLAY_A_PIPE_CONTROL) & INTEL_PIPE_BPC_MASK) >> INTEL_PIPE_COLOR_SHIFT;
2101 switch (bitsPerPixel) {
2102 case INTEL_PIPE_8BPC:
2103 bitsPerPixel = 24;
2104 break;
2105 case INTEL_PIPE_10BPC:
2106 bitsPerPixel = 30;
2107 break;
2108 case INTEL_PIPE_6BPC:
2109 bitsPerPixel = 18;
2110 break;
2111 case INTEL_PIPE_12BPC:
2112 bitsPerPixel = 36;
2113 break;
2114 default:
2115 bitsPerPixel = 0;
2116 }
2117
2118 lanes =
2119 ((read32(INTEL_DISPLAY_PORT_A) & INTEL_DISP_PORT_WIDTH_MASK) >> INTEL_DISP_PORT_WIDTH_SHIFT) + 1;
2120
2121 fPipe->SetFDILink(hardwareTarget, linkBandwidth, lanes, bitsPerPixel);
2122 }
2123
2124 // Program general pipe config
2125 fPipe->Configure(target);
2126
2127 // Pll programming is not needed for (e)DP..
2128
2129 // Program target display mode
2130 fPipe->ConfigureTimings(target, !needsScaling, PortIndex());
2131 } else {
2132 TRACE("%s: Setting display mode via fallback: using scaling!\n", __func__);
2133 // Keep monitor at native mode and scale image to that
2134 fPipe->ConfigureScalePos(target);
2135 }
2136 }
2137
2138 // Set fCurrentMode to our set display mode
2139 memcpy(&fCurrentMode, target, sizeof(display_mode));
2140
2141 return result;
2142 }
2143
2144
2145 // #pragma mark - Embedded DisplayPort
2146
2147
EmbeddedDisplayPort()2148 EmbeddedDisplayPort::EmbeddedDisplayPort()
2149 :
2150 DisplayPort(INTEL_PORT_A, "Embedded DisplayPort")
2151 {
2152 }
2153
2154
2155 bool
IsConnected()2156 EmbeddedDisplayPort::IsConnected()
2157 {
2158 addr_t portRegister = _PortRegister();
2159
2160 TRACE("%s: %s PortRegister: 0x%" B_PRIxADDR "\n", __func__, PortName(),
2161 portRegister);
2162
2163 if (!gInfo->shared_info->device_type.IsMobile()) {
2164 TRACE("%s: skipping eDP on non-mobile GPU\n", __func__);
2165 return false;
2166 }
2167
2168 if ((read32(portRegister) & DISPLAY_MONITOR_PORT_DETECTED) == 0) {
2169 TRACE("%s: %s link not detected\n", __func__, PortName());
2170 return false;
2171 }
2172
2173 HasEDID();
2174
2175 // If eDP has EDID, awesome. We use it.
2176 // No EDID? The modesetting code falls back to VBIOS panel_mode
2177 return true;
2178 }
2179
2180
2181 // #pragma mark - Digital Display Port
2182
2183
DigitalDisplayInterface(port_index index,const char * baseName)2184 DigitalDisplayInterface::DigitalDisplayInterface(port_index index,
2185 const char* baseName)
2186 :
2187 Port(index, baseName)
2188 {
2189 // As of Haswell, Intel decided to change eDP ports to a "DDI" bus...
2190 // on a dare because the hardware engineers were drunk one night.
2191 }
2192
2193
2194 addr_t
_PortRegister()2195 DigitalDisplayInterface::_PortRegister()
2196 {
2197 // TODO: Linux does a DDI_BUF_CTL(INTEL_PORT_A) which is cleaner
2198 // (but we have to ensure the offsets + region base is correct)
2199 switch (PortIndex()) {
2200 case INTEL_PORT_A:
2201 return DDI_BUF_CTL_A;
2202 case INTEL_PORT_B:
2203 return DDI_BUF_CTL_B;
2204 case INTEL_PORT_C:
2205 return DDI_BUF_CTL_C;
2206 case INTEL_PORT_D:
2207 return DDI_BUF_CTL_D;
2208 case INTEL_PORT_E:
2209 return DDI_BUF_CTL_E;
2210 case INTEL_PORT_F:
2211 if ((gInfo->shared_info->device_type.Generation() > 8) &&
2212 !gInfo->shared_info->device_type.InGroup(INTEL_GROUP_SKY))
2213 return DDI_BUF_CTL_F;
2214 return 0;
2215 case INTEL_PORT_G:
2216 if (gInfo->shared_info->device_type.Generation() >= 12)
2217 return DDI_BUF_CTL_G;
2218 return 0;
2219 default:
2220 return 0;
2221 }
2222 return 0;
2223 }
2224
2225
2226 addr_t
_DDCRegister()2227 DigitalDisplayInterface::_DDCRegister()
2228 {
2229 return Port::_DDCPin();
2230 }
2231
2232
2233 status_t
Power(bool enabled)2234 DigitalDisplayInterface::Power(bool enabled)
2235 {
2236 if (fPipe == NULL) {
2237 ERROR("%s: Setting power without assigned pipe!\n", __func__);
2238 return B_ERROR;
2239 }
2240 TRACE("%s: %s DDI enabled: %s\n", __func__, PortName(),
2241 enabled ? "true" : "false");
2242
2243 fPipe->Enable(enabled);
2244
2245 //nogo currently.. (kills output forever)
2246 #if 0
2247 addr_t portRegister = _PortRegister();
2248 uint32 state = read32(portRegister);
2249 write32(portRegister,
2250 enabled ? (state | DDI_BUF_CTL_ENABLE) : (state & ~DDI_BUF_CTL_ENABLE));
2251 read32(portRegister);
2252 #endif
2253
2254 return B_OK;
2255 }
2256
2257
2258 status_t
SetPipe(Pipe * pipe)2259 DigitalDisplayInterface::SetPipe(Pipe* pipe)
2260 {
2261 CALLED();
2262
2263 if (pipe == NULL) {
2264 ERROR("%s: Invalid pipe provided!\n", __PRETTY_FUNCTION__);
2265 return B_ERROR;
2266 }
2267
2268 // TODO: UnAssignPipe? This likely needs reworked a little
2269 if (fPipe != NULL) {
2270 ERROR("%s: Can't reassign display pipe (yet)\n", __PRETTY_FUNCTION__);
2271 return B_ERROR;
2272 }
2273
2274 // all DDI ports pipe selections works differently than on the old port types (indirect).
2275 // fixme: implement..
2276 TRACE("%s: Assuming pipe %d is assigned by BIOS to port %d (fixme)\n", __PRETTY_FUNCTION__,
2277 pipe->Index(), PortIndex());
2278
2279 fPipe = pipe;
2280
2281 if (fPipe == NULL)
2282 return B_NO_MEMORY;
2283
2284 // Disable display pipe until modesetting enables it
2285 if (fPipe->IsEnabled())
2286 fPipe->Enable(false);
2287
2288 return B_OK;
2289 }
2290
2291
2292 status_t
SetupI2c(i2c_bus * bus)2293 DigitalDisplayInterface::SetupI2c(i2c_bus *bus)
2294 {
2295 CALLED();
2296
2297 const uint32 deviceConfigCount = gInfo->shared_info->device_config_count;
2298 if (gInfo->shared_info->device_type.Generation() >= 6 && deviceConfigCount > 0) {
2299 if (!_IsDisplayPortInVBT())
2300 return Port::SetupI2c(bus);
2301 }
2302
2303 return _SetupDpAuxI2c(bus);
2304 }
2305
2306
2307 status_t
SetupI2cFallback(i2c_bus * bus)2308 DigitalDisplayInterface::SetupI2cFallback(i2c_bus *bus)
2309 {
2310 CALLED();
2311
2312 const uint32 deviceConfigCount = gInfo->shared_info->device_config_count;
2313 if (gInfo->shared_info->device_type.Generation() >= 6 && deviceConfigCount > 0
2314 && _IsDisplayPortInVBT() && _IsHdmiInVBT()) {
2315 return Port::SetupI2c(bus);
2316 }
2317
2318 return B_ERROR;
2319 }
2320
2321
2322 bool
IsConnected()2323 DigitalDisplayInterface::IsConnected()
2324 {
2325 addr_t portRegister = _PortRegister();
2326
2327 TRACE("%s: %s PortRegister: 0x%" B_PRIxADDR "\n", __func__, PortName(),
2328 portRegister);
2329
2330 // Please note: Skylake and up (Desktop) might use eDP for a seperate active VGA converter chip.
2331 if (portRegister == 0) {
2332 TRACE("%s: Port not implemented\n", __func__);
2333 return false;
2334 }
2335
2336 // newer chipsets support 4 lanes on all ports
2337 fMaxLanes = 4;
2338 if ((gInfo->shared_info->device_type.Generation() < 9) ||
2339 gInfo->shared_info->device_type.InGroup(INTEL_GROUP_SKY)) {
2340 // Probe a little port info.
2341 if ((read32(DDI_BUF_CTL_A) & DDI_A_4_LANES) != 0) {
2342 switch (PortIndex()) {
2343 case INTEL_PORT_A:
2344 fMaxLanes = 4;
2345 break;
2346 case INTEL_PORT_E:
2347 fMaxLanes = 0;
2348 break;
2349 default:
2350 fMaxLanes = 4;
2351 break;
2352 }
2353 } else {
2354 switch (PortIndex()) {
2355 case INTEL_PORT_A:
2356 fMaxLanes = 2;
2357 break;
2358 case INTEL_PORT_E:
2359 fMaxLanes = 2;
2360 break;
2361 default:
2362 fMaxLanes = 4;
2363 break;
2364 }
2365 }
2366 }
2367
2368 const uint32 deviceConfigCount = gInfo->shared_info->device_config_count;
2369 if (gInfo->shared_info->device_type.Generation() >= 6 && deviceConfigCount > 0) {
2370 // check VBT mapping
2371 if (!_IsPortInVBT()) {
2372 TRACE("%s: %s: port not found in VBT\n", __func__, PortName());
2373 return false;
2374 } else
2375 TRACE("%s: %s: port found in VBT\n", __func__, PortName());
2376 }
2377
2378 TRACE("%s: %s Maximum Lanes: %" B_PRId8 "\n", __func__,
2379 PortName(), fMaxLanes);
2380
2381 // fetch EDID but determine 'in use' later (below) so we also catch screens that fail EDID
2382 bool edidDetected = HasEDID();
2383
2384 // On laptops we always have an internal panel.. (on the eDP port on DDI systems, fixed on eDP pipe)
2385 uint32 pipeState = 0;
2386 if ((gInfo->shared_info->device_type.IsMobile() || _IsEDPPort())
2387 && (PortIndex() == INTEL_PORT_A)) {
2388 if (gInfo->shared_info->device_type.Generation() < 12) {
2389 // TODO: the pipe state isn't reliable after gen11
2390 pipeState = read32(PIPE_DDI_FUNC_CTL_EDP);
2391 TRACE("%s: PIPE_DDI_FUNC_CTL_EDP: 0x%" B_PRIx32 "\n", __func__, pipeState);
2392 if (!(pipeState & PIPE_DDI_FUNC_CTL_ENABLE)) {
2393 TRACE("%s: Laptop, but eDP port down\n", __func__);
2394 return false;
2395 }
2396 }
2397 if (edidDetected)
2398 return true;
2399 else if (gInfo->shared_info->has_vesa_edid_info) {
2400 TRACE("%s: Laptop. Using VESA edid info\n", __func__);
2401 memcpy(&fEDIDInfo, &gInfo->shared_info->vesa_edid_info, sizeof(edid1_info));
2402 if (fEDIDState != B_OK) {
2403 fEDIDState = B_OK;
2404 // HasEDID now true
2405 edid_dump(&fEDIDInfo);
2406 }
2407 return true;
2408 } else if (gInfo->shared_info->got_vbt) {
2409 TRACE("%s: Laptop. No VESA EDID, but force enabled as we have a VBT\n", __func__);
2410 return true;
2411 }
2412 //should not happen:
2413 TRACE("%s: No (panel) type info found, assuming not connected\n", __func__);
2414 return false;
2415 }
2416
2417 // scan all our non-eDP pipes to find the one connected to the current port and check it's enabled
2418 for (uint32 pipeCnt = 0; pipeCnt < 3; pipeCnt++) {
2419 switch (pipeCnt) {
2420 case 1:
2421 pipeState = read32(PIPE_DDI_FUNC_CTL_B);
2422 break;
2423 case 2:
2424 pipeState = read32(PIPE_DDI_FUNC_CTL_C);
2425 break;
2426 default:
2427 pipeState = read32(PIPE_DDI_FUNC_CTL_A);
2428 break;
2429 }
2430 if ((((pipeState & PIPE_DDI_SELECT_MASK) >> PIPE_DDI_SELECT_SHIFT) + 1) == (uint32)PortIndex()) {
2431 TRACE("%s: PIPE_DDI_FUNC_CTL nr %" B_PRIx32 ": 0x%" B_PRIx32 "\n", __func__, pipeCnt + 1, pipeState);
2432 // See if the BIOS enabled our output as it indicates it's in use
2433 if (pipeState & PIPE_DDI_FUNC_CTL_ENABLE) {
2434 TRACE("%s: Connected\n", __func__);
2435 return true;
2436 }
2437 }
2438 }
2439
2440 if (edidDetected) {
2441 for (uint32 pipeCnt = 0; pipeCnt < 3; pipeCnt++) {
2442 uint32 pipeReg = 0;
2443 switch (pipeCnt) {
2444 case 1:
2445 pipeReg = PIPE_DDI_FUNC_CTL_B;
2446 break;
2447 case 2:
2448 pipeReg = PIPE_DDI_FUNC_CTL_C;
2449 break;
2450 default:
2451 pipeReg = PIPE_DDI_FUNC_CTL_A;
2452 break;
2453 }
2454 pipeState = read32(pipeReg);
2455 if ((pipeState & PIPE_DDI_FUNC_CTL_ENABLE) == 0) {
2456 TRACE("%s: Connected but port down\n", __func__);
2457 return false;
2458 }
2459 return true;
2460 }
2461 TRACE("%s: No pipe available, ignoring connected screen\n", __func__);
2462 }
2463
2464 TRACE("%s: Not connected\n", __func__);
2465 return false;
2466 }
2467
2468 status_t
_SetPortLinkGen8(const display_timing & timing,uint32 pllSel)2469 DigitalDisplayInterface::_SetPortLinkGen8(const display_timing& timing, uint32 pllSel)
2470 {
2471 //fixme: always so on pre gen 9?
2472 uint32 linkBandwidth = 270000; //khz
2473
2474 if (gInfo->shared_info->device_type.Generation() >= 11) {
2475 ERROR("%s: DDI PLL selection not implemented for Gen11, "
2476 "assuming default DP-link reference\n", __func__);
2477 } else if (gInfo->shared_info->device_type.Generation() >= 9) {
2478 if (pllSel != 0xff) {
2479 linkBandwidth = (read32(SKL_DPLL_CTRL1) >> (1 + 6 * pllSel)) & SKL_DPLL_DP_LINKRATE_MASK;
2480 switch (linkBandwidth) {
2481 case SKL_DPLL_CTRL1_2700:
2482 linkBandwidth = 2700000 / 5;
2483 break;
2484 case SKL_DPLL_CTRL1_1350:
2485 linkBandwidth = 1350000 / 5;
2486 break;
2487 case SKL_DPLL_CTRL1_810:
2488 linkBandwidth = 810000 / 5;
2489 break;
2490 case SKL_DPLL_CTRL1_1620:
2491 linkBandwidth = 1620000 / 5;
2492 break;
2493 case SKL_DPLL_CTRL1_1080:
2494 linkBandwidth = 1080000 / 5;
2495 break;
2496 case SKL_DPLL_CTRL1_2160:
2497 linkBandwidth = 2160000 / 5;
2498 break;
2499 default:
2500 linkBandwidth = 270000;
2501 ERROR("%s: DDI No known DP-link reference clock selected, assuming default\n", __func__);
2502 break;
2503 }
2504 } else {
2505 ERROR("%s: DDI No known PLL selected, assuming default DP-link reference\n", __func__);
2506 }
2507 }
2508 TRACE("%s: DDI DP-link reference clock is %gMhz\n", __func__, linkBandwidth / 1000.0f);
2509
2510 uint32 fPipeOffset = 0;
2511 switch (fPipe->Index()) {
2512 case INTEL_PIPE_B:
2513 fPipeOffset = 0x1000;
2514 break;
2515 case INTEL_PIPE_C:
2516 fPipeOffset = 0x2000;
2517 break;
2518 case INTEL_PIPE_D:
2519 fPipeOffset = 0xf000;
2520 break;
2521 default:
2522 break;
2523 }
2524
2525 TRACE("%s: DDI M1 data before: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_DDI_PIPE_A_DATA_M + fPipeOffset));
2526 TRACE("%s: DDI N1 data before: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_DDI_PIPE_A_DATA_N + fPipeOffset));
2527 TRACE("%s: DDI M1 link before: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_DDI_PIPE_A_LINK_M + fPipeOffset));
2528 TRACE("%s: DDI N1 link before: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_DDI_PIPE_A_LINK_N + fPipeOffset));
2529
2530 uint32 pipeFunc = read32(PIPE_DDI_FUNC_CTL_A + fPipeOffset);
2531 uint32 bitsPerPixel = (pipeFunc & PIPE_DDI_BPC_MASK) >> PIPE_DDI_COLOR_SHIFT;
2532 switch (bitsPerPixel) {
2533 case PIPE_DDI_8BPC:
2534 bitsPerPixel = 24;
2535 break;
2536 case PIPE_DDI_10BPC:
2537 bitsPerPixel = 30;
2538 break;
2539 case PIPE_DDI_6BPC:
2540 bitsPerPixel = 18;
2541 break;
2542 case PIPE_DDI_12BPC:
2543 bitsPerPixel = 36;
2544 break;
2545 default:
2546 ERROR("%s: DDI illegal link colordepth set.\n", __func__);
2547 return B_ERROR;
2548 }
2549 TRACE("%s: DDI Link Colordepth: %" B_PRIu32 "\n", __func__, bitsPerPixel);
2550
2551 uint32 lanes = 4;
2552 // Only DP modes supports less than 4 lanes: read current config
2553 if (((pipeFunc & PIPE_DDI_MODESEL_MASK) >> PIPE_DDI_MODESEL_SHIFT) >= PIPE_DDI_MODE_DP_SST) {
2554 // On gen 9.5 IceLake 3x mode exists (DSI only), earlier models: reserved value.
2555 lanes = ((pipeFunc & PIPE_DDI_DP_WIDTH_MASK) >> PIPE_DDI_DP_WIDTH_SHIFT) + 1;
2556 TRACE("%s: DDI in DP mode with %" B_PRIx32 " lane(s) in use\n", __func__, lanes);
2557 } else {
2558 TRACE("%s: DDI in non-DP mode with %" B_PRIx32 " lane(s) in use\n", __func__, lanes);
2559 }
2560
2561 //Setup Data M/N
2562 uint64 linkspeed = lanes * linkBandwidth * 8;
2563 uint64 ret_n = 1;
2564 while(ret_n < linkspeed) {
2565 ret_n *= 2;
2566 }
2567 if (ret_n > 0x800000) {
2568 ret_n = 0x800000;
2569 }
2570 uint64 ret_m = timing.pixel_clock * ret_n * bitsPerPixel / linkspeed;
2571 while ((ret_n > 0xffffff) || (ret_m > 0xffffff)) {
2572 ret_m >>= 1;
2573 ret_n >>= 1;
2574 }
2575 //Set TU size bits (to default, max) before link training so that error detection works
2576 write32(INTEL_DDI_PIPE_A_DATA_M + fPipeOffset, ret_m | FDI_PIPE_MN_TU_SIZE_MASK);
2577 write32(INTEL_DDI_PIPE_A_DATA_N + fPipeOffset, ret_n);
2578
2579 //Setup Link M/N
2580 linkspeed = linkBandwidth;
2581 ret_n = 1;
2582 while(ret_n < linkspeed) {
2583 ret_n *= 2;
2584 }
2585 if (ret_n > 0x800000) {
2586 ret_n = 0x800000;
2587 }
2588 ret_m = timing.pixel_clock * ret_n / linkspeed;
2589 while ((ret_n > 0xffffff) || (ret_m > 0xffffff)) {
2590 ret_m >>= 1;
2591 ret_n >>= 1;
2592 }
2593 write32(INTEL_DDI_PIPE_A_LINK_M + fPipeOffset, ret_m);
2594 //Writing Link N triggers all four registers to be activated also (on next VBlank)
2595 write32(INTEL_DDI_PIPE_A_LINK_N + fPipeOffset, ret_n);
2596
2597 TRACE("%s: DDI M1 data after: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_DDI_PIPE_A_DATA_M + fPipeOffset));
2598 TRACE("%s: DDI N1 data after: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_DDI_PIPE_A_DATA_N + fPipeOffset));
2599 TRACE("%s: DDI M1 link after: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_DDI_PIPE_A_LINK_M + fPipeOffset));
2600 TRACE("%s: DDI N1 link after: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_DDI_PIPE_A_LINK_N + fPipeOffset));
2601
2602 return B_OK;
2603 }
2604
2605 status_t
SetDisplayMode(display_mode * target,uint32 colorMode)2606 DigitalDisplayInterface::SetDisplayMode(display_mode* target, uint32 colorMode)
2607 {
2608 CALLED();
2609 TRACE("%s: %s %dx%d\n", __func__, PortName(), target->timing.h_display,
2610 target->timing.v_display);
2611
2612 if (fPipe == NULL) {
2613 ERROR("%s: Setting display mode without assigned pipe!\n", __func__);
2614 return B_ERROR;
2615 }
2616
2617 display_timing hardwareTarget = target->timing;
2618 bool needsScaling = false;
2619 if ((PortIndex() == INTEL_PORT_A)
2620 && (gInfo->shared_info->device_type.IsMobile() || _IsEDPPort())) {
2621 // For internal panels, we may need to set the timings according to the panel
2622 // native video mode, and let the panel fitter do the scaling.
2623
2624 if (gInfo->shared_info->got_vbt || HasEDID()) {
2625 // Set vbios hardware panel mode as base
2626 hardwareTarget = gInfo->shared_info->panel_timing;
2627 if (HasEDID()) {
2628 // the first detailed timing supposed to be the best supported one
2629 int i;
2630 for (i = 0; i < EDID1_NUM_DETAILED_MONITOR_DESC; ++i) {
2631 edid1_detailed_monitor *monitor = &fEDIDInfo.detailed_monitor[i];
2632 if (monitor->monitor_desc_type == EDID1_IS_DETAILED_TIMING)
2633 break;
2634 }
2635 if (i < EDID1_NUM_DETAILED_MONITOR_DESC) {
2636 TRACE("%s: Using EDID detailed timing %d for the internal panel\n",
2637 __func__, i);
2638 const edid1_detailed_timing& timing
2639 = fEDIDInfo.detailed_monitor[i].data.detailed_timing;
2640 hardwareTarget.pixel_clock = timing.pixel_clock * 10;
2641 hardwareTarget.h_display = timing.h_active;
2642 hardwareTarget.h_sync_start = timing.h_active + timing.h_sync_off;
2643 hardwareTarget.h_sync_end = hardwareTarget.h_sync_start + timing.h_sync_width;
2644 hardwareTarget.h_total = timing.h_active + timing.h_blank;
2645 hardwareTarget.v_display = timing.v_active;
2646 hardwareTarget.v_sync_start = timing.v_active + timing.v_sync_off;
2647 hardwareTarget.v_sync_end = hardwareTarget.v_sync_start + timing.v_sync_width;
2648 hardwareTarget.v_total = timing.v_active + timing.v_blank;
2649 hardwareTarget.flags = 0;
2650 if (timing.sync == 3) {
2651 if (timing.misc & 1)
2652 hardwareTarget.flags |= B_POSITIVE_HSYNC;
2653 if (timing.misc & 2)
2654 hardwareTarget.flags |= B_POSITIVE_VSYNC;
2655 }
2656 if (timing.interlaced)
2657 hardwareTarget.flags |= B_TIMING_INTERLACED;
2658 }
2659 }
2660 if (hardwareTarget.h_display == target->timing.h_display
2661 && hardwareTarget.v_display == target->timing.v_display) {
2662 // We are setting the native video mode, nothing special to do
2663 // Note: this means refresh and timing might vary according to requested mode.
2664 hardwareTarget = target->timing;
2665 TRACE("%s: Setting internal panel to native resolution at %" B_PRIu32 "Hz\n", __func__,
2666 hardwareTarget.pixel_clock * 1000 / (hardwareTarget.h_total * hardwareTarget.v_total));
2667 } else {
2668 // We need to enable the panel fitter
2669 TRACE("%s: Hardware mode will actually be %dx%d at %" B_PRIu32 "Hz\n", __func__,
2670 hardwareTarget.h_display, hardwareTarget.v_display,
2671 hardwareTarget.pixel_clock * 1000 / (hardwareTarget.h_total * hardwareTarget.v_total));
2672
2673 // FIXME we should also get the refresh frequency from the target
2674 // mode, and then "sanitize" the resulting mode we made up.
2675 needsScaling = true;
2676 }
2677 } else {
2678 TRACE("%s: Setting internal panel mode without VBT info generation, scaling may not work\n",
2679 __func__);
2680 // We don't have VBT data, try to set the requested mode directly
2681 // and hope for the best
2682 hardwareTarget = target->timing;
2683 }
2684 }
2685
2686 // Setup PanelFitter
2687 PanelFitter* fitter = fPipe->PFT();
2688 if (fitter != NULL)
2689 fitter->Enable(hardwareTarget);
2690
2691 // skip FDI as it never applies to DDI (on gen7 and 8 only for the real analog VGA port)
2692
2693 // Program general pipe config
2694 fPipe->Configure(target);
2695
2696 // TODO create a PLL class that can abstract the details of setting up the clock generation,
2697 // and instanciate the correct type depending on the card generation
2698 uint32 pllSel = 0xff; // no PLL selected
2699 if (gInfo->shared_info->device_type.Generation() <= 8) {
2700 unsigned int r2_out, n2_out, p_out;
2701 hsw_ddi_calculate_wrpll(
2702 hardwareTarget.pixel_clock * 1000 /* in Hz */,
2703 &r2_out, &n2_out, &p_out);
2704 // TODO the computed PLL values are not used for anything?
2705 } else if (gInfo->shared_info->device_type.Generation() <= 11) {
2706 skl_wrpll_params wrpll_params;
2707 skl_ddi_calculate_wrpll(
2708 hardwareTarget.pixel_clock * 1000 /* in Hz */,
2709 gInfo->shared_info->pll_info.reference_frequency,
2710 &wrpll_params);
2711 fPipe->ConfigureClocksSKL(wrpll_params,
2712 hardwareTarget.pixel_clock,
2713 PortIndex(),
2714 &pllSel);
2715 } else {
2716 // Tiger Lake
2717 // See volume 12, page 180, "HDMI Mode Combo PHY Programming"
2718 int p, q, k;
2719 float dco;
2720 uint32 mode = fPipe->TranscoderMode();
2721 if ((mode == PIPE_DDI_MODE_DVI || mode == PIPE_DDI_MODE_HDMI)
2722 && ComputeHdmiDpll(hardwareTarget.pixel_clock, &p, &q, &k, &dco)) {
2723 TRACE("PLL settings: DCO=%f, P,Q,K=%d,%d,%d\n", dco, p, q, k);
2724 } else if ((mode == PIPE_DDI_MODE_DP_SST || mode == PIPE_DDI_MODE_DP_MST)
2725 && ComputeDisplayPortDpll(hardwareTarget.pixel_clock, &p, &q, &k, &dco)) {
2726 TRACE("PLL settings: DCO=%f, P,Q,K=%d,%d,%d\n", dco, p, q, k);
2727 } else {
2728 ERROR("%s: Could not find a matching PLL setting\n", __func__);
2729 return B_ERROR;
2730 }
2731
2732 // TODO write a proper way to assign PLLs to pipes and ports.
2733 int chosenPLL = 0;
2734 if (PortIndex() == 7)
2735 chosenPLL = 1;
2736 TRACE("Using DPLL %d for port %d. PLL settings: DCO=%f, P,Q,K=%d,%d,%d\n", chosenPLL,
2737 PortIndex(), dco, p, q, k);
2738 ProgramPLL(chosenPLL, p, q, k, dco);
2739
2740 // Configure DPLL mapping to port then turn on DPLL clock
2741 uint32 config = read32(TGL_DPCLKA_CFGCR0);
2742 TRACE("PLL configuration before changes: %" B_PRIx32 "\n", config);
2743 if (chosenPLL == 0) {
2744 config |= TGL_DPCLKA_DDIA_CLOCK_OFF;
2745 config &= TGL_DPCLKA_DDIA_CLOCK_SELECT;
2746 write32(TGL_DPCLKA_CFGCR0, config);
2747 config &= ~TGL_DPCLKA_DDIA_CLOCK_OFF;
2748 write32(TGL_DPCLKA_CFGCR0, config);
2749 } else {
2750 config |= TGL_DPCLKA_DDIB_CLOCK_OFF;
2751 config &= TGL_DPCLKA_DDIB_CLOCK_SELECT;
2752 config |= 1 << TGL_DPCLKA_DDIB_CLOCK_SELECT_SHIFT;
2753 write32(TGL_DPCLKA_CFGCR0, config);
2754 config &= ~TGL_DPCLKA_DDIB_CLOCK_OFF;
2755 write32(TGL_DPCLKA_CFGCR0, config);
2756 }
2757 TRACE("PLL configuration after changes: %" B_PRIx32 "\n", config);
2758 }
2759
2760 // Program target display mode
2761 fPipe->ConfigureTimings(target, !needsScaling);
2762 _SetPortLinkGen8(hardwareTarget, pllSel);
2763
2764 // Set fCurrentMode to our set display mode
2765 memcpy(&fCurrentMode, target, sizeof(display_mode));
2766
2767 return B_OK;
2768 }
2769