1 /* 2 * Auich BeOS Driver for Intel Southbridge audio 3 * 4 * Copyright (c) 2003, Jerome Duval (jerome.duval@free.fr) 5 6 * Original code : BeOS Driver for Intel ICH AC'97 Link interface 7 * Copyright (c) 2002, Marcus Overhagen <marcus@overhagen.de> 8 * 9 * All rights reserved. 10 * Redistribution and use in source and binary forms, with or without modification, 11 * are permitted provided that the following conditions are met: 12 * 13 * - Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * - Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 25 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 27 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 28 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 * 30 */ 31 32 #ifndef _AUICHREG_H_ 33 #define _AUICHREG_H_ 34 35 /* Native Audio Bus Master Control Registers */ 36 enum AUICH_GLOBAL_REGISTER 37 { 38 AUICH_REG_GLOB_CNT = 0x2C, 39 AUICH_REG_GLOB_STA = 0x30, 40 AUICH_REG_ACC_SEMA = 0x34, 41 AUICH_REG_SDM = 0x80 42 }; 43 44 enum AUICH_X_REGISTER_BASE /* base addresses for the following offsets */ 45 { 46 AUICH_REG_PI_BASE = 0x00, 47 AUICH_REG_PO_BASE = 0x10, 48 AUICH_REG_MC_BASE = 0x20 49 }; 50 51 enum AUICH_X_REGISTER_OFFSETS /* add base address to get the PI, PO or MC reg */ 52 { 53 AUICH_REG_X_BDBAR = 0x00, 54 AUICH_REG_X_CIV = 0x04, 55 AUICH_REG_X_LVI = 0x05, 56 AUICH_REG_X_SR = 0x06, 57 AUICH_REG_X_PICB = 0x08, 58 AUICH_REG_X_PIV = 0x0A, 59 AUICH_REG_X_CR = 0x0B 60 }; 61 62 /* AUICH_REG_X_SR (Status Register) Bits */ 63 enum REG_X_SR_BITS 64 { 65 SR_DCH = 0x0001, 66 SR_CELV = 0x0002, 67 SR_LVBCI = 0x0004, 68 SR_BCIS = 0x0008, 69 SR_FIFOE = 0x0010, 70 SR_MASK = SR_FIFOE | SR_BCIS | SR_LVBCI | SR_CELV | SR_DCH //| 0x200 | 0x80 | 0x2 71 }; 72 73 /* AUICH_REG_X_CR (Control Register) Bits */ 74 enum REG_X_CR_BITS 75 { 76 CR_RPBM = 0x01, 77 CR_RR = 0x02, 78 CR_LVBIE = 0x04, 79 CR_FEIE = 0x08, 80 CR_IOCE = 0x10 81 }; 82 83 /* AUICH_REG_GLOB_CNT (Global Control Register) Bits */ 84 enum REG_GLOB_CNT_BITS 85 { 86 CNT_GIE = 0x01, 87 CNT_COLD = 0x02, 88 CNT_WARM = 0x04, 89 CNT_SHUT = 0x08, 90 CNT_PRIE = 0x10, 91 CNT_SRIE = 0x20 92 }; 93 94 /* AUICH_REG_GLOB_STA (Global Status Register) Bits */ 95 enum REG_GLOB_STA_BITS 96 { 97 STA_GSCI = 0x00000001, /* GPI Status Change Interrupt */ 98 STA_MIINT = 0x00000002, /* Modem In Interrupt */ 99 STA_MOINT = 0x00000004, /* Modem Out Interrupt */ 100 STA_PIINT = 0x00000020, /* PCM In Interrupt */ 101 STA_POINT = 0x00000040, /* PCM Out Interrupt */ 102 STA_MINT = 0x00000080, /* Mic In Interrupt */ 103 STA_S0CR = 0x00000100, /* AC_SDIN0 Codec Ready */ 104 STA_S1CR = 0x00000200, /* AC_SDIN1 Codec Ready */ 105 STA_S0RI = 0x00000400, /* AC_SDIN0 Resume Interrupt */ 106 STA_S1RI = 0x00000800, /* AC_SDIN1 Resume Interrupt */ 107 STA_RCS = 0x00008000, /* Read Completition Status */ 108 STA_AD3 = 0x00010000, 109 STA_MD3 = 0x00020000, 110 STA_SAMPLE_CAP = 0x00c00000, /* sampling precision capability */ 111 STA_POM20 = 0x00400000, /* PCM out precision 20bit */ 112 STA_CHAN_CAP = 0x00300000, /* multi-channel capability */ 113 STA_PCM4 = 0x00100000, /* 4ch output */ 114 STA_PCM6 = 0x00200000, /* 6ch output */ 115 STA_M2INT = 0x01000000, /* Microphone 2 In Interrupt */ 116 STA_P2INT = 0x02000000, /* PCM In 2 Interrupt */ 117 STA_SPINT = 0x04000000, /* S/PDIF Interrupt */ 118 STA_BCS = 0x08000000, /* Bit Clock Stopped */ 119 STA_S2CR = 0x10000000, /* AC_SDIN2 Codec Ready */ 120 STA_S2RI = 0x20000000, /* AC_SDIN2 Resume Interrupt */ 121 STA_INTMASK = (STA_MIINT | STA_MOINT | STA_PIINT | STA_POINT | STA_MINT | STA_S0RI | STA_S1RI | STA_M2INT | STA_P2INT | STA_SPINT | STA_S2RI) 122 }; 123 124 #define ICH4_MMBAR_SIZE 512 125 #define ICH4_MBBAR_SIZE 256 126 127 #endif /* _AUICHREG_H_ */ 128