1 /*
2 Haiku ATI video driver adapted from the X.org ATI driver which has the
3 following copyright:
4
5 Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario,
6 Precision Insight, Inc., Cedar Park, Texas, and
7 VA Linux Systems Inc., Fremont, California.
8
9 Copyright 2009, 2011 Haiku, Inc. All rights reserved.
10 Distributed under the terms of the MIT license.
11
12 Authors:
13 Gerald Zajac
14 */
15
16
17 #ifndef __RAGE128_H__
18 #define __RAGE128_H__
19
20
21 #define CURSOR_BYTES 1024 // bytes used for cursor image in video memory
22
23 #define R128_TIMEOUT 2000000 // Fall out of wait loops after this count
24
25
26 // Register MMIO addresses.
27 //-------------------------
28
29 #define R128_AUX_SC_CNTL 0x1660
30
31 #define R128_BUS_CNTL 0x0030
32 # define R128_BUS_MASTER_DIS (1 << 6)
33 # define R128_BUS_RD_DISCARD_EN (1 << 24)
34 # define R128_BUS_RD_ABORT_EN (1 << 25)
35 # define R128_BUS_MSTR_DISCONNECT_EN (1 << 28)
36 # define R128_BUS_WRT_BURST (1 << 29)
37 # define R128_BUS_READ_BURST (1 << 30)
38
39 #define R128_CAP0_TRIG_CNTL 0x0950 // ?
40 #define R128_CAP1_TRIG_CNTL 0x09c0 // ?
41 #define R128_CLOCK_CNTL_DATA 0x000c
42 #define R128_CLOCK_CNTL_INDEX 0x0008
43 # define R128_PLL_WR_EN (1 << 7)
44 # define R128_PLL_DIV_SEL (3 << 8)
45 #define R128_CONFIG_MEMSIZE 0x00f8
46 #define R128_CRTC_EXT_CNTL 0x0054
47 # define R128_CRTC_VGA_XOVERSCAN (1 << 0)
48 # define R128_VGA_ATI_LINEAR (1 << 3)
49 # define R128_XCRT_CNT_EN (1 << 6)
50 # define R128_CRTC_HSYNC_DIS (1 << 8)
51 # define R128_CRTC_VSYNC_DIS (1 << 9)
52 # define R128_CRTC_DISPLAY_DIS (1 << 10)
53 # define R128_CRTC_CRT_ON (1 << 15)
54 # define R128_FP_OUT_EN (1 << 22)
55 # define R128_FP_ACTIVE (1 << 23)
56 #define R128_CRTC_GEN_CNTL 0x0050
57 # define R128_CRTC_CUR_EN (1 << 16)
58 # define R128_CRTC_EXT_DISP_EN (1 << 24)
59 # define R128_CRTC_EN (1 << 25)
60 #define R128_CRTC_H_SYNC_STRT_WID 0x0204
61 # define R128_CRTC_H_SYNC_POL (1 << 23)
62 #define R128_CRTC_H_TOTAL_DISP 0x0200
63 #define R128_CRTC_OFFSET 0x0224
64 #define R128_CRTC_OFFSET_CNTL 0x0228
65 #define R128_CRTC_PITCH 0x022c
66 #define R128_CRTC_V_SYNC_STRT_WID 0x020c
67 # define R128_CRTC_V_SYNC_POL (1 << 23)
68 #define R128_CRTC_V_TOTAL_DISP 0x0208
69 #define R128_CUR_CLR0 0x026c
70 #define R128_CUR_CLR1 0x0270
71 #define R128_CUR_HORZ_VERT_OFF 0x0268
72 #define R128_CUR_HORZ_VERT_POSN 0x0264
73 #define R128_CUR_OFFSET 0x0260
74 # define R128_CUR_LOCK (1 << 31)
75
76 #define R128_DAC_CNTL 0x0058
77 # define R128_DAC_RANGE_CNTL (3 << 0)
78 # define R128_DAC_BLANKING (1 << 2)
79 # define R128_DAC_CRT_SEL_CRTC2 (1 << 4)
80 # define R128_DAC_PALETTE_ACC_CTL (1 << 5)
81 # define R128_DAC_8BIT_EN (1 << 8)
82 # define R128_DAC_VGA_ADR_EN (1 << 13)
83 # define R128_DAC_MASK_ALL (0xff << 24)
84 #define R128_DDA_CONFIG 0x02e0
85 #define R128_DDA_ON_OFF 0x02e4
86 #define R128_DEFAULT_OFFSET 0x16e0
87 #define R128_DEFAULT_PITCH 0x16e4
88 #define R128_DEFAULT_SC_BOTTOM_RIGHT 0x16e8
89 # define R128_DEFAULT_SC_RIGHT_MAX (0x1fff << 0)
90 # define R128_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)
91 #define R128_DP_BRUSH_BKGD_CLR 0x1478
92 #define R128_DP_BRUSH_FRGD_CLR 0x147c
93 #define R128_DP_CNTL 0x16c0
94 # define R128_DST_X_LEFT_TO_RIGHT (1 << 0)
95 # define R128_DST_Y_TOP_TO_BOTTOM (1 << 1)
96 #define R128_DP_DATATYPE 0x16c4
97 # define R128_HOST_BIG_ENDIAN_EN (1 << 29)
98 #define R128_DP_GUI_MASTER_CNTL 0x146c
99 # define R128_DP_SRC_SOURCE_MEMORY (2 << 24)
100 # define R128_GMC_AUX_CLIP_DIS (1 << 29)
101 # define R128_GMC_BRUSH_NONE (15 << 4)
102 # define R128_GMC_BRUSH_SOLID_COLOR (13 << 4)
103 # define R128_GMC_CLR_CMP_CNTL_DIS (1 << 28)
104 # define R128_GMC_DST_DATATYPE_SHIFT 8
105 # define R128_GMC_SRC_DATATYPE_COLOR (3 << 12)
106 # define R128_ROP3_Dn 0x00550000
107 # define R128_ROP3_P 0x00f00000
108 # define R128_ROP3_S 0x00cc0000
109 #define R128_DP_SRC_BKGD_CLR 0x15dc
110 #define R128_DP_SRC_FRGD_CLR 0x15d8
111 #define R128_DP_WRITE_MASK 0x16cc
112 #define R128_DST_BRES_DEC 0x1630
113 #define R128_DST_BRES_ERR 0x1628
114 #define R128_DST_BRES_INC 0x162c
115 #define R128_DST_HEIGHT_WIDTH 0x143c
116 #define R128_DST_WIDTH_HEIGHT 0x1598
117 #define R128_DST_Y_X 0x1438
118
119 #define R128_FP_CRTC_H_TOTAL_DISP 0x0250
120 #define R128_FP_CRTC_V_TOTAL_DISP 0x0254
121 #define R128_FP_GEN_CNTL 0x0284
122 # define R128_FP_FPON (1 << 0)
123 # define R128_FP_BLANK_DIS (1 << 1)
124 # define R128_FP_TDMS_EN (1 << 2)
125 # define R128_FP_DETECT_SENSE (1 << 8)
126 # define R128_FP_SEL_CRTC2 (1 << 13)
127 # define R128_FP_CRTC_DONT_SHADOW_VPAR (1 << 16)
128 # define R128_FP_CRTC_DONT_SHADOW_HEND (1 << 17)
129 # define R128_FP_CRTC_USE_SHADOW_VEND (1 << 18)
130 # define R128_FP_CRTC_USE_SHADOW_ROWCUR (1 << 19)
131 # define R128_FP_CRTC_HORZ_DIV2_EN (1 << 20)
132 # define R128_FP_CRTC_HOR_CRT_DIV2_DIS (1 << 21)
133 # define R128_FP_CRT_SYNC_SEL (1 << 23)
134 # define R128_FP_USE_SHADOW_EN (1 << 24)
135 #define R128_FP_H_SYNC_STRT_WID 0x02c4
136 #define R128_FP_HORZ_STRETCH 0x028c
137 # define R128_HORZ_STRETCH_RATIO_MASK 0xfff
138 # define R128_HORZ_STRETCH_RATIO_SHIFT 0
139 # define R128_HORZ_STRETCH_RATIO_MAX 4096
140 # define R128_HORZ_PANEL_SIZE (0xff << 16)
141 # define R128_HORZ_PANEL_SHIFT 16
142 # define R128_AUTO_HORZ_RATIO (0 << 24)
143 # define R128_HORZ_STRETCH_PIXREP (0 << 25)
144 # define R128_HORZ_STRETCH_BLEND (1 << 25)
145 # define R128_HORZ_STRETCH_ENABLE (1 << 26)
146 # define R128_HORZ_FP_LOOP_STRETCH (0x7 << 27)
147 # define R128_HORZ_STRETCH_RESERVED (1 << 30)
148 # define R128_HORZ_AUTO_RATIO_FIX_EN (1 << 31)
149
150 #define R128_FP_PANEL_CNTL 0x0288
151 # define R128_FP_DIGON (1 << 0)
152 # define R128_FP_BLON (1 << 1)
153 #define R128_FP_V_SYNC_STRT_WID 0x02c8
154 #define R128_FP_VERT_STRETCH 0x0290
155 # define R128_VERT_PANEL_SIZE (0x7ff << 0)
156 # define R128_VERT_PANEL_SHIFT 0
157 # define R128_VERT_STRETCH_RATIO_MASK 0x3ff
158 # define R128_VERT_STRETCH_RATIO_SHIFT 11
159 # define R128_VERT_STRETCH_RATIO_MAX 1024
160 # define R128_VERT_STRETCH_ENABLE (1 << 24)
161 # define R128_VERT_STRETCH_LINEREP (0 << 25)
162 # define R128_VERT_STRETCH_BLEND (1 << 25)
163 # define R128_VERT_AUTO_RATIO_EN (1 << 26)
164 # define R128_VERT_STRETCH_RESERVED 0xf8e00000
165
166 #define R128_GEN_INT_CNTL 0x0040
167 #define R128_GEN_INT_STATUS 0x0044
168 #define R128_GEN_RESET_CNTL 0x00f0
169 # define R128_SOFT_RESET_GUI (1 << 0)
170 #define R128_GPIO_MONID 0x0068
171 # define R128_GPIO_MONID_A_0 (1 << 0)
172 # define R128_GPIO_MONID_A_3 (1 << 3)
173 # define R128_GPIO_MONID_Y_0 (1 << 8)
174 # define R128_GPIO_MONID_Y_3 (1 << 11)
175 # define R128_GPIO_MONID_EN_0 (1 << 16)
176 # define R128_GPIO_MONID_EN_3 (1 << 19)
177 # define R128_GPIO_MONID_MASK_0 (1 << 24)
178 # define R128_GPIO_MONID_MASK_3 (1 << 27)
179 #define R128_GUI_PROBE 0x16bc
180 #define R128_GUI_STAT 0x1740
181 # define R128_GUI_FIFOCNT_MASK 0x0fff
182 # define R128_GUI_ACTIVE (1 << 31)
183
184 #define R128_HTOTAL_CNTL 0x0009 // PLL
185
186 #define R128_I2C_CNTL_1 0x0094 // ?
187
188 #define R128_LVDS_GEN_CNTL 0x02d0
189 # define R128_LVDS_ON (1 << 0)
190 # define R128_LVDS_DISPLAY_DIS (1 << 1)
191 # define R128_LVDS_EN (1 << 7)
192 # define R128_LVDS_DIGON (1 << 18)
193 # define R128_LVDS_BLON (1 << 19)
194 # define R128_LVDS_SEL_CRTC2 (1 << 23)
195 # define R128_HSYNC_DELAY_SHIFT 28
196 # define R128_HSYNC_DELAY_MASK (0xf << 28)
197
198 #define R128_MCLK_CNTL 0x000f /* PLL */
199 # define R128_FORCE_GCP (1 << 16)
200 # define R128_FORCE_PIPE3D_CP (1 << 17)
201 #define R128_MEM_CNTL 0x0140
202 #define R128_MPP_TB_CONFIG 0x01c0 // ?
203 #define R128_MPP_GP_CONFIG 0x01c8 // ?
204
205 #define R128_OVR_CLR 0x0230
206 #define R128_OVR_WID_LEFT_RIGHT 0x0234
207 #define R128_OVR_WID_TOP_BOTTOM 0x0238
208
209 #define R128_PALETTE_DATA 0x00b4
210 #define R128_PALETTE_INDEX 0x00b0
211 #define R128_PC_NGUI_CTLSTAT 0x0184
212 # define R128_PC_FLUSH_ALL 0x00ff
213 # define R128_PC_BUSY (1 << 31)
214 #define R128_PPLL_CNTL 0x0002 // PLL
215 # define R128_PPLL_RESET (1 << 0)
216 # define R128_PPLL_SLEEP (1 << 1)
217 # define R128_PPLL_ATOMIC_UPDATE_EN (1 << 16)
218 # define R128_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17)
219 #define R128_PPLL_DIV_3 0x0007 // PLL
220 # define R128_PPLL_FB3_DIV_MASK 0x07ff
221 # define R128_PPLL_POST3_DIV_MASK 0x00070000
222 #define R128_PPLL_REF_DIV 0x0003 // PLL
223 # define R128_PPLL_REF_DIV_MASK 0x03ff
224 # define R128_PPLL_ATOMIC_UPDATE_R (1 << 15) // same as _W
225 # define R128_PPLL_ATOMIC_UPDATE_W (1 << 15) // same as _R
226
227 #define R128_SC_BOTTOM_RIGHT 0x16f0
228 #define R128_SC_TOP_LEFT 0x16ec
229 #define R128_SCALE_3D_CNTL 0x1a00
230 #define R128_SRC_Y_X 0x1434
231 #define R128_SUBPIC_CNTL 0x0540 // ?
232
233 #define R128_TMDS_CRC 0x02a0
234
235 #define R128_VCLK_ECP_CNTL 0x0008 // PLL
236 # define R128_VCLK_SRC_SEL_MASK 0x03
237 # define R128_VCLK_SRC_SEL_CPUCLK 0x00
238 # define R128_VCLK_SRC_SEL_PPLLCLK 0x03
239 # define R128_ECP_DIV_MASK (3 << 8)
240 #define R128_VIPH_CONTROL 0x01D0 // ?
241
242
243 // Definitions used for overlays.
244 //===============================
245
246 #define R128_OV0_Y_X_START 0x0400
247 #define R128_OV0_Y_X_END 0x0404
248 #define R128_OV0_EXCLUSIVE_HORZ 0x0408
249 #define R128_OV0_REG_LOAD_CNTL 0x0410
250 #define R128_OV0_SCALE_CNTL 0x0420
251 #define R128_OV0_V_INC 0x0424
252 #define R128_OV0_P1_V_ACCUM_INIT 0x0428
253 #define R128_OV0_P23_V_ACCUM_INIT 0x042C
254 #define R128_OV0_P1_BLANK_LINES_AT_TOP 0x0430
255 #define R128_OV0_VID_BUF0_BASE_ADRS 0x0440
256 #define R128_OV0_VID_BUF_PITCH0_VALUE 0x0460
257 #define R128_OV0_AUTO_FLIP_CNTL 0x0470
258 #define R128_OV0_H_INC 0x0480
259 #define R128_OV0_STEP_BY 0x0484
260 #define R128_OV0_P1_H_ACCUM_INIT 0x0488
261 #define R128_OV0_P23_H_ACCUM_INIT 0x048C
262 #define R128_OV0_P1_X_START_END 0x0494
263 #define R128_OV0_P2_X_START_END 0x0498
264 #define R128_OV0_P3_X_START_END 0x049C
265 #define R128_OV0_FILTER_CNTL 0x04A0
266 #define R128_OV0_COLOUR_CNTL 0x04E0
267 #define R128_OV0_GRAPHICS_KEY_CLR 0x04EC
268 #define R128_OV0_GRAPHICS_KEY_MSK 0x04F0
269 #define R128_OV0_KEY_CNTL 0x04F4
270 # define R128_GRAPHIC_KEY_FN_EQ 0x00000040L
271 # define R128_GRAPHIC_KEY_FN_NE 0x00000050L
272 #define R128_OV0_TEST 0x04F8
273
274
275
276 // Functions to get/set PLL registers.
277 //=======================================
278
279 static inline uint32
GetPLLReg(uint8 index)280 GetPLLReg(uint8 index)
281 {
282 OUTREG8(R128_CLOCK_CNTL_INDEX, index & 0x3f);
283 return INREG(R128_CLOCK_CNTL_DATA);
284 }
285
286
287 static inline void
SetPLLReg(uint8 index,uint32 value)288 SetPLLReg(uint8 index, uint32 value)
289 {
290 OUTREG8(R128_CLOCK_CNTL_INDEX, ((index) & 0x3f) | R128_PLL_WR_EN);
291 OUTREG(R128_CLOCK_CNTL_DATA, value);
292 }
293
294
295 static inline void
SetPLLReg(uint8 index,uint32 value,uint32 mask)296 SetPLLReg(uint8 index, uint32 value, uint32 mask)
297 {
298 // Write a value to a PLL reg using a mask. The mask selects the
299 // bits to be modified.
300
301 SetPLLReg(index, (GetPLLReg(index) & ~mask) | (value & mask));
302 }
303
304
305 #endif // __RAGE128_H__
306