1 /*
2 * Copyright 2011-2017 Haiku, Inc. All rights reserved.
3 * Distributed under the terms of the MIT License.
4 *
5 * Authors:
6 * Alexander von Gluck, kallisti5@unixzen.com
7 */
8
9
10 #include <debug.h>
11 #include <arch/arm/reg.h>
12 #include <arch/generic/debug_uart.h>
13 #include <arch/arm/arch_uart_pl011.h>
14 #include <new>
15
16
17 #define PL01x_DR 0x00 // Data read or written
18 #define PL01x_RSR 0x04 // Receive status, read
19 #define PL01x_ECR 0x04 // Error clear, write
20 #define PL010_LCRH 0x08 // Line control, high
21 #define PL010_LCRM 0x0C // Line control, middle
22 #define PL010_LCRL 0x10 // Line control, low
23 #define PL010_CR 0x14 // Control
24 #define PL01x_FR 0x18 // Flag (r/o)
25 #define PL010_IIR 0x1C // Interrupt ID (r)
26 #define PL010_ICR 0x1C // Interrupt clear (w)
27 #define PL01x_ILPR 0x20 // IrDA low power
28 #define PL011_IBRD 0x24 // Interrupt baud rate divisor
29 #define PL011_FBRD 0x28 // Fractional baud rate divisor
30 #define PL011_LCRH 0x2C // Line control
31 #define PL011_CR 0x30 // Control
32 #define PL011_IFLS 0x34 // Interrupt fifo level
33 #define PL011_IMSC 0x38 // Interrupt mask
34 #define PL011_RIS 0x3C // Raw interrupt
35 #define PL011_MIS 0x40 // Masked interrupt
36 #define PL011_ICR 0x44 // Interrupt clear
37 #define PL011_DMACR 0x48 // DMA control register
38
39 #define PL011_DR_OE (1 << 11)
40 #define PL011_DR_BE (1 << 10)
41 #define PL011_DR_PE (1 << 9)
42 #define PL011_DR_FE (1 << 8)
43
44 #define PL01x_RSR_OE 0x08
45 #define PL01x_RSR_BE 0x04
46 #define PL01x_RSR_PE 0x02
47 #define PL01x_RSR_FE 0x01
48
49 #define PL011_FR_RI 0x100
50 #define PL011_FR_TXFE 0x080
51 #define PL011_FR_RXFF 0x040
52 #define PL01x_FR_TXFF 0x020
53 #define PL01x_FR_RXFE 0x010
54 #define PL01x_FR_BUSY 0x008
55 #define PL01x_FR_DCD 0x004
56 #define PL01x_FR_DSR 0x002
57 #define PL01x_FR_CTS 0x001
58 #define PL01x_FR_TMSK (PL01x_FR_TXFF | PL01x_FR_BUSY)
59
60 #define PL011_CR_CTSEN 0x8000 // CTS flow control
61 #define PL011_CR_RTSEN 0x4000 // RTS flow control
62 #define PL011_CR_OUT2 0x2000 // OUT2
63 #define PL011_CR_OUT1 0x1000 // OUT1
64 #define PL011_CR_RTS 0x0800 // RTS
65 #define PL011_CR_DTR 0x0400 // DTR
66 #define PL011_CR_RXE 0x0200 // Receive enable
67 #define PL011_CR_TXE 0x0100 // Transmit enable
68 #define PL011_CR_LBE 0x0080 // Loopback enable
69 #define PL010_CR_RTIE 0x0040
70 #define PL010_CR_TIE 0x0020
71 #define PL010_CR_RIE 0x0010
72 #define PL010_CR_MSIE 0x0008
73 #define PL01x_CR_IIRLP 0x0004 // SIR low power mode
74 #define PL01x_CR_SIREN 0x0002 // SIR enable
75 #define PL01x_CR_UARTEN 0x0001 // UART enable
76
77 #define PL011_LCRH_SPS 0x80
78 #define PL01x_LCRH_WLEN_8 0x60
79 #define PL01x_LCRH_WLEN_7 0x40
80 #define PL01x_LCRH_WLEN_6 0x20
81 #define PL01x_LCRH_WLEN_5 0x00
82 #define PL01x_LCRH_FEN 0x10
83 #define PL01x_LCRH_STP2 0x08
84 #define PL01x_LCRH_EPS 0x04
85 #define PL01x_LCRH_PEN 0x02
86 #define PL01x_LCRH_BRK 0x01
87
88 #define PL010_IIR_RTIS 0x08
89 #define PL010_IIR_TIS 0x04
90 #define PL010_IIR_RIS 0x02
91 #define PL010_IIR_MIS 0x01
92
93 #define PL011_IFLS_RX1_8 (0 << 3)
94 #define PL011_IFLS_RX2_8 (1 << 3)
95 #define PL011_IFLS_RX4_8 (2 << 3)
96 #define PL011_IFLS_RX6_8 (3 << 3)
97 #define PL011_IFLS_RX7_8 (4 << 3)
98 #define PL011_IFLS_TX1_8 (0 << 0)
99 #define PL011_IFLS_TX2_8 (1 << 0)
100 #define PL011_IFLS_TX4_8 (2 << 0)
101 #define PL011_IFLS_TX6_8 (3 << 0)
102 #define PL011_IFLS_TX7_8 (4 << 0)
103
104 #define PL011_IFLS_RX_HALF (5 << 3) // ST vendor only
105 #define PL011_IFLS_TX_HALF (5 << 0) // ST vendor only
106
107 #define PL011_OEIM (1 << 10) // overrun error interrupt mask
108 #define PL011_BEIM (1 << 9) // break error interrupt mask
109 #define PL011_PEIM (1 << 8) // parity error interrupt mask
110 #define PL011_FEIM (1 << 7) // framing error interrupt mask
111 #define PL011_RTIM (1 << 6) // receive timeout interrupt mask
112 #define PL011_TXIM (1 << 5) // transmit interrupt mask
113 #define PL011_RXIM (1 << 4) // receive interrupt mask
114 #define PL011_DSRMIM (1 << 3) // DSR interrupt mask
115 #define PL011_DCDMIM (1 << 2) // DCD interrupt mask
116 #define PL011_CTSMIM (1 << 1) // CTS interrupt mask
117 #define PL011_RIMIM (1 << 0) // RI interrupt mask
118 #define PL011_MSKIM 0x7ff // Mask all interrupts
119
120 #define PL011_OEIS (1 << 10) // overrun error interrupt state
121 #define PL011_BEIS (1 << 9) // break error interrupt state
122 #define PL011_PEIS (1 << 8) // parity error interrupt state
123 #define PL011_FEIS (1 << 7) // framing error interrupt state
124 #define PL011_RTIS (1 << 6) // receive timeout interrupt state
125 #define PL011_TXIS (1 << 5) // transmit interrupt state
126 #define PL011_RXIS (1 << 4) // receive interrupt state
127 #define PL011_DSRMIS (1 << 3) // DSR interrupt state
128 #define PL011_DCDMIS (1 << 2) // DCD interrupt state
129 #define PL011_CTSMIS (1 << 1) // CTS interrupt state
130 #define PL011_RIMIS (1 << 0) // RI interrupt state
131
132 #define PL011_OEIC (1 << 10) // overrun error interrupt clear
133 #define PL011_BEIC (1 << 9) // break error interrupt clear
134 #define PL011_PEIC (1 << 8) // parity error interrupt clear
135 #define PL011_FEIC (1 << 7) // framing error interrupt clear
136 #define PL011_RTIC (1 << 6) // receive timeout interrupt clear
137 #define PL011_TXIC (1 << 5) // transmit interrupt clear
138 #define PL011_RXIC (1 << 4) // receive interrupt clear
139 #define PL011_DSRMIC (1 << 3) // DSR interrupt clear
140 #define PL011_DCDMIC (1 << 2) // DCD interrupt clear
141 #define PL011_CTSMIC (1 << 1) // CTS interrupt clear
142 #define PL011_RIMIC (1 << 0) // RI interrupt clear
143
144 #define PL011_DMAONERR (1 << 2) // disable dma on err
145 #define PL011_TXDMAE (1 << 1) // enable transmit dma
146 #define PL011_RXDMAE (1 << 0) // enable receive dma
147
148
ArchUARTPL011(addr_t base,int64 clock)149 ArchUARTPL011::ArchUARTPL011(addr_t base, int64 clock)
150 :
151 DebugUART(base, clock)
152 {
153 Barrier();
154
155 // ** Loopback test
156 uint32 cr = PL01x_CR_UARTEN;
157 // Enable UART
158 cr |= PL011_CR_TXE;
159 // Enable TX
160 cr |= PL011_CR_LBE;
161 // Enable Loopback mode
162 Out32(PL011_CR, cr);
163
164 Out32(PL011_FBRD, 0);
165 Out32(PL011_IBRD, 1);
166 Out32(PL011_LCRH, 0); // TODO: ST is different tx, rx lcr
167
168 // Write a 0 to the port and wait for confim..
169 Out32(PL01x_DR, 0);
170
171 while (In32(PL01x_FR) & PL01x_FR_BUSY)
172 Barrier();
173
174 // ** Disable loopback, enable uart
175 cr = PL01x_CR_UARTEN | PL011_CR_RXE | PL011_CR_TXE;
176 Out32(PL011_CR, cr);
177
178 // ** Clear interrupts
179 Out32(PL011_ICR, PL011_OEIS | PL011_BEIS
180 | PL011_PEIS | PL011_FEIS);
181
182 // ** Disable interrupts
183 Out32(PL011_IMSC, In32(PL011_IMSC) & ~PL011_MSKIM);
184 }
185
186
~ArchUARTPL011()187 ArchUARTPL011::~ArchUARTPL011()
188 {
189 }
190
191
192 void
Out32(int reg,uint32 data)193 ArchUARTPL011::Out32(int reg, uint32 data)
194 {
195 *(volatile uint32*)(Base() + reg) = data;
196 }
197
198
199 uint32
In32(int reg)200 ArchUARTPL011::In32(int reg)
201 {
202 return *(volatile uint32*)(Base() + reg);
203 }
204
205
206 void
Barrier()207 ArchUARTPL011::Barrier()
208 {
209 asm volatile ("" : : : "memory");
210 }
211
212
213 void
InitPort(uint32 baud)214 ArchUARTPL011::InitPort(uint32 baud)
215 {
216 // Calculate baud divisor
217 uint32 baudDivisor = Clock() / (16 * baud);
218 uint32 remainder = Clock() % (16 * baud);
219 uint32 baudFractional = ((8 * remainder) / baud >> 1)
220 + ((8 * remainder) / baud & 1);
221
222 // Disable UART
223 Disable();
224
225 // Set baud divisor
226 Out32(PL011_IBRD, baudDivisor);
227 Out32(PL011_FBRD, baudFractional);
228
229 // Set LCR 8n1, enable fifo
230 Out32(PL011_LCRH, (In32(PL011_LCRH) & ~0xff)
231 | PL01x_LCRH_WLEN_8 | PL01x_LCRH_FEN);
232
233 // Set FIFO levels
234 Out32(PL011_IFLS, PL011_IFLS_RX4_8 | PL011_IFLS_TX4_8);
235
236 // Enable UART
237 Enable();
238 }
239
240
241 void
InitEarly()242 ArchUARTPL011::InitEarly()
243 {
244 // Perform special hardware UART configuration
245 }
246
247
248 void
Enable()249 ArchUARTPL011::Enable()
250 {
251 uint32 cr = PL01x_CR_UARTEN;
252 // Enable UART
253 cr |= PL011_CR_TXE | PL011_CR_RXE;
254 // Enable TX and RX
255
256 Out32(PL011_CR, cr);
257
258 DebugUART::Enable();
259 }
260
261
262 void
Disable()263 ArchUARTPL011::Disable()
264 {
265 // Disable everything
266 Out32(PL011_CR, 0);
267
268 DebugUART::Disable();
269 }
270
271
272 int
PutChar(char c)273 ArchUARTPL011::PutChar(char c)
274 {
275 if (Enabled() == true) {
276 // Wait until there is room in fifo
277 while ((In32(PL01x_FR) & PL01x_FR_TXFF) != 0)
278 Barrier();
279
280 Out32(PL01x_DR, c);
281 return 0;
282 }
283
284 return -1;
285 }
286
287
288 int
GetChar(bool wait)289 ArchUARTPL011::GetChar(bool wait)
290 {
291 if (Enabled() == true) {
292 if (wait) {
293 // Wait until a character is received
294 while ((In32(PL01x_FR) & PL01x_FR_RXFE) != 0)
295 Barrier();
296 } else {
297 // Check if there is any data available in RX fifo
298 if ((In32(PL01x_FR) & PL01x_FR_RXFE) != 0)
299 return -1;
300 }
301 return In32(PL01x_DR);
302 }
303
304 return -1;
305 }
306
307
308 void
FlushTx()309 ArchUARTPL011::FlushTx()
310 {
311 // Wait until transmit fifo empty
312 while ((In32(PL01x_FR) & PL011_FR_TXFE) == 0)
313 Barrier();
314 }
315
316
317 void
FlushRx()318 ArchUARTPL011::FlushRx()
319 {
320 // Wait until receive fifo empty
321 while ((In32(PL01x_FR) & PL01x_FR_RXFE) == 0)
322 Barrier();
323 }
324
325
326 ArchUARTPL011*
arch_get_uart_pl011(addr_t base,int64 clock)327 arch_get_uart_pl011(addr_t base, int64 clock)
328 {
329 static char buffer[sizeof(ArchUARTPL011)];
330 ArchUARTPL011 *uart = new(buffer) ArchUARTPL011(base, clock);
331 return uart;
332 }
333