1 /*
2 * Copyright 2007, Ithamar R. Adema. All rights reserved.
3 * Distributed under the terms of the MIT License.
4 */
5
6
7 #include <ata_adapter.h>
8 #include <KernelExport.h>
9
10 #include <stdlib.h>
11 #include <string.h>
12
13
14 #define DRIVER_PRETTY_NAME "Legacy SATA"
15 #define CONTROLLER_NAME DRIVER_PRETTY_NAME
16 #define CONTROLLER_MODULE_NAME "busses/ata/legacy_sata/driver_v1"
17 #define CHANNEL_MODULE_NAME "busses/ata/legacy_sata/channel/v1"
18
19 #define TRACE(a...) dprintf(DRIVER_PRETTY_NAME ": " a)
20 #define FLOW(a...) dprintf(DRIVER_PRETTY_NAME ": " a)
21
22 #define PCI_vendor_VIA 0x1106
23 #define PCI_device_VIA6420 0x3149
24 #define PCI_device_VIA6421 0x3249
25 #define PCI_device_VIA8237A 0x0591
26
27 #define PCI_vendor_ALI 0x10b9
28 #define PCI_device_ALI5289 0x5289
29 #define PCI_device_ALI5287 0x5287
30 #define PCI_device_ALI5281 0x5281
31
32 #define PCI_vendor_NVIDIA 0x10de
33 #define PCI_device_NF2PROS1 0x008e
34 #define PCI_device_NF3PROS1 0x00e3
35 #define PCI_device_NF3PROS2 0x00ee
36 #define PCI_device_MCP4S1 0x0036
37 #define PCI_device_MCP4S2 0x003e
38 #define PCI_device_CK804S1 0x0054
39 #define PCI_device_CK804S2 0x0055
40 #define PCI_device_MCP51S1 0x0266
41 #define PCI_device_MCP51S2 0x0267
42 #define PCI_device_MCP55S1 0x037e
43 #define PCI_device_MCP55S2 0x037f
44 #define PCI_device_MCP61S1 0x03e7
45 #define PCI_device_MCP61S2 0x03f6
46 #define PCI_device_MCP61S3 0x03f7
47
48 #define ID(v,d) (((v)<< 16) | (d))
49
50
51 static const char * const kChannelNames[] = {
52 "Primary Channel", "Secondary Channel",
53 "Tertiary Channel", "Quaternary Channel"
54 };
55
56 static ata_for_controller_interface* sATA;
57 static ata_adapter_interface* sATAAdapter;
58 static device_manager_info* sDeviceManager;
59
60
61 static float
controller_supports(device_node * parent)62 controller_supports(device_node *parent)
63 {
64 uint16 vendor_id;
65 uint16 device_id;
66 status_t res;
67 const char *bus = NULL;
68
69 // get the bus (should be PCI)
70 if (sDeviceManager->get_attr_string(parent, B_DEVICE_BUS, &bus, false) != B_OK)
71 return B_ERROR;
72 if (strcmp(bus, "pci") != 0) {
73 return B_ERROR;
74 }
75
76 // get vendor and device ID
77 if ((res = sDeviceManager->get_attr_uint16(parent, B_DEVICE_VENDOR_ID, &vendor_id, false)) != B_OK
78 || (res = sDeviceManager->get_attr_uint16(parent, B_DEVICE_ID, &device_id, false)) != B_OK) {
79 return res;
80 }
81
82 switch (ID(vendor_id, device_id)) {
83 /* VIA SATA chipsets */
84 case ID(PCI_vendor_VIA, PCI_device_VIA6420):
85 case ID(PCI_vendor_VIA, PCI_device_VIA6421):
86 case ID(PCI_vendor_VIA, PCI_device_VIA8237A):
87 break;
88
89 /* ALI SATA chipsets */
90 case ID(PCI_vendor_ALI, PCI_device_ALI5281):
91 case ID(PCI_vendor_ALI, PCI_device_ALI5287):
92 case ID(PCI_vendor_ALI, PCI_device_ALI5289):
93 break;
94
95 /* NVidia NForce chipsets */
96 case ID(PCI_vendor_NVIDIA, PCI_device_NF2PROS1):
97 case ID(PCI_vendor_NVIDIA, PCI_device_NF3PROS1):
98 case ID(PCI_vendor_NVIDIA, PCI_device_NF3PROS2):
99 case ID(PCI_vendor_NVIDIA, PCI_device_MCP4S1):
100 case ID(PCI_vendor_NVIDIA, PCI_device_MCP4S2):
101 case ID(PCI_vendor_NVIDIA, PCI_device_CK804S1):
102 case ID(PCI_vendor_NVIDIA, PCI_device_CK804S2):
103 case ID(PCI_vendor_NVIDIA, PCI_device_MCP51S1):
104 case ID(PCI_vendor_NVIDIA, PCI_device_MCP51S2):
105 case ID(PCI_vendor_NVIDIA, PCI_device_MCP55S1):
106 case ID(PCI_vendor_NVIDIA, PCI_device_MCP55S2):
107 case ID(PCI_vendor_NVIDIA, PCI_device_MCP61S1):
108 case ID(PCI_vendor_NVIDIA, PCI_device_MCP61S2):
109 case ID(PCI_vendor_NVIDIA, PCI_device_MCP61S3):
110 break;
111
112 default:
113 return 0.0f;
114 }
115
116 TRACE("controller found! vendor 0x%04x, device 0x%04x\n", vendor_id, device_id);
117
118 return 0.8f;
119 }
120
121
122 static status_t
controller_probe(device_node * parent)123 controller_probe(device_node *parent)
124 {
125 device_node *controller_node;
126 device_node *channels[4];
127 uint16 command_block_base[4];
128 uint16 control_block_base[4];
129 pci_device_module_info *pci;
130 uint8 num_channels = 2;
131 uint32 bus_master_base;
132 pci_device *device = NULL;
133 uint16 device_id;
134 uint16 vendor_id;
135 uint8 int_num;
136 status_t res;
137 uint8 index;
138
139 TRACE("controller_probe\n");
140
141 sDeviceManager->get_driver(parent, (driver_module_info **)&pci, (void **)&device);
142
143 device_id = pci->read_pci_config(device, PCI_device_id, 2);
144 vendor_id = pci->read_pci_config(device, PCI_vendor_id, 2);
145 int_num = pci->read_pci_config(device, PCI_interrupt_line, 1);
146 bus_master_base = pci->read_pci_config(device, PCI_base_registers + 16, 4);
147
148 /* Default PCI assigments */
149 command_block_base[0] = pci->read_pci_config(device, PCI_base_registers + 0, 4);
150 control_block_base[0] = pci->read_pci_config(device, PCI_base_registers + 4, 4);
151 command_block_base[1] = pci->read_pci_config(device, PCI_base_registers + 8, 4);
152 control_block_base[1] = pci->read_pci_config(device, PCI_base_registers + 12, 4);
153
154 /* enable PCI interrupt */
155 pci->write_pci_config(device, PCI_command, 2,
156 pci->read_pci_config(device, PCI_command, 2) & ~PCI_command_int_disable);
157
158 if (vendor_id == PCI_vendor_NVIDIA) {
159 /* enable control access */
160 pci->write_pci_config(device, 0x50, 1,
161 pci->read_pci_config(device, 0x50, 1) | 0x04);
162 }
163
164 switch (ID(vendor_id, device_id)) {
165 case ID(PCI_vendor_VIA,PCI_device_VIA6421):
166 /* newer SATA chips has resources in one BAR for each channel */
167 num_channels = 4;
168 command_block_base[0] = pci->read_pci_config(device, PCI_base_registers + 0, 4);
169 control_block_base[0] = command_block_base[0] + 8;
170 command_block_base[1] = pci->read_pci_config(device, PCI_base_registers + 4, 4);
171 control_block_base[1] = command_block_base[1] + 8;
172 command_block_base[2] = pci->read_pci_config(device, PCI_base_registers + 8, 4);
173 control_block_base[2] = command_block_base[2] + 8;
174 command_block_base[3] = pci->read_pci_config(device, PCI_base_registers + 12, 4);
175 control_block_base[3] = command_block_base[3] + 8;
176 break;
177
178 case ID(PCI_vendor_ALI, PCI_device_ALI5287):
179 num_channels = 4;
180 command_block_base[2] = pci->read_pci_config(device, PCI_base_registers + 0, 4) + 8;
181 control_block_base[2] = pci->read_pci_config(device, PCI_base_registers + 4, 4) + 4;
182 command_block_base[3] = pci->read_pci_config(device, PCI_base_registers + 8, 4) + 8;
183 control_block_base[3] = pci->read_pci_config(device, PCI_base_registers + 12, 4) + 4;
184 break;
185 }
186
187 bus_master_base &= PCI_address_io_mask;
188 for (index = 0; index < num_channels; index++) {
189 command_block_base[index] &= PCI_address_io_mask;
190 control_block_base[index] &= PCI_address_io_mask;
191 }
192
193 res = sATAAdapter->detect_controller(pci, device, parent, bus_master_base,
194 CONTROLLER_MODULE_NAME, "" /* XXX: unused: controller_driver_type*/, CONTROLLER_NAME, true,
195 true, 1, 0xffff, 0x10000, &controller_node);
196 // don't register if controller is already registered!
197 // (happens during rescan; registering new channels would kick out old channels)
198 if (res != B_OK)
199 goto err;
200 if (controller_node == NULL) {
201 res = B_IO_ERROR;
202 goto err;
203 }
204
205 // ignore errors during registration of channels - could be a simple rescan collision
206
207 for (index = 0; index < num_channels; index++) {
208 res = sATAAdapter->detect_channel(pci, device, controller_node, CHANNEL_MODULE_NAME,
209 true, command_block_base[index], control_block_base[index], bus_master_base,
210 int_num, index, kChannelNames[index], &channels[index], false);
211
212 dprintf("%s: %s\n", kChannelNames[index], strerror(res));
213 }
214
215
216 TRACE("controller_probe success\n");
217 return B_OK;
218
219 err:
220 TRACE("controller_probe failed (%s)\n", strerror(res));
221 return res;
222 }
223
224
225 static status_t
controller_init(device_node * node,void ** controller_cookie)226 controller_init(device_node *node, void **controller_cookie)
227 {
228 return sATAAdapter->init_controller(
229 node, (ata_adapter_controller_info**)controller_cookie,
230 sizeof(ata_adapter_controller_info));
231 }
232
233
234 static void
controller_uninit(void * controller_cookie)235 controller_uninit(void *controller_cookie)
236 {
237 sATAAdapter->uninit_controller((ata_adapter_controller_info*)controller_cookie);
238 }
239
240
241 static void
controller_removed(void * controller_cookie)242 controller_removed(void *controller_cookie)
243 {
244 sATAAdapter->controller_removed((ata_adapter_controller_info*)controller_cookie);
245 }
246
247
248 static status_t
channel_init(device_node * node,void ** channel_cookie)249 channel_init(device_node *node, void **channel_cookie)
250 {
251 return sATAAdapter->init_channel(node,
252 (ata_adapter_channel_info**)channel_cookie,
253 sizeof(ata_adapter_channel_info), sATAAdapter->inthand);
254 }
255
256
257 static void
channel_uninit(void * channel_cookie)258 channel_uninit(void *channel_cookie)
259 {
260 sATAAdapter->uninit_channel((ata_adapter_channel_info*)channel_cookie);
261 }
262
263
264 static void
channel_removed(void * channel_cookie)265 channel_removed(void *channel_cookie)
266 {
267 sATAAdapter->channel_removed((ata_adapter_channel_info*)channel_cookie);
268 }
269
270
271 static void
channel_set(void * channel_cookie,ata_channel channel)272 channel_set(void *channel_cookie, ata_channel channel)
273 {
274 sATAAdapter->set_channel((ata_adapter_channel_info*)channel_cookie,
275 channel);
276 }
277
278
279 static status_t
task_file_write(void * channel_cookie,ata_task_file * tf,ata_reg_mask mask)280 task_file_write(void *channel_cookie, ata_task_file *tf, ata_reg_mask mask)
281 {
282 return sATAAdapter->write_command_block_regs(
283 (ata_adapter_channel_info*)channel_cookie, tf, mask);
284 }
285
286
287 static status_t
task_file_read(void * channel_cookie,ata_task_file * tf,ata_reg_mask mask)288 task_file_read(void *channel_cookie, ata_task_file *tf, ata_reg_mask mask)
289 {
290 return sATAAdapter->read_command_block_regs(
291 (ata_adapter_channel_info*)channel_cookie, tf, mask);
292 }
293
294
295 static uint8
altstatus_read(void * channel_cookie)296 altstatus_read(void *channel_cookie)
297 {
298 return sATAAdapter->get_altstatus(
299 (ata_adapter_channel_info*)channel_cookie);
300 }
301
302
303 static status_t
device_control_write(void * channel_cookie,uint8 val)304 device_control_write(void *channel_cookie, uint8 val)
305 {
306 return sATAAdapter->write_device_control(
307 (ata_adapter_channel_info*)channel_cookie, val);
308 }
309
310
311 static status_t
pio_write(void * channel_cookie,uint16 * data,int count,bool force_16bit)312 pio_write(void *channel_cookie, uint16 *data, int count, bool force_16bit)
313 {
314 return sATAAdapter->write_pio((ata_adapter_channel_info*)channel_cookie,
315 data, count, force_16bit);
316 }
317
318
319 static status_t
pio_read(void * channel_cookie,uint16 * data,int count,bool force_16bit)320 pio_read(void *channel_cookie, uint16 *data, int count, bool force_16bit)
321 {
322 return sATAAdapter->read_pio((ata_adapter_channel_info*)channel_cookie,
323 data, count, force_16bit);
324 }
325
326
327 static status_t
dma_prepare(void * channel_cookie,const physical_entry * sg_list,size_t sg_list_count,bool write)328 dma_prepare(void *channel_cookie, const physical_entry *sg_list,
329 size_t sg_list_count, bool write)
330 {
331 return sATAAdapter->prepare_dma((ata_adapter_channel_info*)channel_cookie,
332 sg_list, sg_list_count, write);
333 }
334
335
336 static status_t
dma_start(void * channel_cookie)337 dma_start(void *channel_cookie)
338 {
339 return sATAAdapter->start_dma((ata_adapter_channel_info*)channel_cookie);
340 }
341
342
343 static status_t
dma_finish(void * channel_cookie)344 dma_finish(void *channel_cookie)
345 {
346 return sATAAdapter->finish_dma((ata_adapter_channel_info*)channel_cookie);
347 }
348
349
350 module_dependency module_dependencies[] = {
351 { ATA_FOR_CONTROLLER_MODULE_NAME, (module_info **)&sATA },
352 { B_DEVICE_MANAGER_MODULE_NAME, (module_info **)&sDeviceManager },
353 { ATA_ADAPTER_MODULE_NAME, (module_info **)&sATAAdapter },
354 {}
355 };
356
357 static ata_controller_interface sChannelInterface = {
358 {
359 {
360 CHANNEL_MODULE_NAME,
361 0,
362 NULL
363 },
364
365 NULL,
366 NULL,
367 channel_init,
368 channel_uninit,
369 NULL,
370 NULL,
371 channel_removed,
372 },
373
374 channel_set,
375
376 task_file_write,
377 task_file_read,
378
379 altstatus_read,
380 device_control_write,
381
382 pio_write,
383 pio_read,
384
385 dma_prepare,
386 dma_start,
387 dma_finish,
388 };
389
390 static driver_module_info sControllerInterface = {
391 {
392 CONTROLLER_MODULE_NAME,
393 0,
394 NULL
395 },
396
397 controller_supports,
398 controller_probe,
399 controller_init,
400 controller_uninit,
401 NULL, // register child devices
402 NULL, // rescan
403 controller_removed,
404 };
405
406 module_info *modules[] = {
407 (module_info *)&sControllerInterface,
408 (module_info *)&sChannelInterface,
409 NULL
410 };
411