1 /* NM registers definitions and macros for access to */ 2 3 /* PCI_config_space */ 4 #define NMCFG_DEVID 0x00 5 #define NMCFG_DEVCTRL 0x04 6 #define NMCFG_CLASS 0x08 7 #define NMCFG_HEADER 0x0c 8 #define NMCFG_BASE1FB 0x10 9 #define NMCFG_BASE2REG1 0x14 10 #define NMCFG_BASE3REG2 0x18 11 #define NMCFG_BASE4 0x1c //unknown if used 12 #define NMCFG_BASE5 0x20 //unknown if used 13 #define NMCFG_BASE6 0x24 //unknown if used 14 #define NMCFG_BASE7 0x28 //unknown if used 15 #define NMCFG_SUBSYSID1 0x2c 16 #define NMCFG_ROMBASE 0x30 17 #define NMCFG_CAPPTR 0x34 18 #define NMCFG_CFG_1 0x38 //unknown if used 19 #define NMCFG_INTERRUPT 0x3c 20 #define NMCFG_CFG_3 0x40 //unknown if used 21 #define NMCFG_CFG_4 0x44 //unknown if used 22 #define NMCFG_CFG_5 0x48 //unknown if used 23 #define NMCFG_CFG_6 0x4c //unknown if used 24 #define NMCFG_CFG_7 0x50 //unknown if used 25 #define NMCFG_CFG_8 0x54 //unknown if used 26 #define NMCFG_CFG_9 0x58 //unknown if used 27 #define NMCFG_CFG_10 0x5c //unknown if used 28 #define NMCFG_CFG_11 0x60 //unknown if used 29 #define NMCFG_CFG_12 0x64 //unknown if used 30 #define NMCFG_CFG_13 0x68 //unknown if used 31 #define NMCFG_CFG_14 0x6c //unknown if used 32 #define NMCFG_CFG_15 0x70 //unknown if used 33 #define NMCFG_CFG_16 0x74 //unknown if used 34 #define NMCFG_CFG_17 0x78 //unknown if used 35 #define NMCFG_CFG_18 0x7c //unknown if used 36 #define NMCFG_CFG_19 0x80 //unknown if used 37 #define NMCFG_CFG_20 0x84 //unknown if used 38 #define NMCFG_CFG_21 0x88 //unknown if used 39 #define NMCFG_CFG_22 0x8c //unknown if used 40 #define NMCFG_CFG_23 0x90 //unknown if used 41 #define NMCFG_CFG_24 0x94 //unknown if used 42 #define NMCFG_CFG_25 0x98 //unknown if used 43 #define NMCFG_CFG_26 0x9c //unknown if used 44 #define NMCFG_CFG_27 0xa0 //unknown if used 45 #define NMCFG_CFG_28 0xa4 //unknown if used 46 #define NMCFG_CFG_29 0xa8 //unknown if used 47 #define NMCFG_CFG_30 0xac //unknown if used 48 #define NMCFG_CFG_31 0xb0 //unknown if used 49 #define NMCFG_CFG_32 0xb4 //unknown if used 50 #define NMCFG_CFG_33 0xb8 //unknown if used 51 #define NMCFG_CFG_34 0xbc //unknown if used 52 #define NMCFG_CFG_35 0xc0 //unknown if used 53 #define NMCFG_CFG_36 0xc4 //unknown if used 54 #define NMCFG_CFG_37 0xc8 //unknown if used 55 #define NMCFG_CFG_38 0xcc //unknown if used 56 #define NMCFG_CFG_39 0xd0 //unknown if used 57 #define NMCFG_CFG_40 0xd4 //unknown if used 58 #define NMCFG_CFG_41 0xd8 //unknown if used 59 #define NMCFG_CFG_42 0xdc //unknown if used 60 #define NMCFG_CFG_43 0xe0 //unknown if used 61 #define NMCFG_CFG_44 0xe4 //unknown if used 62 #define NMCFG_CFG_45 0xe8 //unknown if used 63 #define NMCFG_CFG_46 0xec //unknown if used 64 #define NMCFG_CFG_47 0xf0 //unknown if used 65 #define NMCFG_CFG_48 0xf4 //unknown if used 66 #define NMCFG_CFG_49 0xf8 //unknown if used 67 #define NMCFG_CFG_50 0xfc //unknown if used 68 69 /* neomagic ISA direct registers */ 70 /* VGA standard registers: */ 71 #define NMISA8_ATTRINDW 0x03c0 72 #define NMISA8_ATTRINDR 0x03c1 73 #define NMISA8_ATTRDATW 0x03c0 74 #define NMISA8_ATTRDATR 0x03c1 75 #define NMISA8_SEQIND 0x03c4 76 #define NMISA8_SEQDAT 0x03c5 77 #define NMISA16_SEQIND 0x03c4 78 #define NMISA8_CRTCIND 0x03d4 79 #define NMISA8_CRTCDAT 0x03d5 80 #define NMISA16_CRTCIND 0x03d4 81 #define NMISA8_GRPHIND 0x03ce 82 #define NMISA8_GRPHDAT 0x03cf 83 #define NMISA16_GRPHIND 0x03ce 84 85 /* neomagic PCI direct registers */ 86 #define NM2PCI8_SEQIND 0x03c4 87 #define NM2PCI8_SEQDAT 0x03c5 88 #define NM2PCI16_SEQIND 0x03c4 89 #define NM2PCI8_GRPHIND 0x03ce 90 #define NM2PCI8_GRPHDAT 0x03cf 91 #define NM2PCI16_GRPHIND 0x03ce 92 93 /* neomagic ISA GENERAL direct registers */ 94 /* VGA standard registers: */ 95 #define NMISA8_MISCW 0x03c2 96 #define NMISA8_MISCR 0x03cc 97 #define NMISA8_INSTAT1 0x03da 98 99 /* neomagic ISA (DAC) COLOR direct registers (VGA palette RAM) */ 100 /* VGA standard registers: */ 101 #define NMISA8_PALMASK 0x03c6 102 #define NMISA8_PALINDR 0x03c7 103 #define NMISA8_PALINDW 0x03c8 104 #define NMISA8_PALDATA 0x03c9 105 106 /* neomagic ISA CRTC indexed registers */ 107 /* VGA standard registers: */ 108 #define NMCRTCX_HTOTAL 0x00 109 #define NMCRTCX_HDISPE 0x01 110 #define NMCRTCX_HBLANKS 0x02 111 #define NMCRTCX_HBLANKE 0x03 112 #define NMCRTCX_HSYNCS 0x04 113 #define NMCRTCX_HSYNCE 0x05 114 #define NMCRTCX_VTOTAL 0x06 115 #define NMCRTCX_OVERFLOW 0x07 116 #define NMCRTCX_PRROWSCN 0x08 117 #define NMCRTCX_MAXSCLIN 0x09 118 #define NMCRTCX_VGACURCTRL 0x0a 119 #define NMCRTCX_FBSTADDH 0x0c 120 #define NMCRTCX_FBSTADDL 0x0d 121 #define NMCRTCX_VSYNCS 0x10 122 #define NMCRTCX_VSYNCE 0x11 123 #define NMCRTCX_VDISPE 0x12 124 #define NMCRTCX_PITCHL 0x13 125 #define NMCRTCX_VBLANKS 0x15 126 #define NMCRTCX_VBLANKE 0x16 127 #define NMCRTCX_MODECTL 0x17 128 #define NMCRTCX_LINECOMP 0x18 129 /* NeoMagic specific registers: */ 130 #define NMCRTCX_PANEL_0x40 0x40 131 #define NMCRTCX_PANEL_0x41 0x41 132 #define NMCRTCX_PANEL_0x42 0x42 133 #define NMCRTCX_PANEL_0x43 0x43 134 #define NMCRTCX_PANEL_0x44 0x44 135 #define NMCRTCX_PANEL_0x45 0x45 136 #define NMCRTCX_PANEL_0x46 0x46 137 #define NMCRTCX_PANEL_0x47 0x47 138 #define NMCRTCX_PANEL_0x48 0x48 139 #define NMCRTCX_PANEL_0x49 0x49 140 #define NMCRTCX_PANEL_0x4a 0x4a 141 #define NMCRTCX_PANEL_0x4b 0x4b 142 #define NMCRTCX_PANEL_0x4c 0x4c 143 #define NMCRTCX_PANEL_0x4d 0x4d 144 #define NMCRTCX_PANEL_0x4e 0x4e 145 #define NMCRTCX_PANEL_0x4f 0x4f 146 #define NMCRTCX_PANEL_0x50 0x50 /* >= NM2090 */ 147 #define NMCRTCX_PANEL_0x51 0x51 /* >= NM2090 */ 148 #define NMCRTCX_PANEL_0x52 0x52 /* >= NM2090 */ 149 #define NMCRTCX_PANEL_0x53 0x53 /* >= NM2090 */ 150 #define NMCRTCX_PANEL_0x54 0x54 /* >= NM2090 */ 151 #define NMCRTCX_PANEL_0x55 0x55 /* >= NM2090 */ 152 #define NMCRTCX_PANEL_0x56 0x56 /* >= NM2090 */ 153 #define NMCRTCX_PANEL_0x57 0x57 /* >= NM2090 */ 154 #define NMCRTCX_PANEL_0x58 0x58 /* >= NM2090 */ 155 #define NMCRTCX_PANEL_0x59 0x59 /* >= NM2090 */ 156 #define NMCRTCX_PANEL_0x60 0x60 /* >= NM2097(?) */ 157 #define NMCRTCX_PANEL_0x61 0x61 /* >= NM2097(?) */ 158 #define NMCRTCX_PANEL_0x62 0x62 /* >= NM2097(?) */ 159 #define NMCRTCX_PANEL_0x63 0x63 /* >= NM2097(?) */ 160 #define NMCRTCX_PANEL_0x64 0x64 /* >= NM2097(?) */ 161 #define NMCRTCX_VEXT 0x70 /* >= NM2200 */ 162 163 /* neomagic ISA SEQUENCER indexed registers */ 164 /* VGA standard registers: */ 165 #define NMSEQX_RESET 0x00 166 #define NMSEQX_CLKMODE 0x01 167 #define NMSEQX_MAPMASK 0x02 168 #define NMSEQX_MEMMODE 0x04 169 /* NeoMagic BES registers: (> NM2070) (accessible via mapped I/O: >= NM2097) */ 170 #define NMSEQX_BESCTRL2 0x08 171 #define NMSEQX_0x09 0x09 //?? 172 #define NMSEQX_ZVCAP_DSCAL 0x0a 173 #define NMSEQX_BUF2ORGL 0x0c 174 #define NMSEQX_BUF2ORGM 0x0d 175 #define NMSEQX_BUF2ORGH 0x0e 176 #define NMSEQX_VD2COORD1L 0x14 /* >= NM2200(?) */ 177 #define NMSEQX_VD2COORD2L 0x15 /* >= NM2200(?) */ 178 #define NMSEQX_VD2COORD21H 0x16 /* >= NM2200(?) */ 179 #define NMSEQX_HD2COORD1L 0x17 /* >= NM2200(?) */ 180 #define NMSEQX_HD2COORD2L 0x18 /* >= NM2200(?) */ 181 #define NMSEQX_HD2COORD21H 0x19 /* >= NM2200(?) */ 182 #define NMSEQX_BUF2PITCHL 0x1a 183 #define NMSEQX_BUF2PITCHH 0x1b 184 #define NMSEQX_0x1c 0x1c //?? 185 #define NMSEQX_0x1d 0x1d //?? 186 #define NMSEQX_0x1e 0x1e //?? 187 #define NMSEQX_0x1f 0x1f //?? 188 189 /* neomagic ISA ATTRIBUTE indexed registers */ 190 /* VGA standard registers: */ 191 #define NMATBX_MODECTL 0x10 192 #define NMATBX_OSCANCOLOR 0x11 193 #define NMATBX_COLPLANE_EN 0x12 194 #define NMATBX_HORPIXPAN 0x13 195 #define NMATBX_COLSEL 0x14 196 #define NMATBX_0x16 0x16 197 198 /* neomagic ISA GRAPHICS indexed registers */ 199 /* VGA standard registers: */ 200 #define NMGRPHX_ENSETRESET 0x01 201 #define NMGRPHX_DATAROTATE 0x03 202 #define NMGRPHX_READMAPSEL 0x04 203 #define NMGRPHX_MODE 0x05 204 #define NMGRPHX_MISC 0x06 205 #define NMGRPHX_BITMASK 0x08 206 /* NeoMagic specific registers: */ 207 #define NMGRPHX_GRPHXLOCK 0x09 208 #define NMGRPHX_GENLOCK 0x0a 209 #define NMGRPHX_FBSTADDE 0x0e 210 #define NMGRPHX_CRTC_PITCHE 0x0f /* > NM2070 */ 211 #define NMGRPHX_IFACECTRL1 0x10 212 #define NMGRPHX_IFACECTRL2 0x11 213 #define NMGRPHX_0x15 0x15 214 #define NMGRPHX_ACT_CLK_SAV 0x19 /* >= NM2200? auto-pwr-save.. (b2-0) */ 215 #define NMGRPHX_PANELCTRL1 0x20 216 #define NMGRPHX_PANELTYPE 0x21 217 #define NMGRPHX_PANELCTRL2 0x25 218 #define NMGRPHX_PANELVCENT1 0x28 219 #define NMGRPHX_PANELVCENT2 0x29 220 #define NMGRPHX_PANELVCENT3 0x2a 221 #define NMGRPHX_PANELCTRL3 0x30 /* > NM2070 */ 222 #define NMGRPHX_PANELVCENT4 0x32 /* > NM2070 */ 223 #define NMGRPHX_PANELHCENT1 0x33 /* > NM2070 */ 224 #define NMGRPHX_PANELHCENT2 0x34 /* > NM2070 */ 225 #define NMGRPHX_PANELHCENT3 0x35 /* > NM2070 */ 226 #define NMGRPHX_PANELHCENT4 0x36 /* >= NM2160 */ 227 #define NMGRPHX_PANELVCENT5 0x37 /* >= NM2200 */ 228 #define NMGRPHX_PANELHCENT5 0x38 /* >= NM2200 */ 229 #define NMGRPHX_CURCTRL 0x82 230 #define NMGRPHX_COLDEPTH 0x90 231 /* mem or core PLL register??? */ 232 #define NMGRPHX_SPEED 0x93 233 /* (NeoMagic pixelPLL set C registers) */ 234 #define NMGRPHX_PLLC_NH 0x8f /* >= NM2200 */ 235 #define NMGRPHX_PLLC_NL 0x9b 236 #define NMGRPHX_PLLC_M 0x9f 237 /* NeoMagic BES registers: (> NM2070) (accessible via mapped I/O: >= NM2097) */ 238 #define NMGRPHX_BESCTRL1 0xb0 239 #define NMGRPHX_HD1COORD21H 0xb1 240 #define NMGRPHX_HD1COORD1L 0xb2 241 #define NMGRPHX_HD1COORD2L 0xb3 242 #define NMGRPHX_VD1COORD21H 0xb4 243 #define NMGRPHX_VD1COORD1L 0xb5 244 #define NMGRPHX_VD1COORD2L 0xb6 245 #define NMGRPHX_BUF1ORGH 0xb7 246 #define NMGRPHX_BUF1ORGM 0xb8 247 #define NMGRPHX_BUF1ORGL 0xb9 248 #define NMGRPHX_BUF1PITCHH 0xba 249 #define NMGRPHX_BUF1PITCHL 0xbb 250 #define NMGRPHX_0xbc 0xbc //?? 251 #define NMGRPHX_0xbd 0xbd //?? 252 #define NMGRPHX_0xbe 0xbe //?? 253 #define NMGRPHX_0xbf 0xbf //?? 254 #define NMGRPHX_XSCALEH 0xc0 255 #define NMGRPHX_XSCALEL 0xc1 256 #define NMGRPHX_YSCALEH 0xc2 257 #define NMGRPHX_YSCALEL 0xc3 258 #define NMGRPHX_BRIGHTNESS 0xc4 259 #define NMGRPHX_COLKEY_R 0xc5 260 #define NMGRPHX_COLKEY_G 0xc6 261 #define NMGRPHX_COLKEY_B 0xc7 262 263 /* NeoMagic specific PCI cursor registers < NM2200 */ 264 #define NMCR1_CURCTRL 0x0100 265 #define NMCR1_CURX 0x0104 266 #define NMCR1_CURY 0x0108 267 #define NMCR1_CURBGCOLOR 0x010c 268 #define NMCR1_CURFGCOLOR 0x0110 269 #define NMCR1_CURADDRESS 0x0114 270 /* NeoMagic specific PCI cursor registers >= NM2200 */ 271 #define NMCR1_22CURCTRL 0x1000 272 #define NMCR1_22CURX 0x1004 273 #define NMCR1_22CURY 0x1008 274 #define NMCR1_22CURBGCOLOR 0x100c 275 #define NMCR1_22CURFGCOLOR 0x1010 276 #define NMCR1_22CURADDRESS 0x1014 277 278 /* NeoMagic PCI acceleration registers */ 279 /* all cards, but some registers only on 2090 and later; and some on 2200 and later */ 280 #define NMACC_STATUS 0x0000 281 #define NMACC_CONTROL 0x0004 282 #define NMACC_FGCOLOR 0x000c 283 #define NMACC_2200_SRC_PITCH 0x0014 284 #define NMACC_2090_CLIPLT 0x0018 285 #define NMACC_2090_CLIPRB 0x001c 286 #define NMACC_SRCSTARTOFF 0x0024 287 #define NMACC_2090_DSTSTARTOFF 0x002c 288 #define NMACC_2090_XYEXT 0x0030 289 /* NM2070 only */ 290 #define NMACC_2070_PLANEMASK 0x0014 291 #define NMACC_2070_XYEXT 0x0018 292 #define NMACC_2070_SRCPITCH 0x001c 293 #define NMACC_2070_SRCBITOFF 0x0020 294 #define NMACC_2070_DSTPITCH 0x0028 295 #define NMACC_2070_DSTBITOFF 0x002c 296 #define NMACC_2070_DSTSTARTOFF 0x0030 297 298 299 /* Macros for convenient accesses to the NM chips */ 300 301 /* primary PCI register area */ 302 #define NM_REG8(r_) ((vuint8 *)regs)[(r_)] 303 #define NM_REG16(r_) ((vuint16 *)regs)[(r_) >> 1] 304 #define NM_REG32(r_) ((vuint32 *)regs)[(r_) >> 2] 305 /* secondary PCI register area */ 306 #define NM_2REG8(r_) ((vuint8 *)regs2)[(r_)] 307 #define NM_2REG16(r_) ((vuint16 *)regs2)[(r_) >> 1] 308 #define NM_2REG32(r_) ((vuint32 *)regs2)[(r_) >> 2] 309 310 /* read and write to PCI config space */ 311 #define CFGR(A) (nm_pci_access.offset=NMCFG_##A, ioctl(fd,NM_GET_PCI, &nm_pci_access,sizeof(nm_pci_access)), nm_pci_access.value) 312 #define CFGW(A,B) (nm_pci_access.offset=NMCFG_##A, nm_pci_access.value = B, ioctl(fd,NM_SET_PCI,&nm_pci_access,sizeof(nm_pci_access))) 313 314 /* read and write from acceleration engine */ 315 #define ACCR(A) (NM_REG32(NMACC_##A)) 316 #define ACCW(A,B) (NM_REG32(NMACC_##A) = (B)) 317 318 /* read and write from first CRTC (mapped) */ 319 #define CR1R(A) (NM_REG32(NMCR1_##A)) 320 #define CR1W(A,B) (NM_REG32(NMCR1_##A) = (B)) 321 322 /* read and write from ISA I/O space */ 323 #define ISAWB(A,B)(nm_isa_access.adress=NMISA8_##A, nm_isa_access.data = (uint8)B, nm_isa_access.size = 1, ioctl(fd,NM_ISA_OUT, &nm_isa_access,sizeof(nm_isa_access))) 324 #define ISAWW(A,B)(nm_isa_access.adress=NMISA16_##A, nm_isa_access.data = B, nm_isa_access.size = 2, ioctl(fd,NM_ISA_OUT, &nm_isa_access,sizeof(nm_isa_access))) 325 #define ISARB(A) (nm_isa_access.adress=NMISA8_##A, ioctl(fd,NM_ISA_IN, &nm_isa_access,sizeof(nm_isa_access)), (uint8)nm_isa_access.data) 326 #define ISARW(A) (nm_isa_access.adress=NMISA16_##A, ioctl(fd,NM_ISA_IN, &nm_isa_access,sizeof(nm_isa_access)), nm_isa_access.data) 327 328 /* read and write from ISA CRTC indexed registers */ 329 #define ISACRTCW(A,B)(ISAWW(CRTCIND, ((NMCRTCX_##A) | ((B) << 8)))) 330 #define ISACRTCR(A) (ISAWB(CRTCIND, (NMCRTCX_##A)), ISARB(CRTCDAT)) 331 332 /* read and write from ISA GRAPHICS indexed registers */ 333 #define ISAGRPHW(A,B)(ISAWW(GRPHIND, ((NMGRPHX_##A) | ((B) << 8)))) 334 #define ISAGRPHR(A) (ISAWB(GRPHIND, (NMGRPHX_##A)), ISARB(GRPHDAT)) 335 336 /* read and write from PCI GRAPHICS indexed registers (>= NM2097) */ 337 #define PCIGRPHW(A,B)(NM_2REG16(NM2PCI16_GRPHIND) = ((NMGRPHX_##A) | ((B) << 8))) 338 #define PCIGRPHR(A) (NM_2REG8(NM2PCI8_GRPHIND) = (NMGRPHX_##A), NM_2REG8(NM2PCI8_GRPHDAT)) 339 340 /* read and write from ISA SEQUENCER indexed registers */ 341 #define ISASEQW(A,B)(ISAWW(SEQIND, ((NMSEQX_##A) | ((B) << 8)))) 342 #define ISASEQR(A) (ISAWB(SEQIND, (NMSEQX_##A)), ISARB(SEQDAT)) 343 344 /* read and write from PCI SEQUENCER indexed registers (>= NM2097) */ 345 #define PCISEQW(A,B)(NM_2REG16(NM2PCI16_SEQIND) = ((NMSEQX_##A) | ((B) << 8))) 346 #define PCISEQR(A) (NM_2REG8(NM2PCI8_SEQIND) = (NMSEQX_##A), NM_2REG8(NM2PCI8_SEQDAT)) 347 348 /* read and write from ISA ATTRIBUTE indexed registers */ 349 #define ISAATBW(A,B)((void)ISARB(INSTAT1), ISAWB(ATTRINDW, ((NMATBX_##A) | 0x20)), ISAWB(ATTRDATW, (B))) 350 #define ISAATBR(A) ((void)ISARB(INSTAT1), ISAWB(ATTRINDW, ((NMATBX_##A) | 0x20)), ISARB(ATTRDATR)) 351