xref: /haiku/src/add-ons/accelerants/ati/mach64.h (revision 124cdd4f576b15760ed343fddb0d6bb8efcaee27)
1 /*
2 	Haiku ATI video driver adapted from the X.org ATI driver which has the
3 	following copyright:
4 
5 	Copyright 1992,1993,1994,1995,1996,1997 by Kevin E. Martin, Chapel Hill, North Carolina.
6 
7 	Copyright 2009, 2011 Haiku, Inc.  All rights reserved.
8 	Distributed under the terms of the MIT license.
9 
10 	Authors:
11 	Gerald Zajac
12 */
13 
14 #ifndef __MACH64_H__
15 #define __MACH64_H__
16 
17 
18 #define CURSOR_BYTES	1024		// bytes used for cursor image in video memory
19 
20 // Memory types for Mach64 chips.
21 
22 enum Mach64_MemoryType
23 {
24     MEM_NONE,
25     MEM_DRAM,
26     MEM_EDO,
27     MEM_PSEUDO_EDO,
28     MEM_SDRAM,
29     MEM_SGRAM,
30     MEM_SGRAM32,
31     MEM_TYPE_7
32 };
33 
34 
35 // Macros to get/set a contiguous bit field.  Arguments should not be
36 // self-modifying.
37 
38 #define UnitOf(___Value) (((((___Value) ^ ((___Value) - 1)) + 1) >> 1) \
39 						| ((((___Value) ^ ((___Value) - 1)) >> 1) + 1))
40 
41 #define GetBits(__Value, _Mask) (((__Value) & (_Mask)) / UnitOf(_Mask))
42 #define SetBits(__Value, _Mask) (((__Value) * UnitOf(_Mask)) & (_Mask))
43 
44 
45 // Register MMIO addresses - expressed in BYTE offsets.
46 //-----------------------------------------------------
47 
48 #define CRTC_H_TOTAL_DISP		(0x0c00 + 0x0000)	// Dword offset 00
49 #define CRTC_H_SYNC_STRT_WID	(0x0c00 + 0x0004)	// Dword offset 01
50 #define CRTC_V_TOTAL_DISP		(0x0c00 + 0x0008)	// Dword offset 02
51 #define CRTC_V_SYNC_STRT_WID	(0x0c00 + 0x000C)	// Dword offset 03
52 #define CRTC_VLINE_CRNT_VLINE	(0x0c00 + 0x0010)	// Dword offset 04
53 #define CRTC_OFF_PITCH			(0x0c00 + 0x0014)	// Dword offset 05
54 #define CRTC_INT_CNTL			(0x0c00 + 0x0018)	// Dword offset 06
55 #define CRTC_GEN_CNTL			(0x0c00 + 0x001C)	// Dword offset 07
56 
57 #define DSP_CONFIG				(0x0c00 + 0x0020)	// Dword offset 08
58 #define DSP_ON_OFF				(0x0c00 + 0x0024)	// Dword offset 09
59 
60 #define SHARED_CNTL 			(0x0c00 + 0x0038)	// Dword offset 0E
61 
62 #define OVR_CLR 				(0x0c00 + 0x0040)	// Dword offset 10
63 #define OVR_WID_LEFT_RIGHT		(0x0c00 + 0x0044)	// Dword offset 11
64 #define OVR_WID_TOP_BOTTOM		(0x0c00 + 0x0048)	// Dword offset 12
65 
66 #define CUR_CLR0				(0x0c00 + 0x0060)	// Dword offset 18
67 #define CUR_CLR1				(0x0c00 + 0x0064)	// Dword offset 19
68 #define CUR_OFFSET				(0x0c00 + 0x0068)	// Dword offset 1A
69 #define CUR_HORZ_VERT_POSN		(0x0c00 + 0x006C)	// Dword offset 1B
70 #define CUR_HORZ_VERT_OFF		(0x0c00 + 0x0070)	// Dword offset 1C
71 
72 #define HW_DEBUG				(0x0c00 + 0x007C)	// Dword offset 1F
73 
74 #define SCRATCH_REG0			(0x0c00 + 0x0080)	// Dword offset 20
75 #define SCRATCH_REG1			(0x0c00 + 0x0084)	// Dword offset 21
76 
77 #define CLOCK_CNTL				(0x0c00 + 0x0090)	// Dword offset 24
78 
79 #define BUS_CNTL				(0x0c00 + 0x00A0)	// Dword offset 28
80 
81 #define LCD_INDEX				(0x0c00 + 0x00A4)	// Dword offset 29
82 #define LCD_DATA				(0x0c00 + 0x00A8)	// Dword offset 2A
83 
84 #define MEM_CNTL				(0x0c00 + 0x00B0)	// Dword offset 2C
85 
86 #define MEM_VGA_WP_SEL			(0x0c00 + 0x00B4)	// Dword offset 2D
87 #define MEM_VGA_RP_SEL			(0x0c00 + 0x00B8)	// Dword offset 2E
88 
89 #define DAC_REGS				(0x0c00 + 0x00C0)	// Dword offset 30
90 #define DAC_W_INDEX				(DAC_REGS + 0)
91 #define DAC_DATA				(DAC_REGS + 1)
92 #define DAC_MASK				(DAC_REGS + 2)
93 #define DAC_R_INDEX				(DAC_REGS + 3)
94 #define DAC_CNTL				(0x0c00 + 0x00C4)	// Dword offset 31
95 
96 #define GEN_TEST_CNTL			(0x0c00 + 0x00D0)	// Dword offset 34
97 
98 #define CONFIG_CNTL				(0x0c00 + 0x00DC	// Dword offset 37 (CT, ET, VT)
99 #define CONFIG_CHIP_ID			(0x0c00 + 0x00E0)	// Dword offset 38
100 #define CONFIG_STAT0			(0x0c00 + 0x00E4)	// Dword offset 39
101 #define CONFIG_STAT1			(0x0c00 + 0x00E8)	// Dword offset 3A
102 
103 #define DST_OFF_PITCH			(0x0c00 + 0x0100)	// Dword offset 40
104 #define DST_X					(0x0c00 + 0x0104)	// Dword offset 41
105 #define DST_Y					(0x0c00 + 0x0108)	// Dword offset 42
106 #define DST_Y_X 				(0x0c00 + 0x010C)	// Dword offset 43
107 #define DST_WIDTH				(0x0c00 + 0x0110)	// Dword offset 44
108 #define DST_HEIGHT				(0x0c00 + 0x0114)	// Dword offset 45
109 #define DST_HEIGHT_WIDTH		(0x0c00 + 0x0118)	// Dword offset 46
110 #define DST_X_WIDTH 			(0x0c00 + 0x011C)	// Dword offset 47
111 #define DST_BRES_LNTH			(0x0c00 + 0x0120)	// Dword offset 48
112 #define DST_BRES_ERR			(0x0c00 + 0x0124)	// Dword offset 49
113 #define DST_BRES_INC			(0x0c00 + 0x0128)	// Dword offset 4A
114 #define DST_BRES_DEC			(0x0c00 + 0x012C)	// Dword offset 4B
115 #define DST_CNTL				(0x0c00 + 0x0130)	// Dword offset 4C
116 
117 #define SRC_OFF_PITCH			(0x0c00 + 0x0180)	// Dword offset 60
118 #define SRC_X					(0x0c00 + 0x0184)	// Dword offset 61
119 #define SRC_Y					(0x0c00 + 0x0188)	// Dword offset 62
120 #define SRC_Y_X 				(0x0c00 + 0x018C)	// Dword offset 63
121 #define SRC_WIDTH1				(0x0c00 + 0x0190)	// Dword offset 64
122 #define SRC_HEIGHT1 			(0x0c00 + 0x0194)	// Dword offset 65
123 #define SRC_HEIGHT1_WIDTH1		(0x0c00 + 0x0198)	// Dword offset 66
124 #define SRC_X_START 			(0x0c00 + 0x019C)	// Dword offset 67
125 #define SRC_Y_START 			(0x0c00 + 0x01A0)	// Dword offset 68
126 #define SRC_Y_X_START			(0x0c00 + 0x01A4)	// Dword offset 69
127 #define SRC_WIDTH2				(0x0c00 + 0x01A8)	// Dword offset 6A
128 #define SRC_HEIGHT2 			(0x0c00 + 0x01AC)	// Dword offset 6B
129 #define SRC_HEIGHT2_WIDTH2		(0x0c00 + 0x01B0)	// Dword offset 6C
130 #define SRC_CNTL				(0x0c00 + 0x01B4)	// Dword offset 6D
131 
132 #define HOST_DATA0				(0x0c00 + 0x0200)	// Dword offset 80
133 #define HOST_DATA1				(0x0c00 + 0x0204)	// Dword offset 81
134 #define HOST_DATA2				(0x0c00 + 0x0208)	// Dword offset 82
135 #define HOST_DATA3				(0x0c00 + 0x020C)	// Dword offset 83
136 #define HOST_DATA4				(0x0c00 + 0x0210)	// Dword offset 84
137 #define HOST_DATA5				(0x0c00 + 0x0214)	// Dword offset 85
138 #define HOST_DATA6				(0x0c00 + 0x0218)	// Dword offset 86
139 #define HOST_DATA7				(0x0c00 + 0x021C)	// Dword offset 87
140 #define HOST_DATA8				(0x0c00 + 0x0220)	// Dword offset 88
141 #define HOST_DATA9				(0x0c00 + 0x0224)	// Dword offset 89
142 #define HOST_DATAA				(0x0c00 + 0x0228)	// Dword offset 8A
143 #define HOST_DATAB				(0x0c00 + 0x022C)	// Dword offset 8B
144 #define HOST_DATAC				(0x0c00 + 0x0230)	// Dword offset 8C
145 #define HOST_DATAD				(0x0c00 + 0x0234)	// Dword offset 8D
146 #define HOST_DATAE				(0x0c00 + 0x0238)	// Dword offset 8E
147 #define HOST_DATAF				(0x0c00 + 0x023C)	// Dword offset 8F
148 #define HOST_CNTL				(0x0c00 + 0x0240)	// Dword offset 90
149 
150 #define PAT_REG0				(0x0c00 + 0x0280)	// Dword offset A0
151 #define PAT_REG1				(0x0c00 + 0x0284)	// Dword offset A1
152 #define PAT_CNTL				(0x0c00 + 0x0288)	// Dword offset A2
153 
154 #define SC_LEFT 				(0x0c00 + 0x02A0)	// Dword offset A8
155 #define SC_RIGHT				(0x0c00 + 0x02A4)	// Dword offset A9
156 #define SC_LEFT_RIGHT			(0x0c00 + 0x02A8)	// Dword offset AA
157 #define SC_TOP					(0x0c00 + 0x02AC)	// Dword offset AB
158 #define SC_BOTTOM				(0x0c00 + 0x02B0)	// Dword offset AC
159 #define SC_TOP_BOTTOM			(0x0c00 + 0x02B4)	// Dword offset AD
160 
161 #define DP_BKGD_CLR 			(0x0c00 + 0x02C0)	// Dword offset B0
162 #define DP_FRGD_CLR 			(0x0c00 + 0x02C4)	// Dword offset B1
163 #define DP_WRITE_MASK			(0x0c00 + 0x02C8)	// Dword offset B2
164 #define DP_CHAIN_MASK			(0x0c00 + 0x02CC)	// Dword offset B3
165 #define DP_PIX_WIDTH			(0x0c00 + 0x02D0)	// Dword offset B4
166 #define DP_MIX					(0x0c00 + 0x02D4)	// Dword offset B5
167 #define DP_SRC					(0x0c00 + 0x02D8)	// Dword offset B6
168 
169 #define CLR_CMP_CLR 			(0x0c00 + 0x0300)	// Dword offset C0
170 #define CLR_CMP_MASK			(0x0c00 + 0x0304)	// Dword offset C1
171 #define CLR_CMP_CNTL			(0x0c00 + 0x0308)	// Dword offset C2
172 
173 #define FIFO_STAT				(0x0c00 + 0x0310)	// Dword offset C4
174 
175 #define CONTEXT_MASK			(0x0c00 + 0x0320)	// Dword offset C8
176 #define CONTEXT_LOAD_CNTL		(0x0c00 + 0x032C)	// Dword offset CB
177 
178 #define GUI_TRAJ_CNTL			(0x0c00 + 0x0330)	// Dword offset CC
179 #define GUI_STAT				(0x0c00 + 0x0338)	// Dword offset CE
180 
181 
182 // Definitions used for overlays.
183 //===============================
184 
185 #define REG_BLOCK_1	0x0800		// offset of register block 1 in register area
186 
187 #define OVERLAY_Y_X_START		(REG_BLOCK_1 + 0x0000)	// Dword offset 00
188 #define OVERLAY_LOCK_START		0x80000000ul
189 #define OVERLAY_Y_X_END			(REG_BLOCK_1 + 0x0004)	// Dword offset 01
190 #define OVERLAY_GRAPHICS_KEY_CLR (REG_BLOCK_1 + 0x0010)	// Dword offset 04
191 #define OVERLAY_GRAPHICS_KEY_MSK (REG_BLOCK_1 + 0x0014)	// Dword offset 05
192 #define OVERLAY_KEY_CNTL		(REG_BLOCK_1 + 0x0018)	// Dword offset 06
193 #define OVERLAY_MIX_FALSE		0x00
194 #define OVERLAY_MIX_EQUAL		0x50
195 #define OVERLAY_SCALE_INC		(REG_BLOCK_1 + 0x0020)	// Dword offset 08
196 #define OVERLAY_SCALE_CNTL		(REG_BLOCK_1 + 0x0024)	// Dword offset 09
197 #define SCALE_PIX_EXPAND		0x00000001
198 #define OVERLAY_EN				0x40000000
199 #define SCALE_EN				0x80000000
200 #define SCALER_HEIGHT_WIDTH		(REG_BLOCK_1 + 0x0028)	// Dword offset 0a
201 #define SCALER_BUF0_OFFSET		(REG_BLOCK_1 + 0x0034)	// Dword offset 0d
202 #define SCALER_BUF0_PITCH		(REG_BLOCK_1 + 0x003c)	// Dword offset 0f
203 #define VIDEO_FORMAT			(REG_BLOCK_1 + 0x0048)	// Dword offset 12
204 #define SCALE_IN_VYUY422		0x000b0000
205 #define BUF0_OFFSET				(REG_BLOCK_1 + 0x0080)	// Dword offset 20
206 #define BUF0_PITCH				(REG_BLOCK_1 + 0x008c)	// Dword offset 23
207 #define SCALER_COLOUR_CNTL		(REG_BLOCK_1 + 0x0150)	// Dword offset 54
208 #define SCALER_H_COEFF0			(REG_BLOCK_1 + 0x0154)	// Dword offset 55
209 #define SCALER_H_COEFF1			(REG_BLOCK_1 + 0x0158)	// Dword offset 56
210 #define SCALER_H_COEFF2			(REG_BLOCK_1 + 0x015c)	// Dword offset 57
211 #define SCALER_H_COEFF3			(REG_BLOCK_1 + 0x0160)	// Dword offset 58
212 #define SCALER_H_COEFF4			(REG_BLOCK_1 + 0x0164)	// Dword offset 59
213 
214 
215 // CRTC control values.
216 
217 #define CRTC_H_SYNC_NEG			0x00200000
218 #define CRTC_V_SYNC_NEG			0x00200000
219 
220 #define CRTC_DBL_SCAN_EN		0x00000001
221 #define CRTC_INTERLACE_EN		0x00000002
222 #define CRTC_HSYNC_DIS			0x00000004
223 #define CRTC_VSYNC_DIS			0x00000008
224 #define CRTC_CSYNC_EN			0x00000010
225 #define CRTC_PIX_BY_2_EN		0x00000020
226 #define CRTC_DISPLAY_DIS		0x00000040
227 #define CRTC_VGA_XOVERSCAN		0x00000080
228 
229 #define CRTC_PIX_WIDTH			0x00000700
230 #define CRTC_PIX_WIDTH_4BPP		0x00000100
231 #define CRTC_PIX_WIDTH_8BPP		0x00000200
232 #define CRTC_PIX_WIDTH_15BPP	0x00000300
233 #define CRTC_PIX_WIDTH_16BPP	0x00000400
234 #define CRTC_PIX_WIDTH_24BPP	0x00000500
235 #define CRTC_PIX_WIDTH_32BPP	0x00000600
236 
237 #define CRTC_BYTE_PIX_ORDER		0x00000800
238 #define CRTC_PIX_ORDER_MSN_LSN	0x00000000
239 #define CRTC_PIX_ORDER_LSN_MSN	0x00000800
240 
241 #define CRTC_FIFO_LWM			0x000f0000
242 #define CRTC2_PIX_WIDTH			0x000e0000
243 #define CRTC_VGA_128KAP_PAGING	0x00100000
244 #define CRTC_VFC_SYNC_TRISTATE	0x00200000
245 #define CRTC2_EN				0x00200000
246 #define CRTC_LOCK_REGS			0x00400000
247 #define CRTC_SYNC_TRISTATE		0x00800000
248 #define CRTC_EXT_DISP_EN		0x01000000
249 #define CRTC_EN					0x02000000
250 #define CRTC_DISP_REQ_EN		0x04000000
251 #define CRTC_VGA_LINEAR			0x08000000
252 #define CRTC_VGA_TEXT_132		0x20000000
253 #define CRTC_CNT_EN				0x40000000
254 #define CRTC_CUR_B_TEST			0x80000000
255 
256 #define CRTC_CRNT_VLINE			0x07f00000
257 #define CRTC_VBLANK				0x00000001
258 
259 #define CRTC_PITCH				0xffc00000
260 
261 // DAC control values.
262 #define DAC_8BIT_EN				0x00000100
263 
264 
265 // Mix control values.
266 #define MIX_NOT_DST				0x0000
267 #define MIX_0 					0x0001
268 #define MIX_1 					0x0002
269 #define MIX_DST					0x0003
270 #define MIX_NOT_SRC				0x0004
271 #define MIX_XOR					0x0005
272 #define MIX_XNOR				0x0006
273 #define MIX_SRC					0x0007
274 #define MIX_NAND				0x0008
275 #define MIX_NOT_SRC_OR_DST		0x0009
276 #define MIX_SRC_OR_NOT_DST		0x000a
277 #define MIX_OR					0x000b
278 #define MIX_AND					0x000c
279 #define MIX_SRC_AND_NOT_DST		0x000d
280 #define MIX_NOT_SRC_AND_DST		0x000e
281 #define MIX_NOR					0x000f
282 
283 // BUS_CNTL register constants.
284 #define BUS_FIFO_ERR_ACK		0x00200000
285 #define BUS_HOST_ERR_ACK		0x00800000
286 #define BUS_EXT_REG_EN			0x08000000
287 
288 // GEN_TEST_CNTL register constants.
289 #define GEN_OVR_OUTPUT_EN		0x20
290 #define HWCURSOR_ENABLE 		0x80
291 #define GUI_ENGINE_ENABLE		0x100
292 
293 // DSP_CONFIG register constants.
294 #define DSP_XCLKS_PER_QW		0x00003fff
295 #define DSP_LOOP_LATENCY		0x000f0000
296 #define DSP_PRECISION			0x00700000
297 
298 // DSP_ON_OFF register constants.
299 #define DSP_OFF 				0x000007ff
300 #define DSP_ON					0x07ff0000
301 
302 // CLOCK_CNTL register constants.
303 #define CLOCK_SEL		0x0f
304 #define CLOCK_DIV		0x30
305 #define CLOCK_DIV1		0x00
306 #define CLOCK_DIV2		0x10
307 #define CLOCK_DIV4		0x20
308 #define CLOCK_STROBE	0x40
309 #define PLL_WR_EN		0x02
310 #define PLL_ADDR		0xfc
311 
312 // PLL registers.
313 #define PLL_MACRO_CNTL		0x01
314 #define PLL_REF_DIV			0x02
315 #define PLL_GEN_CNTL		0x03
316 #define PLL_MCLK_FB_DIV		0x04
317 #define PLL_VCLK_CNTL		0x05
318 #define PLL_VCLK_POST_DIV	0x06
319 #define PLL_VCLK0_FB_DIV	0x07
320 #define PLL_VCLK1_FB_DIV	0x08
321 #define PLL_VCLK2_FB_DIV	0x09
322 #define PLL_VCLK3_FB_DIV	0x0A
323 #define PLL_XCLK_CNTL		0x0B
324 #define PLL_TEST_CTRL		0x0E
325 #define PLL_TEST_COUNT		0x0F
326 
327 // Fields in PLL registers.
328 #define PLL_PC_GAIN			0x07
329 #define PLL_VC_GAIN			0x18
330 #define PLL_DUTY_CYC		0xE0
331 #define PLL_MFB_TIMES_4_2B	0x08
332 #define PLL_VCLK0_XDIV		0x10
333 #define PLL_OVERRIDE		0x01
334 #define PLL_MCLK_RST		0x02
335 #define OSC_EN				0x04
336 #define EXT_CLK_EN			0x08
337 #define MCLK_SRC_SEL		0x70
338 #define EXT_CLK_CNTL		0x80
339 #define PLL_VCLK_SRC_SEL	0x03
340 #define PLL_VCLK_RESET		0x04
341 #define VCLK_INVERT			0x08
342 #define VCLK0_POST			0x03
343 #define VCLK1_POST			0x0C
344 #define VCLK2_POST			0x30
345 #define VCLK3_POST			0xC0
346 
347 // MEM_CNTL register constants.
348 #define CTL_MEM_TRP			0x00000300
349 #define CTL_MEM_TRCD		0x00000C00
350 #define CTL_MEM_TCRD		0x00001000
351 #define CTL_MEM_TRAS		0x00070000
352 
353 // DST_CNTL register constants.
354 #define DST_X_LEFT_TO_RIGHT		1
355 #define DST_Y_TOP_TO_BOTTOM		2
356 #define DST_LAST_PEL				0x20
357 
358 // SRC_CNTL register constants.
359 #define SRC_LINE_X_LEFT_TO_RIGHT	0x10
360 
361 // HOST_CNTL register constants.
362 #define HOST_BYTE_ALIGN			1
363 
364 // DP_CHAIN_MASK register constants.
365 #define DP_CHAIN_4BPP			0x8888
366 #define DP_CHAIN_7BPP			0xD2D2
367 #define DP_CHAIN_8BPP			0x8080
368 #define DP_CHAIN_8BPP_RGB		0x9292
369 #define DP_CHAIN_15BPP		0x4210
370 #define DP_CHAIN_16BPP		0x8410
371 #define DP_CHAIN_24BPP		0x8080
372 #define DP_CHAIN_32BPP		0x8080
373 
374 // DP_PIX_WIDTH register constants.
375 #define DST_1BPP			0
376 #define DST_4BPP			1
377 #define DST_8BPP			2
378 #define DST_15BPP 			3
379 #define DST_16BPP 			4
380 #define DST_32BPP 			6
381 #define SRC_1BPP			0
382 #define SRC_4BPP			0x100
383 #define SRC_8BPP			0x200
384 #define SRC_15BPP 			0x300
385 #define SRC_16BPP 			0x400
386 #define SRC_32BPP 			0x600
387 #define HOST_1BPP 			0
388 #define HOST_4BPP 			0x10000
389 #define HOST_8BPP 			0x20000
390 #define HOST_15BPP			0x30000
391 #define HOST_16BPP			0x40000
392 #define HOST_32BPP			0x60000
393 #define BYTE_ORDER_MSB_TO_LSB 0
394 #define BYTE_ORDER_LSB_TO_MSB 0x1000000
395 
396 // DP_SRC register constants.
397 #define BKGD_SRC_BKGD_CLR 	0
398 #define FRGD_SRC_FRGD_CLR 	0x100
399 #define FRGD_SRC_BLIT 		0x300
400 #define MONO_SRC_ONE		0
401 
402 // GUI_STAT register constants.
403 #define ENGINE_BUSY 		1
404 
405 // LCD Index register constants.
406 #define LCD_REG_INDEX		0x0000003F
407 #define LCD_DISPLAY_DIS		0x00000100
408 #define LCD_SRC_SEL			0x00000200
409 #define CRTC2_DISPLAY_DIS	0x00000400
410 
411 // LCD register indices.
412 #define LCD_CONFIG_PANEL		0x00
413 #define LCD_GEN_CNTL			0x01
414 #define LCD_DSTN_CONTROL		0x02
415 #define LCD_HFB_PITCH_ADDR		0x03
416 #define LCD_HORZ_STRETCHING		0x04
417 #define LCD_VERT_STRETCHING		0x05
418 #define LCD_EXT_VERT_STRETCH	0x06
419 #define LCD_LT_GIO				0x07
420 #define LCD_POWER_MANAGEMENT	0x08
421 
422 // LCD_CONFIG_PANEL register constants.
423 #define DONT_SHADOW_HEND	0x00004000
424 
425 // LCD_GEN_CNTL register constants.
426 #define CRT_ON				0x00000001
427 #define LCD_ON				0x00000002
428 #define HORZ_DIVBY2_EN		0x00000004
429 #define LOCK_8DOT			0x00000010
430 #define DONT_SHADOW_VPAR	0x00000040
431 #define DIS_HOR_CRT_DIVBY2	0x00000400
432 #define MCLK_PM_EN			0x00010000
433 #define VCLK_DAC_PM_EN		0x00020000
434 #define CRTC_RW_SELECT		0x08000000
435 #define USE_SHADOWED_VEND	0x10000000
436 #define USE_SHADOWED_ROWCUR	0x20000000
437 #define SHADOW_EN			0x40000000
438 #define SHADOW_RW_EN		0x80000000
439 
440 // LCD_HORZ_STRETCHING register constants.
441 #define HORZ_STRETCH_BLEND	0x00000fff
442 #define HORZ_STRETCH_RATIO	0x0000ffff
443 #define HORZ_STRETCH_LOOP	0x00070000
444 #define HORZ_PANEL_SIZE		0x0ff00000
445 #define AUTO_HORZ_RATIO		0x20000000
446 #define HORZ_STRETCH_MODE	0x40000000
447 #define HORZ_STRETCH_EN		0x80000000
448 
449 // LCD_VERT_STRETCHING register constants.
450 #define VERT_STRETCH_RATIO0	0x000003ff
451 #define VERT_STRETCH_RATIO1	0x000ffc00
452 #define VERT_STRETCH_RATIO2	0x3ff00000
453 #define VERT_STRETCH_USE0	0x40000000
454 #define VERT_STRETCH_EN		0x80000000
455 
456 // LCD_EXT_VERT_STRETCH register constants.
457 #define VERT_STRETCH_RATIO3	0x000003ff
458 #define FORCE_DAC_DATA		0x000000ff
459 #define FORCE_DAC_DATA_SEL	0x00000300
460 #define VERT_STRETCH_MODE	0x00000400
461 #define VERT_PANEL_SIZE		0x003ff800
462 #define AUTO_VERT_RATIO		0x00400000
463 #define USE_AUTO_FP_POS		0x00800000
464 #define USE_AUTO_LCD_VSYNC	0x01000000
465 
466 // LCD_POWER_MANAGEMENT register constants.
467 #define AUTO_POWER_UP		0x00000008
468 #define POWER_BLON			0x02000000
469 #define STANDBY_NOW			0x10000000
470 #define SUSPEND_NOW			0x20000000
471 
472 
473 
474 // Functions to get/set PLL registers.
475 //=======================================
476 
477 static inline uint8
Mach64_GetPLLReg(uint8 index)478 Mach64_GetPLLReg(uint8 index)
479 {
480 	OUTREG8(CLOCK_CNTL + 1, (index << 2) & PLL_ADDR);
481 	return INREG8(CLOCK_CNTL + 2);
482 }
483 
484 
485 static inline void
Mach64_SetPLLReg(uint8 index,uint8 value)486 Mach64_SetPLLReg(uint8 index, uint8 value)
487 {
488 	OUTREG8(CLOCK_CNTL + 1, ((index << 2) & PLL_ADDR) | PLL_WR_EN);
489 	OUTREG8(CLOCK_CNTL + 2, value);
490 }
491 
492 
493 static inline uint32
Mach64_GetLCDReg(int index)494 Mach64_GetLCDReg(int index)
495 {
496 	OUTREG8(LCD_INDEX, index & LCD_REG_INDEX);
497 	return INREG(LCD_DATA);
498 }
499 
500 
501 static inline void
Mach64_PutLCDReg(int index,uint32 value)502 Mach64_PutLCDReg(int index, uint32 value)
503 {
504 	OUTREG8(LCD_INDEX, index & LCD_REG_INDEX);
505 	OUTREG(LCD_DATA, value);
506 }
507 
508 
509 #endif	// __MACH64_H__
510