1 /* 2 * Copyright 2012-2013, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Alexander von Gluck IV, kallisti5@unixzen.com 7 */ 8 #ifndef _INTEL_POWER_H_ 9 #define _INTEL_POWER_H_ 10 11 12 #include <string.h> 13 14 #include "driver.h" 15 16 17 // Clocking configuration 18 #define INTEL6_GT_THREAD_STATUS_REG 0x13805c 19 #define INTEL6_GT_THREAD_STATUS_CORE_MASK 0x7 20 #define INTEL6_GT_THREAD_STATUS_CORE_MASK_HSW (0x7 | (0x07 << 16)) 21 #define INTEL6_GT_PERF_STATUS 0x145948 22 #define INTEL6_RP_STATE_LIMITS 0x145994 23 #define INTEL6_RP_STATE_CAP 0x145998 24 #define INTEL6_RPNSWREQ 0xA008 25 #define INTEL6_TURBO_DISABLE (1<<31) 26 #define INTEL6_FREQUENCY(x) ((x)<<25) 27 #define INTEL6_OFFSET(x) ((x)<<19) 28 #define INTEL6_AGGRESSIVE_TURBO (0<<15) 29 #define INTEL6_RC_VIDEO_FREQ 0xA00C 30 #define INTEL6_RC_CONTROL 0xA090 31 #define INTEL6_RC_CTL_RC6pp_ENABLE (1<<16) 32 #define INTEL6_RC_CTL_RC6p_ENABLE (1<<17) 33 #define INTEL6_RC_CTL_RC6_ENABLE (1<<18) 34 #define INTEL6_RC_CTL_RC1e_ENABLE (1<<20) 35 #define INTEL6_RC_CTL_RC7_ENABLE (1<<22) 36 #define INTEL6_RC_CTL_EI_MODE(x) ((x)<<27) 37 #define INTEL6_RC_CTL_HW_ENABLE (1<<31) 38 #define INTEL6_RP_DOWN_TIMEOUT 0xA010 39 #define INTEL6_RP_INTERRUPT_LIMITS 0xA014 40 #define INTEL6_RPSTAT1 0xA01C 41 #define INTEL6_CAGF_SHIFT 8 42 #define INTEL6_CAGF_MASK (0x7f << INTEL6_CAGF_SHIFT) 43 #define INTEL6_RP_CONTROL 0xA024 44 #define INTEL6_RP_MEDIA_TURBO (1<<11) 45 #define INTEL6_RP_MEDIA_MODE_MASK (3<<9) 46 #define INTEL6_RP_MEDIA_HW_TURBO_MODE (3<<9) 47 #define INTEL6_RP_MEDIA_HW_NORMAL_MODE (2<<9) 48 #define INTEL6_RP_MEDIA_HW_MODE (1<<9) 49 #define INTEL6_RP_MEDIA_SW_MODE (0<<9) 50 #define INTEL6_RP_MEDIA_IS_GFX (1<<8) 51 #define INTEL6_RP_ENABLE (1<<7) 52 #define INTEL6_RP_UP_IDLE_MIN (0x1<<3) 53 #define INTEL6_RP_UP_BUSY_AVG (0x2<<3) 54 #define INTEL6_RP_UP_BUSY_CONT (0x4<<3) 55 #define GEN7_RP_DOWN_IDLE_AVG (0x2<<0) 56 #define INTEL6_RP_DOWN_IDLE_CONT (0x1<<0) 57 #define INTEL6_RP_UP_THRESHOLD 0xA02C 58 #define INTEL6_RP_DOWN_THRESHOLD 0xA030 59 #define INTEL6_RP_CUR_UP_EI 0xA050 60 #define INTEL6_CURICONT_MASK 0xffffff 61 #define INTEL6_RP_CUR_UP 0xA054 62 #define INTEL6_CURBSYTAVG_MASK 0xffffff 63 #define INTEL6_RP_PREV_UP 0xA058 64 #define INTEL6_RP_CUR_DOWN_EI 0xA05C 65 #define INTEL6_CURIAVG_MASK 0xffffff 66 #define INTEL6_RP_CUR_DOWN 0xA060 67 #define INTEL6_RP_PREV_DOWN 0xA064 68 #define INTEL6_RP_UP_EI 0xA068 69 #define INTEL6_RP_DOWN_EI 0xA06C 70 #define INTEL6_RP_IDLE_HYSTERSIS 0xA070 71 #define INTEL6_RC_STATE 0xA094 72 #define INTEL6_RC1_WAKE_RATE_LIMIT 0xA098 73 #define INTEL6_RC6_WAKE_RATE_LIMIT 0xA09C 74 #define INTEL6_RC6pp_WAKE_RATE_LIMIT 0xA0A0 75 #define INTEL6_RC_EVALUATION_INTERVAL 0xA0A8 76 #define INTEL6_RC_IDLE_HYSTERSIS 0xA0AC 77 #define INTEL6_RC_SLEEP 0xA0B0 78 #define INTEL6_RC1e_THRESHOLD 0xA0B4 79 #define INTEL6_RC6_THRESHOLD 0xA0B8 80 #define INTEL6_RC6p_THRESHOLD 0xA0BC 81 #define INTEL6_RC6pp_THRESHOLD 0xA0C0 82 #define INTEL6_PMINTRMSK 0xA168 83 #define INTEL6_PMISR 0x44020 84 #define INTEL6_PMIMR 0x44024 /* rps_lock */ 85 #define INTEL6_PMIIR 0x44028 86 #define INTEL6_PMIER 0x4402C 87 #define INTEL6_PM_MBOX_EVENT (1<<25) 88 #define INTEL6_PM_THERMAL_EVENT (1<<24) 89 #define INTEL6_PM_RP_DOWN_TIMEOUT (1<<6) 90 #define INTEL6_PM_RP_UP_THRESHOLD (1<<5) 91 #define INTEL6_PM_RP_DOWN_THRESHOLD (1<<4) 92 #define INTEL6_PM_RP_UP_EI_EXPIRED (1<<2) 93 #define INTEL6_PM_RP_DOWN_EI_EXPIRED (1<<1) 94 #define INTEL6_PM_DEFERRED_EVENTS (INTEL6_PM_RP_UP_THRESHOLD \ 95 | INTEL6_PM_RP_DOWN_THRESHOLD \ 96 | INTEL6_PM_RP_DOWN_TIMEOUT) 97 #define INTEL6_GT_GFX_RC6_LOCKED 0x138104 98 #define INTEL6_GT_GFX_RC6 0x138108 99 #define INTEL6_GT_GFX_RC6p 0x13810C 100 #define INTEL6_GT_GFX_RC6pp 0x138110 101 #define INTEL6_PCODE_MAILBOX 0x138124 102 #define INTEL6_PCODE_READY (1<<31) 103 #define INTEL6_READ_OC_PARAMS 0xc 104 #define INTEL6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 105 #define INTEL6_PCODE_READ_MIN_FREQ_TABLE 0x9 106 #define INTEL6_PCODE_DATA 0x138128 107 #define INTEL6_PCODE_FREQ_IA_RATIO_SHIFT 8 108 #define INTEL6_GT_CORE_STATUS 0x138060 109 #define INTEL6_CORE_CPD_STATE_MASK (7<<4) 110 #define INTEL6_RCn_MASK 7 111 #define INTEL6_RC0 0 112 #define INTEL6_RC3 2 113 #define INTEL6_RC6 3 114 #define INTEL6_RC7 4 115 116 117 status_t intel_en_gating(intel_info &info); 118 status_t intel_en_downclock(intel_info &info); 119 120 121 #endif /* _INTEL_POWER_H_ */