1 /* 2 * Copyright 2002/03, Thomas Kurschel. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 */ 5 #ifndef __ATA_TYPES_H__ 6 #define __ATA_TYPES_H__ 7 8 9 #include <iovec.h> 10 #include <lendian_bitfield.h> 11 12 13 // ATA task file. 14 // contains the command block interpreted under different conditions with 15 // first byte being first command register, second byte second command register 16 // etc.; for lba48, registers must be written twice, therefore there 17 // are twice as many bytes as registers - the first eight bytes are those 18 // that must be written first, the second eight bytes are those that 19 // must be written second. 20 union ata_task_file { 21 struct { 22 uint8 features; 23 uint8 sector_count; 24 uint8 sector_number; 25 uint8 cylinder_0_7; 26 uint8 cylinder_8_15; 27 B_LBITFIELD8_3( 28 head : 4, 29 device : 1, 30 mode : 3 31 ); 32 uint8 command; 33 } chs; 34 struct { 35 uint8 features; 36 uint8 sector_count; 37 uint8 lba_0_7; 38 uint8 lba_8_15; 39 uint8 lba_16_23; 40 B_LBITFIELD8_3( 41 lba_24_27 : 4, 42 device : 1, 43 mode : 3 44 ); 45 uint8 command; 46 } lba; 47 struct { 48 B_LBITFIELD8_3( 49 dma : 1, 50 ovl : 1, 51 _0_res2 : 6 52 ); 53 B_LBITFIELD8_2( 54 _1_res0 : 3, 55 tag : 5 56 ); 57 uint8 _2_res; 58 uint8 byte_count_0_7; 59 uint8 byte_count_8_15; 60 B_LBITFIELD8_6( 61 lun : 3, 62 _5_res3 : 1, 63 device : 1, 64 _5_one5 : 1, 65 _5_res6 : 1, 66 _5_one7 : 1 67 ); 68 uint8 command; 69 } packet; 70 struct { 71 B_LBITFIELD8_5( 72 ili : 1, 73 eom : 1, 74 abrt : 1, 75 _0_res3 : 1, 76 sense_key : 4 77 ); 78 B_LBITFIELD8_4( 79 cmd_or_data : 1, // 1 - cmd, 0 - data 80 input_or_output : 1, // 0 - input (to device), 1 - output 81 release : 1, 82 tag : 5 83 ); 84 uint8 _2_res; 85 uint8 byte_count_0_7; 86 uint8 byte_count_8_15; 87 B_LBITFIELD8_5( 88 _4_res0 : 4, 89 device : 1, 90 _4_obs5 : 1, 91 _4_res6 : 1, 92 _4_obs7 : 1 93 ); 94 B_LBITFIELD8_7( 95 chk : 1, 96 _7_res1 : 2, 97 drq : 1, 98 serv : 1, 99 dmrd : 1, 100 drdy : 1, 101 bsy : 1 102 ); 103 } packet_res; 104 struct { 105 uint8 sector_count; 106 B_LBITFIELD8_4( // only <tag> is defined for write 107 cmd_or_data : 1, // 1 - cmd, 0 - data 108 input_or_output : 1, // 0 - input (to device), 1 - output 109 release : 1, 110 tag : 5 111 ); 112 uint8 lba_0_7; 113 uint8 lba_8_15; 114 uint8 lba_16_23; 115 B_LBITFIELD8_3( 116 lba_24_27 : 4, 117 device : 1, 118 mode : 3 119 ); 120 uint8 command; 121 } queued; 122 struct { 123 // low order bytes 124 uint8 features; 125 uint8 sector_count_0_7; 126 uint8 lba_0_7; 127 uint8 lba_8_15; 128 uint8 lba_16_23; 129 B_LBITFIELD8_3( 130 _5low_res0 : 4, 131 device : 1, 132 mode : 3 133 ); 134 uint8 command; 135 136 // high order bytes 137 uint8 _0high_res; 138 uint8 sector_count_8_15; 139 uint8 lba_24_31; 140 uint8 lba_32_39; 141 uint8 lba_40_47; 142 } lba48; 143 struct { 144 // low order bytes 145 uint8 sector_count_0_7; 146 B_LBITFIELD8_4( 147 cmd_or_data : 1, // 1 - cmd, 0 - data 148 input_or_output : 1, // 0 - input (to device), 1 - output 149 release : 1, 150 tag : 5 151 ); 152 uint8 lba_0_7; 153 uint8 lba_8_15; 154 uint8 lba_16_23; 155 B_LBITFIELD8_3( 156 _5low_res0 : 4, 157 device : 1, 158 mode : 3 159 ); 160 uint8 command; 161 162 // high order bytes 163 uint8 sector_count_8_15; 164 uint8 _1high_res; 165 uint8 lba_24_31; 166 uint8 lba_32_39; 167 uint8 lba_40_47; 168 } queued48; 169 struct { 170 uint8 r[7+5]; 171 } raw; 172 struct { 173 uint8 features; 174 uint8 sector_count; 175 uint8 sector_number; 176 uint8 cylinder_low; 177 uint8 cylinder_high; 178 uint8 device_head; 179 uint8 command; 180 } write; 181 struct { 182 uint8 error; 183 uint8 sector_count; 184 uint8 sector_number; 185 uint8 cylinder_low; 186 uint8 cylinder_high; 187 uint8 device_head; 188 uint8 status; 189 } read; 190 }; 191 192 typedef union ata_task_file ata_task_file; 193 194 // content of "mode" field 195 enum { 196 ATA_MODE_CHS = 5, 197 ATA_MODE_LBA = 7 198 }; 199 200 // mask for ata_task_file fields to be written 201 enum { 202 ATA_MASK_FEATURES = 0x01, 203 ATA_MASK_SECTOR_COUNT = 0x02, 204 205 // CHS 206 ATA_MASK_SECTOR_NUMBER = 0x04, 207 ATA_MASK_CYLINDER_LOW = 0x08, 208 ATA_MASK_CYLINDER_HIGH = 0x10, 209 210 // LBA 211 ATA_MASK_LBA_LOW = 0x04, 212 ATA_MASK_LBA_MID = 0x08, 213 ATA_MASK_LBA_HIGH = 0x10, 214 215 // packet 216 ATA_MASK_BYTE_COUNT = 0x18, 217 218 // packet and dma queued result 219 ATA_MASK_ERROR = 0x01, 220 ATA_MASK_INTERRUPT_REASON = 0x02, 221 222 ATA_MASK_DEVICE_HEAD = 0x20, 223 ATA_MASK_COMMAND = 0x40, 224 225 ATA_MASK_STATUS = 0x40, 226 227 // for 48 bits, the following flags tell which registers to load twice 228 ATA_MASK_FEATURES_48 = 0x80 | ATA_MASK_FEATURES, 229 ATA_MASK_SECTOR_COUNT_48 = 0x100 | ATA_MASK_SECTOR_COUNT, 230 ATA_MASK_LBA_LOW_48 = 0x200 | ATA_MASK_LBA_LOW, 231 ATA_MASK_LBA_MID_48 = 0x400 | ATA_MASK_LBA_MID, 232 ATA_MASK_LBA_HIGH_48 = 0x800 | ATA_MASK_LBA_HIGH, 233 234 ATA_MASK_HOB = 0xf80 235 }; 236 237 // status register 238 enum { 239 ATA_STATUS_ERROR = 0x01, // error 240 ATA_STATUS_INDEX = 0x02, // obsolete 241 ATA_STATUS_CORR = 0x04, // obsolete 242 ATA_STATUS_DATA_REQUEST = 0x08, // data request 243 ATA_STATUS_DSC = 0x10, // reserved 244 ATA_STATUS_SERVICE = 0x10, // ready to service device 245 ATA_STATUS_DWF = 0x20, // reserved 246 ATA_STATUS_DMA = 0x20, // reserved 247 ATA_STATUS_DMA_READY = 0x20, // packet: DMA ready 248 ATA_STATUS_DEVICE_FAULT = 0x20, // device fault 249 ATA_STATUS_DEVICE_READY = 0x40, // device ready 250 ATA_STATUS_BUSY = 0x80 // busy 251 }; 252 253 // device control register (ATA command block) 254 enum { 255 // bit 0 must be zero 256 ATA_DEVICE_CONTROL_DISABLE_INTS = 0x02, // disable INTRQ 257 ATA_DEVICE_CONTROL_SOFT_RESET = 0x04, // software device reset 258 ATA_DEVICE_CONTROL_BIT3 = 0x08, // obsolete. Must always be set 259 // bits inbetween are reserved 260 ATA_DEVICE_CONTROL_HIGH_ORDER_BYTE = 0x80 // read high order byte 261 // (for 48-bit lba) 262 }; 263 264 // error register - most bits are command specific 265 enum { 266 // always used 267 ATA_ERROR_ABORTED = 0x04, // command aborted 268 269 // used for Ultra DMA modes 270 ATA_ERROR_INTERFACE_CRC = 0x80, // interface CRC error 271 272 // used by reading data transfers 273 ATA_ERROR_UNCORRECTABLE = 0x40, // uncorrectable data error 274 // used by writing data transfers 275 ATA_ERROR_WRITE_PROTECTED = 0x40, // media write protect 276 277 // used by all data transfer commands 278 ATA_ERROR_MEDIUM_CHANGED = 0x20, // medium changed 279 ATA_ERROR_INVALID_ADDRESS = 0x10, // invalid CHS address 280 ATA_ERROR_MEDIA_CHANGE_REQUESTED = 0x08, // media change requested 281 ATA_ERROR_NO_MEDIA = 0x02, // no media 282 283 ATA_ERROR_ALL = 0xfe 284 }; 285 286 typedef struct ata_channel_info *ata_channel_cookie; 287 288 #endif /* __ATA_TYPES_H__ */ 289