78 	SetRegister(VIP_ADC_CNTL, ADC_CPRESET, ADC_CPRESET);  in SetEnable()
80 	SetRegister(VIP_ADC_CNTL, ADC_CPRESET, 0);  in SetEnable()
82 	SetRegister(VIP_ADC_CNTL, ADC_PDWN, ADC_PDWN_DOWN);  in SetEnable()
100 	SetRegister(VIP_ADC_CNTL, ADC_PDWN, ADC_PDWN);  in SetEnable()
124 		SetRegister(VIP_ADC_CNTL, ADC_PDWN, ADC_PDWN_UP);  in SetEnable()
340 		SetRegister(VIP_ADC_CNTL, INPUT_SELECT, fTunerPort);  in SetADC()
344 		SetRegister(VIP_ADC_CNTL, INPUT_SELECT, fCompositePort);  in SetADC()
348 		SetRegister(VIP_ADC_CNTL, INPUT_SELECT, fSVideoPort);  in SetADC()
356 	SetRegister(VIP_ADC_CNTL, I_CLAMP_SEL, I_CLAMP_SEL_22);  in SetADC()
357 	SetRegister(VIP_ADC_CNTL, I_AGC_SEL, I_AGC_SEL_7);  in SetADC()
359 	SetRegister(VIP_ADC_CNTL, EXT_CLAMP_CAP, EXT_CLAMP_CAP_EXTERNAL);  in SetADC()
360 	SetRegister(VIP_ADC_CNTL, EXT_AGC_CAP, EXT_AGC_CAP_EXTERNAL);  in SetADC()
361 	SetRegister(VIP_ADC_CNTL, ADC_DECI_BYPASS, ADC_DECI_WITH_FILTER);  in SetADC()
362 	SetRegister(VIP_ADC_CNTL, VBI_DECI_BYPASS, VBI_DECI_WITH_FILTER);  in SetADC()
363 	SetRegister(VIP_ADC_CNTL, DECI_DITHER_EN, 0 << 12);  in SetADC()
364 	SetRegister(VIP_ADC_CNTL, ADC_CLK_SEL, ADC_CLK_SEL_8X);  in SetADC()
365 	SetRegister(VIP_ADC_CNTL, ADC_BYPASS, ADC_BYPASS_INTERNAL);  in SetADC()
371 		SetRegister(VIP_ADC_CNTL, ADC_CH_GAIN_SEL, ADC_CH_GAIN_SEL_NTSC);  in SetADC()
378 		SetRegister(VIP_ADC_CNTL, ADC_CH_GAIN_SEL, ADC_CH_GAIN_SEL_PAL);  in SetADC()
381 	SetRegister(VIP_ADC_CNTL, ADC_PAICM, 1 << 18);  in SetADC()
383 	SetRegister(VIP_ADC_CNTL, ADC_PDCBIAS, 2 << 20);  in SetADC()
384 	SetRegister(VIP_ADC_CNTL, ADC_PREFHI, ADC_PREFHI_2_7);  in SetADC()
385 	SetRegister(VIP_ADC_CNTL, ADC_PREFLO, ADC_PREFLO_1_5);  in SetADC()
387 	SetRegister(VIP_ADC_CNTL, ADC_IMUXOFF, 0 << 26);  in SetADC()
388 	SetRegister(VIP_ADC_CNTL, ADC_CPRESET, 0 << 27);  in SetADC()