Lines Matching refs:blocks
668 uint32* blocks = info.shared_info->register_blocks; in intel_extreme_init() local
669 blocks[REGISTER_BLOCK(REGS_FLAT)] = 0; in intel_extreme_init()
674 blocks[REGISTER_BLOCK(REGS_NORTH_SHARED)] in intel_extreme_init()
676 blocks[REGISTER_BLOCK(REGS_NORTH_PIPE_AND_PORT)] in intel_extreme_init()
678 blocks[REGISTER_BLOCK(REGS_NORTH_PLANE_CONTROL)] in intel_extreme_init()
680 blocks[REGISTER_BLOCK(REGS_SOUTH_SHARED)] in intel_extreme_init()
682 blocks[REGISTER_BLOCK(REGS_SOUTH_TRANSCODER_PORT)] in intel_extreme_init()
686 blocks[REGISTER_BLOCK(REGS_NORTH_SHARED)] in intel_extreme_init()
688 blocks[REGISTER_BLOCK(REGS_NORTH_PIPE_AND_PORT)] in intel_extreme_init()
690 blocks[REGISTER_BLOCK(REGS_NORTH_PLANE_CONTROL)] in intel_extreme_init()
692 blocks[REGISTER_BLOCK(REGS_SOUTH_SHARED)] in intel_extreme_init()
694 blocks[REGISTER_BLOCK(REGS_SOUTH_TRANSCODER_PORT)] in intel_extreme_init()
701 blocks[REGISTER_BLOCK(REGS_SOUTH_SHARED)] += VLV_DISPLAY_BASE; in intel_extreme_init()
702 blocks[REGISTER_BLOCK(REGS_SOUTH_TRANSCODER_PORT)] += VLV_DISPLAY_BASE; in intel_extreme_init()
706 blocks[REGISTER_BLOCK(REGS_NORTH_SHARED)]); in intel_extreme_init()
708 blocks[REGISTER_BLOCK(REGS_NORTH_PIPE_AND_PORT)]); in intel_extreme_init()
710 blocks[REGISTER_BLOCK(REGS_NORTH_PLANE_CONTROL)]); in intel_extreme_init()
712 blocks[REGISTER_BLOCK(REGS_SOUTH_SHARED)]); in intel_extreme_init()
714 blocks[REGISTER_BLOCK(REGS_SOUTH_TRANSCODER_PORT)]); in intel_extreme_init()