Lines Matching refs:m_max
390 int m = 0, n = 0, p = 0, m_max, p_max; in eng_dac_sys_pll_find() local
405 m_max = 14; in eng_dac_sys_pll_find()
418 if (req_sclk > 340.0) m_max = 2; /* Fpll > 340Mhz */ in eng_dac_sys_pll_find()
419 else if (req_sclk > 200.0) m_max = 4; /* 200Mhz < Fpll <= 340Mhz */ in eng_dac_sys_pll_find()
420 else if (req_sclk > 150.0) m_max = 6; /* 150Mhz < Fpll <= 200Mhz */ in eng_dac_sys_pll_find()
421 else m_max = 14; /* Fpll < 150Mhz */ in eng_dac_sys_pll_find()
434 if (req_sclk > 340.0) m_max = 2; /* Fpll > 340Mhz */ in eng_dac_sys_pll_find()
435 else if (req_sclk > 250.0) m_max = 6; /* 250Mhz < Fpll <= 340Mhz */ in eng_dac_sys_pll_find()
436 else m_max = 14; /* Fpll < 250Mhz */ in eng_dac_sys_pll_find()
450 LOG(4,("DAC: PLL reference frequency postscaler divider range is 1 - %d\n", m_max)); in eng_dac_sys_pll_find()
484 for (m = 1; m <= m_max; m++) in eng_dac_sys_pll_find()